JPH11176860A - Solder bump structure and its forming method - Google Patents
Solder bump structure and its forming methodInfo
- Publication number
- JPH11176860A JPH11176860A JP33898797A JP33898797A JPH11176860A JP H11176860 A JPH11176860 A JP H11176860A JP 33898797 A JP33898797 A JP 33898797A JP 33898797 A JP33898797 A JP 33898797A JP H11176860 A JPH11176860 A JP H11176860A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- current film
- film
- metal layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 150000001875 compounds Chemical class 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000000206 photolithography Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 40
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000003960 organic solvent Substances 0.000 description 4
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体ウエハ上
のハンダバンプ構造とその形成方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder bump structure on a semiconductor wafer and a method for forming the same.
【０００２】[0002]
【従来の技術】図３は、従来のハンダバンプ構造を示す
拡大図である。図４は、半導体ウエハ上のハンダバンプ
の形成方法を示す図である。１は図示しない電子回路が
搭載される半導体ウエハ、２は半導体ウエハ１上に形成
され、図示しない電子回路から入出力を行う電極部、３
は半導体ウエハ１上に形成され、図示しない電子回路を
埃やくずから守る保護膜である。４は半導体ウエハ１の
電極部２がある面全面に蒸着法やスパッタリング法を用
いてアルミニウム、チタン、クロム、銅、ニッケル等の
金属膜を一層又は多層に形成し、電解メッキのために設
けたカレントフィルムである。2. Description of the Related Art FIG. 3 is an enlarged view showing a conventional solder bump structure. FIG. 4 is a diagram showing a method of forming solder bumps on a semiconductor wafer. Reference numeral 1 denotes a semiconductor wafer on which an electronic circuit (not shown) is mounted, 2 denotes an electrode portion formed on the semiconductor wafer 1 and performs input / output from an electronic circuit (not shown),
Is a protective film formed on the semiconductor wafer 1 to protect an electronic circuit (not shown) from dust and debris. Reference numeral 4 denotes a single-layer or multi-layer metal film of aluminum, titanium, chromium, copper, nickel or the like formed by vapor deposition or sputtering over the entire surface of the semiconductor wafer 1 where the electrode portion 2 is located, and provided for electrolytic plating This is the current film.
【０００３】５はメッキする箇所に開口部６を有し、メ
ッキしない箇所を保護するフォトレジストである。７は
ハンダバンプ９とカレントフィルム４との濡れ性を向上
させて接合強度を大きくするために設けられたハンダ下
地層である。ハンダ下地層７は、電極部２の幅より狭く
することが好ましい。理由は、保護膜３は電極部２の端
の上部に段差を生じるため、この端までハンダ下地層７
を形成すると、ハンダ下地層７にクラックを生じること
があるためである。又、ハンダ下地層７は、ハンダ成分
と温度により拡散を起こし、化合物となりやすいような
材料から成り、例えば銅が用いられることが多い。[0005] Reference numeral 5 denotes a photoresist having an opening 6 at a portion to be plated and protecting a portion not to be plated. Reference numeral 7 denotes a solder base layer provided for improving the wettability between the solder bumps 9 and the current film 4 to increase the bonding strength. It is preferable that the solder base layer 7 be narrower than the width of the electrode portion 2. The reason is that the protective film 3 has a step above the end of the electrode portion 2, and thus the solder base layer 7 is formed up to this end.
This is because cracks may be generated in the solder underlayer 7 when forming the layer. The solder base layer 7 is made of a material that easily diffuses due to a solder component and temperature, and is likely to be a compound. For example, copper is often used.
【０００４】８はハンダ下地層７の上にニッケル等のハ
ンダと前記化合物を作りにくい金属より構成される金属
層である。尚、この化合物は強度が弱く、脆い。又、ハ
ンダ下地層７と金属層８と２層に分けた理由は、前述し
た理由の他に、カレントフィルム４とハンダ下地層７、
ハンダ下地層７と金属層８それぞれの密着性が充分であ
る必要があるためである。又、金属層８は電極部２上の
保護膜３よりも内側に端があるとするとカレントフィル
ム４は除去するので、電極部２がむき出しの状態とな
る。Numeral 8 denotes a metal layer formed on the solder base layer 7 by a solder such as nickel and a metal which is difficult to form the compound. This compound has low strength and is brittle. The reason why the solder underlayer 7 and the metal layer 8 are divided into two layers is that the current film 4 and the solder underlayer 7,
This is because the adhesion between the solder base layer 7 and the metal layer 8 needs to be sufficient. If the metal layer 8 has an edge inside the protective film 3 on the electrode portion 2, the current film 4 is removed, so that the electrode portion 2 is exposed.
【０００５】半導体ウエハ１上全面にカレントフィルム
を形成した状態を図４（ａ）に示す。カレントフィルム
４は電極部２と保護膜３との密着性が充分である必要が
あり、非常に薄いもので、厚さは、約０．５μｍ以下で
ある。FIG. 4A shows a state in which a current film is formed on the entire surface of the semiconductor wafer 1. The current film 4 needs to have sufficient adhesion between the electrode portion 2 and the protective film 3 and is very thin, and has a thickness of about 0.5 μm or less.
【０００６】次の工程を図４（ｂ）に示す。カレントフ
ィルム４上にフォトレジスト５を塗布し、フォトリソ工
程により電極部２上に開口部６を形成する。この開口部
６のカレントフィルム４上にハンダ下地層７、金属層８
を形成する。The next step is shown in FIG. A photoresist 5 is applied on the current film 4 and an opening 6 is formed on the electrode 2 by a photolithography process. A solder base layer 7 and a metal layer 8 are formed on the current film 4 in the opening 6.
To form
【０００７】図４（ｂ）の次の工程を図４（ｃ）に示
す。開口部６にハンダバンプ９をマッシュルーム形状に
形成する。フォトレジスト５を有機溶剤を用いて除去
し、さらにカレントフィルム４の不要部をエッチングに
より除去する。この場合、前述したように、電極部２が
むき出しの状態だと電極部２まで除去されてしまう。従
って、電極部２はカレントフィルム４、ハンダ下地層
７、金属層８にて覆われていなければならない。FIG. 4C shows a step subsequent to FIG. 4B. A solder bump 9 is formed in the opening 6 in a mushroom shape. The photoresist 5 is removed using an organic solvent, and unnecessary portions of the current film 4 are removed by etching. In this case, as described above, if the electrode portion 2 is exposed, even the electrode portion 2 is removed. Therefore, the electrode section 2 must be covered with the current film 4, the solder base layer 7, and the metal layer 8.
【０００８】ハンダバンプ構造の最終の状態を図３、図
４（ｄ）に示す。リフローを行いハンダバンプ９を球形
に整形する。FIGS. 3 and 4D show the final state of the solder bump structure. Reflow is performed to shape the solder bump 9 into a spherical shape.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、ハンダ
下地層７とハンダバンプ９を全て前述した形成方法で形
成した後リフロー整形すると、図３に示すようにハンダ
がハンダ下地層７の壁面に接触する構造となる。この箇
所で前記化合物が形成され、接合強度や接続信頼性の低
下、接続箇所の抵抗値の増大を引き起こすことになる。
従って、本発明はハンダバンプ構造の接合強度や接続信
頼性の向上、接続箇所の抵抗値の低減を目的とする。However, when the solder underlayer 7 and the solder bumps 9 are all formed by the above-described forming method and then subjected to reflow shaping, the solder contacts the wall surface of the solder underlayer 7 as shown in FIG. Becomes The compound is formed at this location, causing a decrease in bonding strength and connection reliability and an increase in the resistance value of the connection location.
Accordingly, an object of the present invention is to improve the bonding strength and connection reliability of a solder bump structure and reduce the resistance value at a connection point.
【００１０】[0010]
【課題を解決するための手段】電子回路が搭載される半
導体ウエハ上に電子回路からの入出力を行う電極部と、
電極部の周辺部を含む半導体ウエハ上に保護膜を形成す
る。ついで、電極部上の保護膜形成面上にカレントフィ
ルムを形成する。次に、電極部と保護膜が重なる箇所の
カレントフィルム上に端を備えたハンダ下地層を順次形
成する。更に、カレントフィルムとハンダ下地層の露出
部を覆い、ハンダと合わせても化合物には成らない金属
層と、金属層を覆うようなハンダバンプを順次形成す
る。An electrode unit for inputting and outputting data from an electronic circuit on a semiconductor wafer on which the electronic circuit is mounted;
A protective film is formed on a semiconductor wafer including a peripheral part of the electrode part. Next, a current film is formed on the protective film forming surface on the electrode portion. Next, a solder base layer having an end is sequentially formed on the current film where the electrode portion and the protective film overlap. Further, a metal layer which covers the exposed portion of the current film and the solder underlayer, and which does not become a compound even when combined with solder, and a solder bump which covers the metal layer are formed sequentially.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。図１は、本発明のハン
ダバンプ構造を示す拡大図である。図２は、本発明の第
１の実施の形態を示す図である。従来の技術と同等なも
のについては同一符号を付ける。５ａはフォトレジス
ト、６ａは開口部、８ａは金属層である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged view showing a solder bump structure of the present invention. FIG. 2 is a diagram showing a first embodiment of the present invention. The same reference numerals are given to those equivalent to the conventional technology. 5a is a photoresist, 6a is an opening, and 8a is a metal layer.
【００１２】以上のように構成された本発明の第１の実
施の形態の形成方法の説明を図２を参照しながら説明す
る。半導体ウエハ１上全面にカレントフィルムを形成し
た状態を図２（ａ）に示す。A description will be given, with reference to FIG. 2, of a forming method according to the first embodiment of the present invention configured as described above. FIG. 2A shows a state in which a current film is formed on the entire surface of the semiconductor wafer 1.
【００１３】次の工程を図２（ｂ）に示す。まず、カレ
ントフィルム４上にフォトレジスト５を塗布し、フォト
リソ工程により電極部２上に開口部６を形成する。この
開口部６のカレントフィルム４上にフォトレジスト５を
感光させずにハンダ下地層７をメッキする。The next step is shown in FIG. First, a photoresist 5 is applied on the current film 4 and an opening 6 is formed on the electrode 2 by a photolithography process. The solder base layer 7 is plated on the current film 4 in the opening 6 without exposing the photoresist 5 to light.
【００１４】図２（ｂ）の次の工程を図２（ｃ）に示
す。メッキ後、フォトリソ工程の現像を再度行い、フォ
トレジスト５ａの開口部６ａを形成する。この場合、開
口部６ａの周囲を開口部６より金属層８ａの平面部の厚
さ程度広げるように形成する。その後、ニッケル等のハ
ンダと合わせても前記化合物には成らない金属層８ａを
形成する。この結果、ハンダ下地層７の露出部は金属層
８ａにて覆われる。この時、カレントフィルム４の露出
部も金属層８ａにて覆われる。FIG. 2C shows a step subsequent to FIG. 2B. After the plating, the development in the photolithography process is performed again to form the opening 6a of the photoresist 5a. In this case, the opening 6a is formed so as to be wider than the opening 6 by the thickness of the plane portion of the metal layer 8a. Thereafter, a metal layer 8a that does not become the compound even when combined with solder such as nickel is formed. As a result, the exposed portion of the solder underlayer 7 is covered with the metal layer 8a. At this time, the exposed portion of the current film 4 is also covered with the metal layer 8a.
【００１５】図２（ｃ）の次の工程を図２（ｄ）に示
す。開口部６ａにハンダバンプ９をマッシュルーム状に
形成する。その後、フォトレジスト５ａを有機溶剤を用
いて除去し、更に不要部分のカレントフィルム４のエッ
チングを行う。最後に図１、図２（ｅ）に示すように、
リフローを行いハンダを球形に整形する。FIG. 2D shows a step subsequent to FIG. 2C. A solder bump 9 is formed in the opening 6a in a mushroom shape. Thereafter, the photoresist 5a is removed using an organic solvent, and the unnecessary portion of the current film 4 is etched. Finally, as shown in FIGS. 1 and 2 (e),
Perform reflow to shape the solder into a sphere.
【００１６】ここで、ハンダ下地層７の壁面への金属層
８ａの厚さが薄すぎると金属層８ａの効果が無くなり、
ハンダ下地層７とハンダバンプ９が前記化合物となる。
又、厚すぎると開口部６ａが広くなりすぎてしまい、結
果としてハンダバンプ９が大きくなり、高密度実装がで
きなくなる。そのため、ハンダ下地層７の壁面への金属
層８ａの厚さはハンダ下地層７への平面部の厚さと同等
にする。Here, if the thickness of the metal layer 8a on the wall surface of the solder underlayer 7 is too thin, the effect of the metal layer 8a is lost,
The solder underlayer 7 and the solder bumps 9 are the compounds.
On the other hand, if the thickness is too large, the opening 6a becomes too wide, and as a result, the solder bump 9 becomes large, and high-density mounting cannot be performed. Therefore, the thickness of the metal layer 8a on the wall surface of the solder underlayer 7 is made equal to the thickness of the plane portion on the solder underlayer 7.
【００１７】以上のように、ハンダバンプ９とハンダ下
地層７が接触する部分が無くなる。この結果、前記化合
物の生成を防ぐことができ、ハンダバンプ９の接続信頼
性を向上でき、又、接続箇所の抵抗値を低減できる。As described above, there is no portion where the solder bump 9 and the solder underlayer 7 come into contact with each other. As a result, the generation of the compound can be prevented, the connection reliability of the solder bump 9 can be improved, and the resistance value of the connection portion can be reduced.
【００１８】次に、本発明の第２の実施の形態について
図面を参照しながら説明する。図面は図２を用いる。半
導体ウエハ１上全面にカレントフィルムを形成した状態
を図２（ａ）に示す。Next, a second embodiment of the present invention will be described with reference to the drawings. Drawing 2 uses FIG. FIG. 2A shows a state in which a current film is formed on the entire surface of the semiconductor wafer 1.
【００１９】次の工程を図２（ｂ）に示す。まず、カレ
ントフィルム４上にフォトレジスト５を塗布し、フォト
リソ工程により電極部２上に開口部６を形成する。この
開口部６のカレントフィルム４上にハンダ下地層７をメ
ッキする。The next step is shown in FIG. First, a photoresist 5 is applied on the current film 4 and an opening 6 is formed on the electrode 2 by a photolithography process. A solder base layer 7 is plated on the current film 4 in the opening 6.
【００２０】図２（ｂ）の次の工程を図２（ｃ）に示
す。図２（ｂ）の工程でフォトレジスト５を感光させる
と、半導体ウエハ１への処理ができなくなる。そのた
め、フォトレジスト５を有機溶剤を用いて除去し、フォ
トレジスト５ａを塗布する。更に、フォトリソ工程を行
い、ハンダ下地層７上に開口部６ａを設ける。開口部６
ａの周囲を、開口部６より第１の実施の形態のように、
金属層８ａの平面部の厚さ程度広げるようにマスクパタ
ーンを用い形成する。FIG. 2C shows a step subsequent to that of FIG. 2B. If the photoresist 5 is exposed in the step of FIG. 2B, processing on the semiconductor wafer 1 cannot be performed. Therefore, the photoresist 5 is removed using an organic solvent, and a photoresist 5a is applied. Further, a photolithography process is performed to provide an opening 6 a on the solder base layer 7. Opening 6
a around the opening a through the opening 6 as in the first embodiment,
The metal layer 8a is formed using a mask pattern so as to be widened by about the thickness of the plane portion.
【００２１】その後、ニッケル等のハンダと合わせても
前記化合物を生成しない金属により金属層８ａをメッキ
する。ここで、ハンダ下地層７の上層である金属層８ａ
はカレントフィルム４の露出部とハンダ下地層７の壁面
にも形成される構造になる。Thereafter, the metal layer 8a is plated with a metal which does not form the compound even when combined with solder such as nickel. Here, the metal layer 8a which is the upper layer of the solder base layer 7
Is formed on the exposed portion of the current film 4 and also on the wall surface of the solder base layer 7.
【００２２】図２（ｃ）の次の工程を図２（ｄ）に示
す。更に、その上にハンダバンプ９をマッシュルーム状
に形成する。その後、フォトレジスト５ａを有機溶剤を
用いて除去し、更に不要部分のカレントフィルム４のエ
ッチングを行う。最後に図１、図２（ｅ）に示すよう
に、リフローを行いハンダを球形に整形する。FIG. 2D shows a step subsequent to that of FIG. 2C. Further, a solder bump 9 is formed thereon in a mushroom shape. Thereafter, the photoresist 5a is removed using an organic solvent, and the unnecessary portion of the current film 4 is etched. Finally, as shown in FIGS. 1 and 2 (e), reflow is performed to shape the solder into a spherical shape.
【００２３】以上のように第２の実施の形態では、ハン
ダバンプ９とハンダ下地層７が接触する部分が無くな
る。この結果、前記化合物の生成を防ぐことができ、ハ
ンダバンプ９の接続信頼性を向上でき、又、接続箇所の
抵抗値を低減できる。As described above, in the second embodiment, there is no portion where the solder bump 9 and the solder base layer 7 are in contact with each other. As a result, the generation of the compound can be prevented, the connection reliability of the solder bump 9 can be improved, and the resistance value of the connection portion can be reduced.
【００２４】第１、第２の実施の形態において、電極部
２の上面から見た形状は任意にしてよい。すなわち、こ
の形状は円形、多角形等のどれにしてもよい。In the first and second embodiments, the shape of the electrode section 2 as viewed from the upper surface may be arbitrary. That is, this shape may be any of a circle, a polygon, and the like.
【００２５】更に、図１又は図２（ｅ）で、カレントフ
ィルム４とハンダバンプ９が接触する箇所がある。カレ
ントフィルム４の材料は、ハンダと前記化合物となりや
すい銅があると述べた。しかし、カレントフィルム４は
前述したように、約０．５μｍ以下と非常に薄い。又、
ハンダ下地層７の厚さは１０μｍ以下程度、金属層８ａ
の厚さは５μｍ以下程度である。従って、カレントフィ
ルム４とハンダバンプ９の壁面での接触箇所は、無視で
きる。Further, in FIG. 1 or FIG. 2E, there is a portion where the current film 4 and the solder bump 9 come into contact. It was stated that the material of the current film 4 includes solder and copper which is likely to be the compound. However, the current film 4 is as thin as about 0.5 μm or less as described above. or,
The thickness of the solder base layer 7 is about 10 μm or less, and the thickness of the metal
Is about 5 μm or less. Therefore, the contact point between the current film 4 and the wall surface of the solder bump 9 can be ignored.
【００２６】[0026]
【発明の効果】以上のように、本発明の実施の形態で
は、ハンダバンプとハンダ下地層が接触する部分が無く
なる。この結果、化合物の生成を防ぐことができ、ハン
ダバンプ構造の接続強度や接続信頼性を向上でき、又、
接続箇所の抵抗値を低減できる。As described above, in the embodiment of the present invention, there is no portion where the solder bumps and the solder underlayer are in contact with each other. As a result, generation of a compound can be prevented, connection strength and connection reliability of the solder bump structure can be improved, and
The resistance value at the connection point can be reduced.
【図１】本発明のハンダバンプの構造を示す拡大図であ
る。FIG. 1 is an enlarged view showing a structure of a solder bump of the present invention.
【図２】本発明の実施の形態を示す図である。FIG. 2 is a diagram showing an embodiment of the present invention.
【図３】従来のハンダバンプの構造を示す拡大図であ
る。FIG. 3 is an enlarged view showing a structure of a conventional solder bump.
【図４】従来のハンダバンプ形成方法を示す図である。FIG. 4 is a view showing a conventional solder bump forming method.
１…半導体ウエハ ２…電極部 ３…保護膜 ４…カレントフィルム ７…ハンダ下地層 ８ａ…金属層 ９…ハンダバンプ DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer 2 ... Electrode part 3 ... Protective film 4 ... Current film 7 ... Solder underlayer 8a ... Metal layer 9 ... Solder bump
Claims (2)
らの入出力を行う電極部と、 前記電極部の周辺部を含む前記半導体ウエハ上に保護膜
と、 前記電極部上の前記保護膜を含む箇所の上にカレントフ
ィルムと、 前記電極部と前記保護膜が重なる箇所の前記カレントフ
ィルム上に端を備えたハンダ下地層と、 前記カレントフィルムと前記ハンダ下地層の露出部を覆
い、ハンダと合わせても化合物には成らない金属層と、 前記金属層を覆うようなハンダバンプと、 を順次形成することを特徴とするハンダバンプ構造。An electrode unit for inputting and outputting data from the electronic circuit on a semiconductor wafer on which an electronic circuit is mounted; a protective film on the semiconductor wafer including a peripheral portion of the electrode unit; A current film on a portion of the electrode portion including the protective film; a solder underlayer having an edge on the current film at a portion where the electrode portion and the protective film overlap; a current film and the solder underlayer And a solder bump covering the exposed portion of the metal layer and not forming a compound even when combined with solder, and a solder bump covering the metal layer.
行う電極部を有し、前記電極部の周辺部を含んだ上に保
護膜を有する半導体ウエハを形成するステップと、 前記電極部形成面全面に電解メッキ用のカレントフィル
ムを形成するステップと、 フォトレジストを塗布し、フォトリソ工程により前記電
極部と保護膜が重なる箇所に 端を備えた開口部を前記
カレントフィルム上に形成するステップと、 前記開口部の前記カレントフィルム上にハンダ下地層を
メッキするステップと、 前記開口部の前記ハンダ下地層上にハンダと合わせても
化合物には成らない金属層をメッキするステップと、 フォトリソ工程により前記フォトレジストの前記開口部
の周囲を金属層の厚さ程度広げるステップと、 前記カレントフィルムと前記ハンダ下地層の露出部を覆
い、前記金属層をメッキするステップと、 前記金属層の上にハンダを形成するステップと、 前記フォトレジストを除去し、金属層で覆われていない
カレントフィルムをエッチングするステップと、 前記ハンダを球形のバンプにするステップと、 を有することを特徴とするハンダバンプ電極形成方法。2. A method for forming a solder bump structure, comprising: a semiconductor wafer having an electrode portion for mounting an electronic circuit and performing input / output from the electronic circuit, and having a protective film on a peripheral portion of the electrode portion. Forming a current film for electrolytic plating on the entire surface of the electrode portion forming surface; applying a photoresist; and an opening having an edge at a position where the electrode portion and the protective film overlap by a photolithography process. Forming on the current film, plating a solder underlayer on the current film in the opening, and forming a metal which does not become a compound even when combined with solder on the solder underlayer in the opening. Plating a layer, and enlarging the periphery of the opening of the photoresist by a photolithography process by a thickness of a metal layer. Covering the exposed portions of the current film and the solder underlayer and plating the metal layer; forming solder on the metal layer; removing the photoresist and covering with a metal layer Etching a current film which has not been removed, and forming the solder into a spherical bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33898797A JPH11176860A (en) | 1997-12-09 | 1997-12-09 | Solder bump structure and its forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33898797A JPH11176860A (en) | 1997-12-09 | 1997-12-09 | Solder bump structure and its forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11176860A true JPH11176860A (en) | 1999-07-02 |
Family
ID=18323209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33898797A Withdrawn JPH11176860A (en) | 1997-12-09 | 1997-12-09 | Solder bump structure and its forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11176860A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100519893B1 (en) * | 2001-11-15 | 2005-10-13 | 인피니온 테크놀로지스 아게 | Fabrication method for an interconnect on a substrate |
| CN117374041A (en) * | 2023-12-08 | 2024-01-09 | 英诺赛科(苏州)半导体有限公司 | Packaging substrate, manufacturing method, packaging assembly, microelectronic assembly and electronic device |
-
1997
- 1997-12-09 JP JP33898797A patent/JPH11176860A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100519893B1 (en) * | 2001-11-15 | 2005-10-13 | 인피니온 테크놀로지스 아게 | Fabrication method for an interconnect on a substrate |
| CN117374041A (en) * | 2023-12-08 | 2024-01-09 | 英诺赛科(苏州)半导体有限公司 | Packaging substrate, manufacturing method, packaging assembly, microelectronic assembly and electronic device |
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
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