JPH1117079A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1117079A JPH1117079A JP9170796A JP17079697A JPH1117079A JP H1117079 A JPH1117079 A JP H1117079A JP 9170796 A JP9170796 A JP 9170796A JP 17079697 A JP17079697 A JP 17079697A JP H1117079 A JPH1117079 A JP H1117079A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- composite substrate
- substrate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 温度上昇による反りが減少し、電気容量を上
げることができる半導体装置を提供する。
【解決手段】 半導体素子１３の両面に半田層１３、１
４を介して、少なくとも片面に金属被覆を施したセラミ
ック基板１１、１５の金属被覆部を接着させる。
(57) [Summary] [PROBLEMS] To provide a semiconductor device in which warpage due to temperature rise is reduced and electric capacity can be increased. SOLUTION: Solder layers 13, 1 are provided on both surfaces of a semiconductor element 13.
The metal-coated portions of the ceramic substrates 11 and 15 having at least one surface coated with metal are adhered to each other through the metal layer 4.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、放熱を要する半導
体装置の構造に関する。The present invention relates to a structure of a semiconductor device requiring heat radiation.
【０００２】[0002]
【従来の技術】パワー系の半導体素子（例えば、ＩＧＢ
Ｔ(Insulated Gate Bipolar Transistor) ）等の発熱部
品を如何に冷却するかは、発熱部品が搭載された機器を
使用する上で解決すべき重要課題となっている。この課
題を解決するためには、先ず、放熱冷却特性を向上させ
ることに努めるが、温度が変化する場合には熱応力によ
る変形が問題となる。例えば図２（ａ）に示すように、
発熱する半導体素子１（例えばＳｉチップなどのチップ
状のもの）は、放熱させる目的で、その片面が半田層２
を介して基板３（金属被覆されたセラミック基板）に取
り付けられた半導体装置４として使用される。また、こ
の半導体装置４はヒートシンク（図示されず）などの冷
却部材上に搭載されて使用される。この例では、半導体
素子１と基板３の熱膨張係数の差から発生する熱応力が
問題となる。即ち、実使用においては半導体素子１は熱
応力により変形して、反り、また電力のオン・オフによ
るヒートサイクルによって半導体素子１と基板３間の半
田層２がクラックなどにより劣化する。通常は、半導体
素子１の熱膨張係数が基板３やヒートシンクよりも小さ
く、温度が上昇すると、図２（ｂ）に示すような反りが
生ずる。このため、この熱応力を小さくするように半導
体素子１と基板３の熱膨張係数の差を小さくすることが
必要となり、基板材料は限定されたものとなる。また、
実際に使える半導体素子１の電気的容量は制約を受け、
半導体素子１本来の電気的容量よりも小さくなる。2. Description of the Related Art Power semiconductor devices (for example, IGB)
How to cool a heat-generating component such as T (Insulated Gate Bipolar Transistor) is an important issue to be solved when using a device equipped with a heat-generating component. In order to solve this problem, first, efforts are made to improve the radiation cooling characteristics, but when the temperature changes, deformation due to thermal stress becomes a problem. For example, as shown in FIG.
One side of the semiconductor element 1 (for example, a chip-shaped element such as a Si chip) that generates heat has a solder layer 2 for heat dissipation.
As a semiconductor device 4 mounted on a substrate 3 (a metal-coated ceramic substrate) via a substrate. The semiconductor device 4 is used by being mounted on a cooling member such as a heat sink (not shown). In this example, a problem is a thermal stress generated from a difference between the thermal expansion coefficients of the semiconductor element 1 and the substrate 3. That is, in actual use, the semiconductor element 1 is deformed due to thermal stress and warps, and the solder layer 2 between the semiconductor element 1 and the substrate 3 is deteriorated by cracks and the like due to a heat cycle caused by turning on and off the power. Normally, the coefficient of thermal expansion of the semiconductor element 1 is smaller than that of the substrate 3 or the heat sink, and when the temperature rises, warpage as shown in FIG. 2B occurs. For this reason, it is necessary to reduce the difference between the thermal expansion coefficients of the semiconductor element 1 and the substrate 3 so as to reduce the thermal stress, and the substrate material is limited. Also,
The electric capacity of the semiconductor element 1 that can be actually used is limited,
It becomes smaller than the original electric capacity of the semiconductor element 1.
【０００３】[0003]
【発明が解決しようとする課題】上述のように、従来の
半導体装置には、熱応力により変形して、反りが生じる
ため、基板材料が限定され、また、実際に使える電気的
容量が制約を受けて上がらないという問題があった。As described above, since the conventional semiconductor device is deformed by thermal stress and warps, the substrate material is limited, and the practically usable electric capacity is limited. There was a problem of not receiving it.
【０００４】[0004]
【課題を解決するための手段】本発明は上記問題点を解
決すべくなされたもので、請求項１記載の発明は、半導
体素子の両面に基板を配置したことを特徴とする半導体
装置である。ここで、半導体素子はＳｉ、ＧａＡｓなど
のチップ状のものを指す。本発明によれば、温度が上昇
したときに、半導体素子の両面に反り方向が逆の方向に
なるように２つの熱応力が働き、これらの熱応力が釣り
合うため、反りが従来に比し減少する。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the invention according to claim 1 is a semiconductor device characterized in that substrates are arranged on both surfaces of a semiconductor element. . Here, the semiconductor element indicates a chip-shaped element such as Si or GaAs. According to the present invention, when the temperature rises, two thermal stresses act on both surfaces of the semiconductor element so that the warping directions are opposite to each other, and these thermal stresses are balanced, so that the warpage is reduced as compared with the conventional case. I do.
【０００５】また、請求項２記載の発明は、請求項１記
載の発明をより具体的に記したもので、半導体素子の両
面に半田層を介して、セラミック板の少なくとも片面に
金属被覆を施した複合基板の金属被覆部を接合させたこ
とを特徴とする半導体装置である。The second aspect of the invention is a more specific version of the first aspect of the invention, in which at least one surface of a ceramic plate is provided with a metal coating via solder layers on both surfaces of a semiconductor element. A semiconductor device characterized in that a metal covering portion of the composite substrate is joined.
【０００６】さらに、請求項３記載の発明は、冷却部材
上に搭載して使用する請求項２記載の半導体装置であっ
て、冷却部材に接合する複合基板の厚さに対して、冷却
部材と反対側に位置する複合基板の厚さが１．５倍以上
であることを特徴とするものである。上述のように、冷
却部材と反対側に位置する複合基板の厚さを冷却部材に
接合する複合基板の厚さに対して１．５倍以上にする
と、熱応力による反りを一層減少させることができる。
なお、冷却部材と反対側に位置する複合基板は熱応力を
釣り合わせるためのものであって、電気的などの他の機
能は特に要求されることはない。Further, the invention according to claim 3 is the semiconductor device according to claim 2, which is mounted on a cooling member and used, wherein the thickness of the composite substrate bonded to the cooling member is less than the thickness of the composite member. The thickness of the composite substrate located on the opposite side is 1.5 times or more. As described above, when the thickness of the composite substrate located on the side opposite to the cooling member is set to be 1.5 times or more the thickness of the composite substrate bonded to the cooling member, the warpage due to thermal stress can be further reduced. it can.
The composite substrate located on the side opposite to the cooling member is for balancing thermal stress, and other functions such as electrical are not particularly required.
【０００７】[0007]
【発明の実施の形態】以下、図面に基づいて本発明の実
施の形態を詳細に説明する。図１は、本発明にかかる半
導体装置の一実施形態の側面図である。図中、１１、１
５はアルミナ板の両側に０．２５ｍｍ厚の銅箔を接着し
た複合基板である。１２、１４は０．１ｍｍ厚の半田
層、１３は０．３５ｍｍ厚、１２ｍｍ×１２ｍｍのＧａ
Ａｓチップからなる半導体素子である。なお、複合基板
１１、１５の熱膨張係数は８×１０-6ｄｅｇ-1であり、
半導体素子１３の熱膨張係数は４×１０ -6ｄｅｇ-1であ
る。本実施形態では、半導体素子１３は両面で半田層１
２、１４を介して複合基板１１、１５に接合している。
複合基板１１はサイズが６０ｍｍ×１００ｍｍであり、
ヒートシンクなどの冷却部材（図示されず）に接合す
る。また、複合基板１５は１２ｍｍ×１２ｍｍのサイズ
で、０．３〜０．５ｍｍφ程度の穴１６が設けられてい
る。これらの穴１６を通して配線材１７が半導体素子１
３に接続している。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The embodiment will be described in detail. FIG.
It is a side view of one embodiment of a conductor device. In the figure, 11, 1
5 is gluing copper foil of 0.25mm thickness on both sides of alumina plate
Composite substrate. 12 and 14 are 0.1mm thick solder
Layer 13 is 0.35 mm thick, 12 mm × 12 mm Ga
This is a semiconductor element composed of an As chip. In addition, composite board
Thermal expansion coefficients of 11 and 15 are 8 × 10-6deg-1And
The thermal expansion coefficient of the semiconductor element 13 is 4 × 10 -6deg-1In
You. In this embodiment, the semiconductor element 13 has the solder layers 1 on both sides.
They are joined to the composite substrates 11 and 15 via the substrates 2 and 14.
The composite substrate 11 has a size of 60 mm × 100 mm,
Connect to a cooling member (not shown) such as a heat sink
You. The composite substrate 15 has a size of 12 mm × 12 mm.
And a hole 16 of about 0.3 to 0.5 mmφ is provided.
You. Through these holes 16, the wiring member 17 is connected to the semiconductor element 1.
3 is connected.
【０００８】本実施形態において、複合基板１１側をヒ
ートシンク上にグリースで接合し、複合基板１１の厚さ
を０．７５ｍｍとし、複合基板１５の厚さを変えて、反
りの大きさをレーザー距離計を用いて非接触で測定し
た。その結果を表１に示す。なお、半導体素子１３には
１００Ｗの発熱量となるように通電した。In the present embodiment, the composite substrate 11 is bonded to a heat sink with grease, the thickness of the composite substrate 11 is set to 0.75 mm, the thickness of the composite substrate 15 is changed, and the magnitude of the warpage is changed by the laser distance. The measurement was performed without contact using a meter. Table 1 shows the results. The semiconductor element 13 was energized so as to generate 100 W of heat.
【０００９】 注）試料NO. ６：本実施形態の複合基板１５を除いたものであり、図２の従 来例に相当する。[0009] Note) Sample No. 6: Except for the composite substrate 15 of the present embodiment, which corresponds to the conventional example of FIG.
【００１０】表１によれば、半導体素子１３のヒートシ
ンクと反対側に複合基板１５を設けると、複合基板１５
を設けない場合（試料NO. ６）よりも反りが小さくな
る。特に、複合基板１５の厚さを１．１３ｍｍ（複合基
板１１の１．５倍）以上にすると、反りが１μｍ以下に
抑えられる。According to Table 1, when the composite substrate 15 is provided on the side of the semiconductor element 13 opposite to the heat sink, the composite substrate 15
The warpage is smaller than when no sample is provided (Sample No. 6). In particular, when the thickness of the composite substrate 15 is 1.13 mm (1.5 times the composite substrate 11) or more, the warpage can be suppressed to 1 μm or less.
【００１１】なお、本発明は上記実施形態に限定される
ことはなく、例えば、複合基板１１、１５はアルミナの
代わりにＡｌＮを用いてもよい。また、複合基板１５
は、Ｍｏ、インバー合金、Ｃｕ−Ｗなどの熱膨張係数が
おおむね１０×１０-6／℃以下のものを用いることもで
きる。ＡｌＮはアルミナよりも熱伝導率がよいため、半
導体素子１３の上昇温度を同程度にしても、半導体素子
１３の発熱量を大きくすることができるので、電気容量
を上げることができる。The present invention is not limited to the above embodiment. For example, the composite substrates 11 and 15 may use AlN instead of alumina. Also, the composite substrate 15
For example, Mo, Invar alloy, Cu-W, or the like having a thermal expansion coefficient of about 10 × 10 −6 / ° C. or less can be used. Since AlN has a higher thermal conductivity than alumina, even if the temperature of the semiconductor element 13 is kept almost the same, the calorific value of the semiconductor element 13 can be increased, so that the electric capacity can be increased.
【００１２】[0012]
【発明の効果】本発明によれば、温度上昇による反りが
減少し、電気容量を上げることができるという優れた効
果がある。According to the present invention, there is an excellent effect that the warpage due to the temperature rise is reduced and the electric capacity can be increased.
【図１】本発明に係る半導体装置の一実施形態の側面図
である。FIG. 1 is a side view of one embodiment of a semiconductor device according to the present invention.
【図２】（ａ）、（ｂ）はそれぞれ、常温および温度上
昇時の半導体装置の側面図である。FIGS. 2A and 2B are side views of the semiconductor device at normal temperature and when the temperature is increased, respectively.
１１、１５ 複合基板 １２、１４ 半田層 １３ 半導体素子 １６ 穴 １７ 配線材 11, 15 Composite substrate 12, 14 Solder layer 13 Semiconductor element 16 Hole 17 Wiring material
Claims (3)
を特徴とする半導体装置。1. A semiconductor device comprising substrates arranged on both sides of a semiconductor element.
ラミック板の少なくとも片面に金属被覆を施した複合基
板の金属被覆部を接合させたことを特徴とする半導体装
置。2. A semiconductor device wherein a metal coating portion of a composite substrate in which at least one surface of a ceramic plate is coated with a metal is joined via solder layers on both surfaces of the semiconductor element.
置であって、冷却部材に接合する複合基板の厚さに対し
て、冷却部材と反対側に位置する複合基板の厚さが１．
５倍以上であることを特徴とする請求項２記載の半導体
装置。3. A semiconductor device mounted and used on a cooling member, wherein the thickness of the composite substrate located on the side opposite to the cooling member with respect to the thickness of the composite substrate bonded to the cooling member is 1.
3. The semiconductor device according to claim 2, wherein the number is five times or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9170796A JPH1117079A (en) | 1997-06-27 | 1997-06-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9170796A JPH1117079A (en) | 1997-06-27 | 1997-06-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117079A true JPH1117079A (en) | 1999-01-22 |
Family
ID=15911521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9170796A Pending JPH1117079A (en) | 1997-06-27 | 1997-06-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117079A (en) |
-
1997
- 1997-06-27 JP JP9170796A patent/JPH1117079A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH07106477A (en) | Heat sink assembly with heat conduction board | |
| JPH06252285A (en) | Circuit board | |
| JPH04162756A (en) | Semiconductor module | |
| JP2930133B2 (en) | Printed wiring board composite structure | |
| JP2004022973A (en) | Ceramic circuit board and semiconductor module | |
| JP2002289630A (en) | Power semiconductor module | |
| JP2006269966A (en) | Wiring substrate and its manufacturing method | |
| JP4992302B2 (en) | Power semiconductor module | |
| US7236367B2 (en) | Power electronics component | |
| JPH1117079A (en) | Semiconductor device | |
| JP2004343035A (en) | Heat radiating component, circuit board, and semiconductor device | |
| JP4876612B2 (en) | Insulated heat transfer structure and power module substrate | |
| CN112490202A (en) | Power device package structure | |
| JP2001135753A (en) | Semiconductor module substrate and manufacturing method for the same | |
| JP2521624Y2 (en) | Semiconductor device | |
| JP3007086U (en) | Insulating substrate | |
| JPS59227132A (en) | Semiconductor device | |
| JPH06169037A (en) | Semiconductor package | |
| JP2006041231A (en) | Ceramic circuit board and electrical device | |
| JP2619155B2 (en) | Hybrid integrated circuit device | |
| JPS60250655A (en) | Integrated circuit package | |
| JPH05114665A (en) | Heat radiative substrate | |
| JPS62193157A (en) | power device package | |
| JP2005217134A (en) | Composite wiring board and composite wiring board device | |
| JP2626785B2 (en) | Substrate for mounting electronic components |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050301 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050726 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050926 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060110 |