JPH11186439A - Substrate for semiconductor package and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve position precision of an outer terminal against the outer form of a package, by forming an aligning pattern becoming a reference in a dicing process and an outer connection electrode deciding the outer diameter and the position of the outer terminal with same members and the same processes. SOLUTION: A cut aligning mark 11 formed of solder resist exists outside a product. An outer connection electrode 4a whose outer form and the position are decided by solder resist exists on a copper pattern of a product-side. When the outer diameter of the copper pattern is larger than the opening diameter of the opening part of solder resist, the cut aligning mark 11 is formed of solder resist deciding the outer diameter and the position of the outer connection electrode 4a. Thus, the position precision of the electrode against the outer form of the product improves. Consequently, the semiconductor package superior in the loading ability of the semiconductor package to a mother board and productivity is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor package, and more particularly to a method of manufacturing a semiconductor package having a projection electrode for external connection.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing.

FIG. 6 shows a prior art in which a large number of pieces are taken and high-density mounting is carried out in JP-A-8-153819. The outline will be described below with reference to the drawings.

In FIG. 6, after a through hole 2 is formed in a strip-shaped circuit board 1, a copper plating layer is applied, and a plurality of, for example, two BGAs including a common electrode 14 connected to all circuit patterns are formed. A circuit pattern forming step of forming a circuit pattern to be formed, and after applying a photosensitive resin film on the upper and lower surfaces of the circuit board 1, the common electrode 14 and the respective connection portions of the IC chip, bonding wires, and solder bumps are etched. A dry film laminating step of forming a dry film so as to remove, and forming a Ni—Au plated layer on the surfaces of the copper plated layers of the exposed electrodes on the upper and lower surfaces of the circuit board 1 using the common electrode 14. I do.

Next, a pattern separating step for separating the common electrode 14 from the circuit pattern is performed along four sides of the product separation line 15 at the four corners of the connecting portion 15 for connecting to the circuit board 1.
A long hole 16 is made by router processing so as to leave a. Thereafter, resin sealing is performed by wire bonding and transfer molding, and solder bumps are formed on the lower surface of the circuit board 1.

[0006] In the product separation step, since the connection portions left at the four corners are narrow, separation can be performed very easily by a separation means such as a press without applying an extra load.
A single BGA can be manufactured.

However, the above-described method of manufacturing a semiconductor package in which a plurality of strip-shaped semiconductor packages are obtained has a slight improvement in productivity as compared with the method of manufacturing a single semiconductor package. The number of substrates to be manufactured at the time of substrate manufacture is small, and the production cost is increased. Further, when the distance from the outer edge of the circuit board to the center of the ball electrode located at the outermost periphery is eliminated as in the case of the CSP, when the mold is separated by a separation means such as a press punch in a product separation process, the die is pressed. There was a problem that the bill was lost.

Therefore, a CSP mounted on a small portable device or the like
An outline of the conventional semiconductor package manufacturing method will be described below.

FIG. 3 shows a semiconductor package substrate manufacturing process. After a through hole 21 is formed in the collective circuit board 1A covered with copper on both sides, a copper plating layer 22 is formed by electroless copper plating and electrolytic copper plating, and the through hole is filled with a filling material 23 such as a resin. Are laminated and exposed and developed to form a pattern mask, and then pattern etching is performed using an etching solution, whereby a plurality of IC connection electrodes 3 arranged on the upper surface side of the collective circuit board 1A, the lower surface side Next, an external connection electrode 4 which is a pad electrode is formed. Next, a solder resist process is performed to form a resist film on a predetermined portion, so that the external connection electrode 4 is formed on the lower surface side of the collective circuit board 1A so as to be exposed, and the exposed IC connection electrode 3 is further formed. Then, gold plating is performed on the external connection electrodes 4 to complete the collective circuit board 1A in which a large number of pieces are taken.

FIG. 4 (a) is a circuit board forming step for forming a large number of circuit boards as described in detail in FIG. Are formed with a large number of solderable external connection electrodes 4 of the same shape. 2 is a cut line orthogonal to the X and Y directions.

The IC chip mounting step shown in FIG.
First, a solder bump 5 is formed on a pad electrode surface of the IC wafer by flowing the IC wafer to a bump process. The method of forming the solder bumps 5 is generally a stud bump method, a ball bump method, a plating bump method, etc. Among them, a window is formed with a resist at a pad electrode position and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps in a narrow arrangement between pad electrodes, and is an effective means of forming solder bumps for miniaturizing IC chips.

After the solder bumps 5 are formed, the thickness of the wafer is cut in the X and Y directions by a full-cut method with a device such as a dicing saw to a predetermined chip size while the IC wafer is adhered with an adhesive tape or the like. After that, the IC chip 6 is divided into single pieces.

A flux is applied to the IC chip 6 with solder bumps or a predetermined position of the wiring pattern of the above-mentioned collective circuit board 1A, and a plurality of the IC chips 6 divided into single pieces are arranged one by one. After being mounted at a predetermined position on each circuit board 1 of the circuit board 1A, flip-chip mounting is performed through a solder reflow process.

In the sealing step shown in FIG. 4C, the resin is integrally sealed by side potting with the thermosetting sealing resin 7 straddling the plurality of adjacent IC chips 5. By doing so, the IC chip 6 is fixed face down on the individual circuit boards 1 of the collective circuit board 1A.

Further, a ball electrode 9 is formed by arranging and reflowing solder balls at the positions of the external connection electrodes 4 formed on the lower surface side of the integrated circuit board 1A on which the IC chip 6 is mounted.

In the reference member attaching step shown in FIG. 5A, the external connection electrode 4 formed on the lower surface side of the integrated circuit board 1A on which the IC chip 6 is mounted is attached to the reference member 8 with an adhesive or an adhesive tape. Attach with fixing means such as.

FIG. 5 (b) shows a tying step, in which cutting means such as a dicing saw is used along the above-mentioned cut line 2 in the X and Y directions, and the collective circuit board 1 as shown in FIG.
A is individually cut and divided based on the cutting registration mark 11 formed on the lower surface side of A, and the reference member 8 is heated or the like.
More peel off.

FIG. 7A is a plan view of the lower surface side of the collective circuit board 1A. The external connection electrode 4 is formed inside the product, and the cutting alignment mark 11 is formed outside the product.

FIG. 7B is a sectional view taken along the line EE 'of the cutting registration mark 11 of FIG. 7A, and is formed by a copper pattern.

FIG. 7C is a cross-sectional view of the external connection electrode 4 taken along line FF ′ of FIG. 7A, which is formed by a solder resist formed on a copper pattern. That is, the surface of the external connection electrode 4a is formed by the copper pattern, and the outer diameter and position of the electrode are determined by the opening of the solder resist.

[0021]

However, the above-described method for manufacturing a semiconductor package has the following problems. That is, since the cutting registration pattern and the external connection electrode which are the reference in the dicing process are not the same, when cut and divided into single pieces, problems such as poor positional accuracy of the external terminals based on the external shape of the product occur. there were. In other words, the outer diameter and position of the cutting registration pattern are determined by the copper pattern, whereas the outer diameter and position of the external connection electrode are not determined by the copper pattern but by the opening of the solder resist. It was difficult to make a perfect match.

The positional accuracy of the external terminals with reference to the external shape of the product is determined by the positional tolerance of the solder forming the external connection electrode with respect to the copper pattern forming the cutting alignment pattern ± 1.
It becomes ± 150 microns, which is the sum of 00 microns and dicing tolerance ± 50 microns.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a semiconductor substrate and a semiconductor package in which external terminals have high positional accuracy with respect to an external standard mounted on a small portable device or the like. It is.

[0024]

In order to achieve the above object, the present invention provides a bonding circuit for mounting an IC chip and an electrode pattern for forming electrodes for external connection on a surface of a collective circuit board. In a semiconductor package substrate, a plurality of IC chips are electrically connected to an arrayed circuit board, and a package assembly in which the IC chips are sealed with a resin is cut to form a single completed semiconductor package. The circuit board of the package assembly has a positioning pattern indicating a cutting position, and the positioning pattern is formed of the same member as a constituent member of the external connection electrode.

Also, a plurality of bonding patterns for mounting an IC chip provided on one surface and an electrode pattern for forming external connection electrodes provided on the other surface are arranged on the surface of the collective circuit board. Forming a circuit board, forming an integrated circuit by electrically connecting an IC chip to the bonding pattern, sealing the IC chip with a resin to form a package assembly, A holding step of fixing the IC chip mounting surface side of the assembly to the reference member, an alignment pattern forming step of forming an alignment pattern that is a cutting position on the held circuit board of the package assembly, and And a cutting step of cutting the circuit board on the basis of to form a single completed semiconductor package. Serial alignment pattern is characterized in that the configuration same members as those of the external connection electrodes formed at the circuit board forming process, and is and formed in the same step.

Further, the constituent member of the external connection electrode is the same metal wiring member as the electrode pattern.

Further, the constituent member of the external connection electrode is a solder resist which partially covers the electrode pattern and regulates the position of the external connection electrode.

Further, the cutting step is performed by cutting with a dicing saw.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package substrate and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. 1 and 2 are explanatory views of a semiconductor package substrate according to an embodiment of the present invention. FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor package substrate. 4 and 5 are explanatory views showing the steps of manufacturing a semiconductor package with a bump electrode. The same members as those in the prior art are denoted by the same reference numerals.

First, FIG. 3 is an explanatory view of a process for forming a substrate for a semiconductor package. However, the description is omitted because it is the same as the above-mentioned prior art.

FIG. 1A is a plan view showing a semiconductor package substrate according to the present invention. There is a cutting alignment mark 11 formed of a solder resist outside the product. On the copper pattern on the product side, there is an external connection electrode 4b whose outer diameter and position are determined by the solder resist. That is, the present embodiment shows a case where the outer diameter of the copper pattern is larger than the opening diameter of the solder resist opening, and the cutting registration mark 11 is formed by the solder resist that determines the outer diameter and the position of the external connection electrode 4b. Because it is formed,
This improves the positional accuracy of the electrodes with respect to the outer shape of the product.

FIG. 1B is a sectional view taken along the line AA ′ of FIG.

FIG. 1C is a sectional view taken along the line BB 'of FIG. 1A.

FIG. 2A shows another example of the semiconductor package substrate of the present invention. Outside the product, there is a cutting alignment mark 11 formed of a copper pattern. An external connection electrode 4b formed of a copper pattern is provided in a portion where the solder resist on the product side is opened. In the present embodiment,
The case where the outer diameter of the copper pattern is smaller than the opening diameter of the solder resist opening is shown.
However, since it is composed of a copper pattern that determines the outer diameter and position of the external connection electrode 4b, the positional accuracy of the electrode with respect to the outer shape of the product is improved.

FIG. 2B is a sectional view taken along the line CC 'of FIG. 2A.

FIG. 2C is a sectional view taken along the line DD ′ of FIG. 2A.

FIG. 4A shows a circuit board forming step, and FIG.
The IC mounting process of FIG. 4B and the resin sealing process of FIG.
The description is omitted because it is similar to the above-described conventional technology.

In the reference member attaching step shown in FIG. 5A, the ball electrode 9a and the solder ball protrusion 9b are bonded to the reference member 8 with an adhesive, for example, a heat-peeling tape manufactured by Nitto Denko Corporation, "Elep Holder Sensing". Compression dicing tape, SPV
-224 "or the like, and is fixed on the reference member 8.

FIG. 2 (d) shows a dicing process along a dicing saw, for example, a dicing machine "DFD-64" along the cut line 2 in the X and Y directions.
0 ", the blade used" NBC-ZB1090S3, 0.
After cutting and dividing into single pieces with reference to the cutting registration mark 11 formed of a solder resist on the outside of the product by a cutting means using "1 mm width" or the like, the adhesive force of the peeling tape is reduced by heat. Then, it is peeled off from the reference member 8. Through the above steps, a single flip chip BGA10
Is completed.

[0040]

As described above, in the semiconductor package using the semiconductor package substrate of the present invention, the configuration of the external connection electrode for determining the outer diameter and the position of the alignment pattern and the external terminal pattern to be a reference in the dicing process. Since the members and the members are formed in the same member and in the same process, it is possible to provide a semiconductor package in which the positional accuracy of the external terminals with respect to the package outer shape is good, and the semiconductor package has excellent mountability and productivity on a motherboard.

The positional accuracy of the external terminals based on the external shape of the product is as follows. Since the process of forming the cutting registration pattern and the external connection electrode is the same, the positional tolerance of the copper pattern or the solder resist is ± 10 μm and the dicing tolerance is ± 10 μm. The sum of 50 microns is ± 60 microns.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is another explanatory view of the semiconductor substrate according to the embodiment of the present invention.

FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor substrate.

FIG. 4 is an explanatory view showing a circuit board forming step, an IC mounting step, and a resin sealing step in a manufacturing process of the BGA semiconductor package.

FIG. 5 is an explanatory view showing a circuit board forming step, an IC mounting step, and a resin sealing step in a manufacturing process of the BGA semiconductor package.

FIG. 6 is a plan view of a conventional strip-shaped BGA.

FIG. 7 is an explanatory view of a conventional semiconductor substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit board 1A Assembly circuit board 2 Cut line 3 IC connection electrode 4a External connection electrode 4b Projection forming pad 5 Solder ball 6 IC chip 7 Sealing resin 8 Reference member 9 Ball electrode (projection electrode) 10 Flip chip BGA 11 Cutting Eye matching pattern

Claims (5)

[Claims] A plurality of IC chips are electrically connected to a circuit board formed by arranging a plurality of bonding patterns for mounting IC chips and electrode patterns for forming external connection electrodes on a surface of a collective circuit board. A package assembly in which the IC chip is resin-sealed to form a single completed semiconductor package by cutting the package assembly, wherein the circuit board of the package assembly has an alignment pattern indicating a cutting position. Wherein the alignment pattern is formed of the same member as a constituent member of the external connection electrode. 2. A plurality of bonding patterns for mounting an IC chip provided on one surface and electrode patterns for forming external connection electrodes provided on the other surface are arranged on the collective circuit board surface. Forming a circuit board, forming an integrated circuit by electrically connecting an IC chip to the bonding pattern, sealing the IC chip with a resin to form a package assembly, A holding step of fixing the IC chip mounting surface side of the assembly to the reference member, an alignment pattern forming step of forming an alignment pattern that is a cutting position on the held circuit board of the package assembly, and A step of cutting the circuit board to form a single completed semiconductor package based on the semiconductor substrate. A method of manufacturing a substrate for a semiconductor package, wherein the alignment pattern is formed of the same member as the constituent member of the external connection electrode formed in the circuit board forming step, and is formed in the same step. 3. The method for manufacturing a semiconductor package substrate according to claim 2, wherein the constituent members of the external connection electrodes are the same metal wiring members as the electrode patterns. 4. The semiconductor package substrate according to claim 1, wherein the constituent member of the external connection electrode is a solder resist that partially covers the electrode pattern and regulates the position of the external connection electrode. 5. The method according to claim 2, wherein the cutting step is performed by cutting with a dicing saw.