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JPH11186471A - Multi-chip parallel mounting type semiconductor device - Google Patents

Multi-chip parallel mounting type semiconductor device

Info

Publication number
JPH11186471A
JPH11186471A JP34755497A JP34755497A JPH11186471A JP H11186471 A JPH11186471 A JP H11186471A JP 34755497 A JP34755497 A JP 34755497A JP 34755497 A JP34755497 A JP 34755497A JP H11186471 A JPH11186471 A JP H11186471A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
semiconductor
roll
heat radiating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34755497A
Other languages
Japanese (ja)
Inventor
Hironori Kodama
弘則 児玉
Mitsuo Kato
光雄 加藤
Mamoru Sawahata
守 沢畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP34755497A priority Critical patent/JPH11186471A/en
Publication of JPH11186471A publication Critical patent/JPH11186471A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】 【課題】本発明は、多チップ並列実装型半導体装置にお
いて、特に高さの異なる半導体チップと半導体チップか
ら発生する熱を放散する放熱部材との間の均一な接触状
態を確保し、かつ熱抵抗を低減できる構造を提供するこ
とにある。 【解決手段】多チップ並列実装型半導体装置において、
該半導体チップと該放熱部材との間に薄板をロール状に
加工した金属またはその集合体を配置する。
(57) Abstract: The present invention relates to a multi-chip parallel mounting type semiconductor device, and more particularly to a uniform contact state between semiconductor chips having different heights and a heat radiating member for dissipating heat generated from the semiconductor chips. An object of the present invention is to provide a structure that can secure the heat resistance and reduce the heat resistance. In a multi-chip parallel mounting type semiconductor device,
A metal obtained by processing a thin plate into a roll or an aggregate thereof is disposed between the semiconductor chip and the heat radiating member.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多チップ並列実装
型半導体装置に係り、特に半導体チップから発生する熱
を放散する放熱部材との均一な接触状態を確保し、かつ
熱抵抗を低減できる多チップ並列実装型半導体装置、及
びこれを用いた変換器、または演算制御装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip parallel mounting type semiconductor device, and more particularly to a multi-chip parallel mounting type semiconductor device capable of ensuring uniform contact with a heat radiating member for dissipating heat generated from a semiconductor chip and reducing thermal resistance. The present invention relates to a chip-parallel-mounted semiconductor device and a converter or an operation control device using the same.

【0002】[0002]

【従来の技術】近年、計算機や各種演算制御システムで
は処理の高速化の要求に対応するため、半導体チップの
高集積化,高速化とともに、実装側では一つの配線基板
上に複数個の半導体チップを搭載して配線長を短縮し、
高速化を実現する多チップ並列実装が行われるようにな
ってきている。上記により半導体チップの発熱量が増加
し、さらに半導体チップの実装密度が高くなっているこ
とから実装面での発熱密度も増加してきており、この熱
を放散することが非常に重要な課題となっている。さら
に多チップ並列実装の場合には、チップ間でチップを実
装した高さがばらつくため、これを吸収して冷却部材と
の均一な接触状態を確保するために、熱伝導性の良好な
フィラー入りゴムや有機ペースト等の柔軟な材料を用い
たり、個別の半導体チップ毎に独立したピストン型やく
し歯型の冷却部材等を用いている。一方、半導体エレク
トロニクスの技術を駆使して主回路電流を制御するパワ
ーエレクトロニクスの分野でも近年、MOS構造ゲート
への入力信号により主電流を制御するMOS制御デバイ
スである絶縁ゲート型バイポーラトランジスタ(以下I
GBTと略す)やMOS型電界効果トランジスタ(以下M
OSFETと略す)などが注目され、例えばIGBTは、パワ
ースイッチングデバイスとしてモータPWM制御インバ
ータの応用などに幅広く使われている。
2. Description of the Related Art In recent years, in order to respond to the demand for high-speed processing in computers and various arithmetic and control systems, the integration and speed of semiconductor chips have been increased, and a plurality of semiconductor chips have been mounted on a single wiring board on the mounting side. To shorten the wiring length,
Multi-chip parallel mounting for realizing high speed has been performed. Due to the above, the amount of heat generated by the semiconductor chip has increased, and since the mounting density of the semiconductor chip has increased, the heat generation density on the mounting surface has also increased. Dissipating this heat has become a very important issue. ing. Furthermore, in the case of multi-chip parallel mounting, since the height at which chips are mounted varies between chips, a filler with good thermal conductivity is used to absorb this and ensure uniform contact with the cooling member. A flexible material such as rubber or organic paste is used, or an independent piston-type or comb-type cooling member is used for each individual semiconductor chip. On the other hand, in the field of power electronics, in which the main circuit current is controlled by making full use of semiconductor electronics technology, recently, an insulated gate bipolar transistor (hereinafter referred to as I) which is a MOS control device for controlling a main current by an input signal to a MOS structure gate.
GBT) and MOS field-effect transistors (M
For example, IGBTs are widely used as power switching devices in applications such as motor PWM control inverters.

【0003】従来、IGBTでは主にモジュール型構造
と呼ばれる、ワイヤによる電極接続方式のパッケージ形
態により複数個のチップを実装していたが、最近、さら
に大容量化の要求に応えるため、多数のIGBTチップ
を圧接型のパッケージ内に組み込み、その主面に形成さ
れたエミッタ電極,コレクタ電極をそれぞれパッケージ
側に設けた一対の外部共通電極基板に面接触させて引き
出すようにした多チップ並列型加圧接触構造の半導体装
置が注目されている。
Conventionally, a plurality of chips are mounted in an IGBT in a package form of an electrode connection method using wires, which is mainly called a module type structure. A multi-chip parallel-type press, in which the chip is incorporated in a pressure-contact type package, and the emitter electrode and collector electrode formed on the main surface are brought into surface contact with a pair of external common electrode substrates provided on the package side, respectively, and pulled out. Attention has been focused on a semiconductor device having a contact structure.

【0004】このパッケージ構造によれば、上記のモジ
ュール型パッケージに比べて、1)半導体チップを両面
から冷却ができるので冷却効率を上げることができる、
2)接続導体のインダクタンス、及び抵抗が小さくな
る、3)主電極の接続がワイヤボンドでなくなるために
接続信頼性が向上する、等の改善がはかれる。
According to this package structure, 1) the semiconductor chip can be cooled from both sides, so that the cooling efficiency can be improved as compared with the above-mentioned module type package.
2) The inductance and resistance of the connection conductor are reduced, and 3) the connection of the main electrode is not wire-bonded, so that the connection reliability is improved.

【0005】ところが、この多チップ並列型の圧接型半
導体装置では、部材寸法ばらつきに起因するチップ位置
毎の高さのばらつきや共通電極板のそりやうねりによる
場所毎のばらつきが避けられず、これによりチップ毎に
加圧力が異なり均一な接触が得られない、すなわち熱抵
抗,電気抵抗がチップ位置毎に大きく異なり、全体とし
ての素子特性が安定しないという大きな問題があった。
最も単純には、寸法の厳密に揃った部材を用いることで
対処できるが、部品のコスト、および選別のコスト等の
アップが避けられない。この問題に対して、特開平8−8
8240号公報においては、Agなどの延性のある軟金属シ
ートを厚さ補正板として介在させる方法を開示してい
る。
However, in this multi-chip parallel type pressure contact type semiconductor device, variations in height at each chip position due to variations in member dimensions and variations in locations due to warpage or undulation of the common electrode plate are inevitable. As a result, there is a large problem that the pressing force varies from chip to chip and uniform contact cannot be obtained, that is, thermal resistance and electric resistance vary greatly from chip position to chip position, and the element characteristics as a whole are not stable.
In the simplest case, it is possible to cope with the problem by using members having strictly uniform dimensions. However, it is unavoidable to increase the cost of parts and the cost of sorting. To solve this problem,
No. 8240 discloses a method in which a ductile soft metal sheet such as Ag is interposed as a thickness correction plate.

【0006】[0006]

【発明が解決しようとする課題】上記のフィラー入りゴ
ムや有機ペースト等の柔軟な材料を用いる方法は、特に
発熱量が大きくなってくると熱伝導率が十分ではない。
また、個別の半導体チップ毎に独立したピストン型やく
し歯型の冷却部材等を用いる方法は低コスト化が難し
い。
The above-mentioned method using a flexible material such as a rubber containing a filler or an organic paste does not have a sufficient thermal conductivity, particularly when the calorific value increases.
Further, it is difficult to reduce the cost by using a piston-type or comb-type cooling member that is independent for each individual semiconductor chip.

【0007】一方、前述の軟金属シートをはさむ方法
は、本発明者らの検討によると少なくとも半導体チップ
を破壊しない実用の圧力範囲ではその変形量がごくわず
か(弾性変形による変形のみ)であり、チップ位置毎の
高さ(及びチップを挟む中間部材等を含めた高さ)のば
らつきが大きい場合にはその変形量が不十分で、均一な
接触を確保できないことが明らかとなった。この原因は
図6に模式図で示したように軟質金属シート面に厚さ方
向に圧力を加えて横方向へ塑性変形させようとした場合
にも、軟質金属シート24を挟む電極部材25,26と
の界面で発生する摩擦力(摩擦抵抗)27のため、軟質
金属材料といえども横方向への変形抵抗が非常に大きく
なってしまうことによると考えられる。変形させるため
に加圧力を上げても、摩擦力も圧力に比例して大きくな
るので塑性変形は容易には起こらない。
On the other hand, according to the method of sandwiching the above-mentioned soft metal sheet, according to the study of the present inventors, the amount of deformation is very small (only deformation due to elastic deformation) at least in a practical pressure range where the semiconductor chip is not broken. When the height of each chip position (and the height including the intermediate member sandwiching the chip, etc.) has a large variation, it is clear that the deformation amount is insufficient and uniform contact cannot be ensured. The cause is that the electrode members 25 and 26 sandwiching the soft metal sheet 24 also when the soft metal sheet surface is subjected to plastic deformation in the lateral direction by applying pressure in the thickness direction as shown in the schematic diagram of FIG. It is considered that due to the frictional force (frictional resistance) 27 generated at the interface with the material, the deformation resistance in the lateral direction becomes extremely large even with a soft metal material. Even if the pressing force is increased for deformation, the plastic deformation does not easily occur because the frictional force also increases in proportion to the pressure.

【0008】特にシート形状のような抵抗を受ける面積
に比べて厚さが非常に小さい場合には、この表面に発生
する摩擦力の影響が支配的となるため、一般に知られて
いる材料の降伏応力を超える圧力を加えても実際には実
質的な塑性変形(流動)が起こらず、軟金属シートの厚
さは加圧の前後でほとんど変わらない。この摩擦抵抗を
下げるために、電極部材表面の粗さを小さくする方法が
考えられるが、ラップ仕上げ等で得られる現実的な加工
粗さの範囲(Rmax1〜0.5μm,Ra0.05〜0.03
μm)では大きな変形は起こらない。
In particular, when the thickness is very small compared with the area receiving the resistance, such as a sheet shape, the influence of the frictional force generated on the surface becomes dominant, so that the generally known yielding of the material occurs. Even if a pressure exceeding the stress is applied, practically no plastic deformation (flow) actually occurs, and the thickness of the soft metal sheet hardly changes before and after pressing. In order to reduce the frictional resistance, a method of reducing the roughness of the electrode member surface is considered. However, a practical range of the processing roughness obtained by lapping or the like (Rmax1 to 0.5 μm, Ra0.05 to 0.5). 03
μm), no significant deformation occurs.

【0009】本発明の目的は、上記のような実装方式の
多チップ並列化に伴って、ますます困難になる大面積領
域での冷却部材との均一な接触状態を確保する方法、す
なわち接触面での高さばらつき(部材寸法ばらつき,反
り,うねり等による)を吸収し、かつ接触界面での熱抵
抗,電気抵抗をも低減できる方法を提供するものであ
る。
An object of the present invention is to provide a method for ensuring a uniform contact state with a cooling member in a large-area area, which becomes more and more difficult with the parallelization of the mounting method as described above, that is, a contact surface. It is intended to provide a method capable of absorbing height variations (due to member size variations, warpage, undulations, etc.) and reducing thermal resistance and electrical resistance at the contact interface.

【0010】また第2の目的は上記により得られる半導
体装置を用いることにより、特に大容量のシステムに好
適な変換器や高速演算制御装置を提供することにある。
It is a second object of the present invention to provide a converter and a high-speed operation control device particularly suitable for a large-capacity system by using the semiconductor device obtained as described above.

【0011】[0011]

【課題を解決するための手段】上記課題は、複数個の半
導体チップが一つの電極基板、又は配線基板上に並置し
て組み込まれ、かつ該半導体チップから発生する熱を該
複数個の半導体チップに共通の放熱部材を介して放熱す
る構造を有する半導体装置において、該半導体チップと
該放熱部材との間に薄板をロール状に加工した金属また
はその集合体を配置することにより解決できる。より好
ましくは、上記ロール状に加工した金属の表面により軟
質、または耐酸化性の良い金属層を形成するか、該ロー
ル状に加工した金属に対向する電極面に軟質金属膜を形
成する。
The object of the present invention is to provide a semiconductor device in which a plurality of semiconductor chips are incorporated side by side on one electrode substrate or a wiring substrate, and the heat generated from the semiconductor chips is generated by the plurality of semiconductor chips. In a semiconductor device having a structure for dissipating heat via a common heat dissipating member, the problem can be solved by disposing a metal obtained by processing a thin plate into a roll or an aggregate thereof between the semiconductor chip and the heat dissipating member. More preferably, a soft or oxidation-resistant metal layer is formed on the surface of the metal processed into the roll shape, or a soft metal film is formed on an electrode surface facing the metal processed into the roll shape.

【0012】[0012]

【発明の実施の形態】本発明の実施の代表的な形態を図
面に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described with reference to the drawings.

【0013】図1に本発明の基本的な適用形態をシート
状に複数の薄板ロール状金属を並べた集合体を用いた例
で示す。半導体チップ1の第一主面には少なくとも第一
の主電極、第二主面には第二の主電極が形成されてい
る。この両主電極面上にMoやW等からなる中間電極板
(中間部材)2,3が配置され、さらにこの中間電極板
の外側部分に一対のCuなどからなる放熱部材を兼ねた
共通電極基板(主電極板)4,5が配置される。中間電極
板3と共通電極基板5の間には複数の薄板ロール状金属
を並べた集合体6が挟まれており、全体が一括に加圧さ
れて各部材間が接触されている。図1では(a),(b),
(c)位置で部品1,2,3の厚さの合計が順に厚くな
るケースを示している。
FIG. 1 shows an example of a basic application of the present invention using an aggregate in which a plurality of sheet metal rolls are arranged in a sheet. At least a first main electrode is formed on the first main surface of the semiconductor chip 1, and a second main electrode is formed on the second main surface. Intermediate electrode plates (intermediate members) 2 and 3 made of Mo, W, or the like are arranged on both main electrode surfaces, and a common electrode substrate also serving as a pair of heat-dissipating members made of a pair of Cu and the like outside the intermediate electrode plates. (Main electrode plates) 4 and 5 are arranged. Between the intermediate electrode plate 3 and the common electrode substrate 5, an assembly 6 in which a plurality of thin-plate roll-shaped metals are arranged is sandwiched, and the whole is pressed at once and the members are in contact with each other. In FIG. 1, (a), (b),
The case where the sum of the thicknesses of the components 1, 2, 3 increases in order at the position (c) is shown.

【0014】これらの高さの差に対応して、加圧接触さ
せる前には一定の厚さを持っていたロール状金属集合体
6の厚さが、加圧接触後には(a),(b),(c)の順に
薄くなっている。すなわち、ロール状金属集合体の高さ
を含めた全体としての高さ(部品1,2,3,6の厚さ
の合計)が(a),(b),(c)位置で同じになるように
ロール状金属集合体の厚さが変化している。
According to the difference between these heights, the thickness of the roll-shaped metal assembly 6 having a constant thickness before the pressure contact is changed to (a), ( b) and (c) become thinner in this order. That is, the overall height including the height of the roll-shaped metal assembly (the sum of the thicknesses of the components 1, 2, 3, and 6) is the same at the positions (a), (b), and (c). Thus, the thickness of the roll-shaped metal aggregate changes.

【0015】これにより、上記部材1,2,3に各々厚
さばらつきがあったり、主電極板4,5にそりやうねり
がある場合でも複数のチップ位置(a),(b),(c)間
で良好な加圧接触状態を確保して半導体素子を実装で
き、従って熱抵抗,電気抵抗のばらつきの少ない加圧接
触型の半導体装置が実現できる。図1では主電極基板5
と中間電極板3の対向して圧接される面にロール状金属
集合体6を挟んだ例を示したが、この位置はもちろん他
の接触面、すなわち主電極基板4と中間電極板2の間や
半導体チップ1と中間電極板2,3の間でも良く、また
複数の界面に対して同時に適用しても構わない。また電
極間ごとに異なる材質のロール状金属を配置してもよ
い。
Accordingly, even when the members 1, 2, 3 have thickness variations, or the main electrode plates 4, 5 have warpage or undulation, a plurality of chip positions (a), (b), (c) are required. The semiconductor element can be mounted while maintaining a good pressure contact state between (1) and (2), so that a pressure contact type semiconductor device with little variation in thermal resistance and electric resistance can be realized. In FIG. 1, the main electrode substrate 5
Although the example in which the roll-shaped metal assembly 6 is interposed between the surfaces of the metal electrode 6 and the intermediate electrode plate 3 which are pressed against each other is shown, this position is of course the other contact surface, that is, between the main electrode substrate 4 and the intermediate electrode plate 2. Or between the semiconductor chip 1 and the intermediate electrode plates 2 and 3, or may be applied to a plurality of interfaces simultaneously. Further, a roll-shaped metal of a different material may be arranged for each electrode.

【0016】IGBTを用いたスイッチングデバイスと
逆並列に接続したフライホイールダイオード(FWD)
を混載実装した逆導通型スイッチングデバイスの実施例
において、実装したチップ位置毎の厚さばらつきが最大
200μmとした場合にも、板厚0.05mm,巻数1
0,太さ1.5mmのロール状金属の集合体を中間電極板
3と共通主電極基板5間に挟み、中間電極板2と共通主
電極基板4間に感圧紙を挟んで圧力分布を測定した結
果、圧力差は小さく、ほぼ均一に加圧されていることが
わかった。
Flywheel diode (FWD) connected in anti-parallel with a switching device using IGBT
In the embodiment of the reverse conduction type switching device in which the thickness of each mounted chip is 200 μm at the maximum, even if the thickness is 0.05 mm and the number of turns is 1
A roll-shaped metal assembly having a thickness of 0.5 mm and a thickness of 1.5 mm is sandwiched between the intermediate electrode plate 3 and the common main electrode substrate 5, and the pressure distribution is measured by sandwiching a pressure-sensitive paper between the intermediate electrode plate 2 and the common main electrode substrate 4. As a result, it was found that the pressure difference was small and the pressure was almost uniformly applied.

【0017】図2には本発明の薄板をロール状に加工し
た金属、及びその集合体の各種形状の代表例を示す。図
2(a)は棒状に巻いた薄板金属7が平面状にきれいに
ならんで配列され、さらにこれらの金属棒7同士が互い
に接着8されて一体の薄板状(シート状)に保持されて
いるものである。これらの接着部を形成する方法として
は、細線を接触させた状態で高温加熱して軽く融着した
り、有機接着材または半田等の低温接合材を用いて接着
する方法がある。
FIG. 2 shows a typical example of a metal obtained by processing a thin plate of the present invention into a roll, and various shapes of an aggregate thereof. FIG. 2 (a) shows a thin sheet metal 7 wound in a bar shape and arranged in a clean and flat manner, and these metal bars 7 are adhered 8 to each other and held in an integrated thin plate (sheet shape). It is. As a method of forming these bonding portions, there is a method in which high-temperature heating is performed in a state where the fine wires are in contact with each other to lightly fuse them, or bonding is performed using a low-temperature bonding material such as an organic bonding material or solder.

【0018】図2(b)はロール状の金属線7が平面で
渦巻き状に配列され、さらにこれらの金属線7同士が互
いに接着8されて一体の円形薄板状(シート状)に保持
された例である。これらの他に、平面でリング(円環)
状に加工した例、径の異なるリング(円環)が複数個組
み合わされた例なども可能である。金属線7同士の接着
は必ずしも必要ではない。いずれも細線の断面形状は円
形の例を示したが、必ずしも円形である必要はなく、も
ちろん偏平な形状でもよい。
In FIG. 2B, roll-shaped metal wires 7 are arranged in a spiral shape in a plane, and these metal wires 7 are bonded to each other 8 to be held in an integrated circular thin plate (sheet shape). It is an example. In addition to these, a ring in a plane
Examples of processing into a shape, examples in which a plurality of rings (rings) having different diameters are combined, and the like are also possible. Adhesion between the metal wires 7 is not always necessary. In each case, the cross-sectional shape of the thin line is an example of a circular shape, but it is not necessarily required to be a circular shape, but may be a flat shape.

【0019】本発明の薄板をロール状に加工した金属の
場合には、前述の一様な厚さをもつ金属箔(薄板)の場
合(図6)と異なり、自身の内部に空隙を有し、この部
分を利用して変形する力を受けた材料が容易に移動でき
るため、加圧方向の変形に対する抵抗が小さく比較的小
さな圧力で大きな変形が得られる。このロール状に加工
した金属の変形により、接触界面の増加とロール状金属
集合体の板厚の減少の効果により電気抵抗,熱抵抗は減
少する。
In the case of the metal obtained by processing the thin plate of the present invention into a roll shape, unlike the case of the above-mentioned metal foil (thin plate) having a uniform thickness (FIG. 6), there is a gap inside itself. Since the material receiving the deforming force can be easily moved by utilizing this portion, the resistance to the deformation in the pressing direction is small, and a large deformation can be obtained with a relatively small pressure. Due to the deformation of the rolled metal, the electrical resistance and the thermal resistance decrease due to the effect of increasing the contact interface and reducing the thickness of the rolled metal aggregate.

【0020】これに対して、一様厚さの軟質金属薄板の
場合には前述したように(図6)、降伏応力を越える圧
力を加えても塑性変形による大きな変形は起こらず、弾
性変形分の小さな変形が起こるだけである。
On the other hand, in the case of a soft metal thin plate having a uniform thickness, as described above (FIG. 6), even if a pressure exceeding the yield stress is applied, large deformation due to plastic deformation does not occur, and elastic deformation does not occur. Only a small deformation of.

【0021】これらの材料は弾塑性変形能を有するた
め、変形後に除荷すると弾性変形分の戻りが見られる
が、ほぼ実装部品間の高さのばらつきに対応した塑性変
形分は保持される。再度加圧する場合には、この弾性変
形分を利用して同じ圧力で十分な接触が確保できる。
Since these materials have elasto-plastic deformation ability, when the load is removed after the deformation, the elastic deformation returns, but the plastic deformation corresponding to the height variation between the mounted components is maintained. When pressurizing again, sufficient contact can be ensured at the same pressure by utilizing this elastic deformation.

【0022】この変形が起こる圧力、および弾塑性変形
挙動は、金属の種類や、見かけの密度(空隙率),薄板
の厚さ,巻数によりコントロールすることが可能で、使
用状況に応じた最適な圧力で最適な量の変形が起こるよ
うに選択することができる。小さい圧力で変形量を大き
くするには、板厚を薄くし、巻数,巻の密度を低くする
のが良い。熱抵抗,電気抵抗の低減の観点からは巻数,
巻の密度を高くするのが好ましい。
The pressure at which this deformation occurs and the elasto-plastic deformation behavior can be controlled by the type of metal, the apparent density (porosity), the thickness of the thin plate, and the number of windings. Pressure can be selected to produce an optimal amount of deformation. In order to increase the amount of deformation under a small pressure, it is preferable to reduce the thickness of the sheet and the number of turns and the density of the turns. From the viewpoint of reduction of thermal resistance and electric resistance, the number of turns,
It is preferable to increase the winding density.

【0023】薄板をロール状に加工した金属を挟む電極
との界面の接触抵抗(電気,熱)も重要な要素となる。
接触抵抗をより小さくするためには、このロール状金属
を挟む部材との界面の接触抵抗を小さくすることが重要
である。このためには、ロール状金属の表面に細線状軟
質金属材料より軟質、または耐酸化性の良い金属層を印
刷,めっき,蒸着等の方法により形成することがよい。
The contact resistance (electricity, heat) at the interface with the electrode sandwiching the metal obtained by processing the thin plate into a roll shape is also an important factor.
In order to further reduce the contact resistance, it is important to reduce the contact resistance at the interface with the member sandwiching the roll-shaped metal. For this purpose, it is preferable to form a metal layer that is softer than the fine linear soft metal material or has better oxidation resistance on the surface of the roll-shaped metal by printing, plating, vapor deposition, or the like.

【0024】高さの補正と電気抵抗,熱抵抗の低減を最
適に実現するために、各半導体素子の主電極,中間電極
板、及び共通電極板のうち互いに対向する少なくとも一
つの接触面間に、ロール状に加工した金属またはその集
合体を挟むだけでなく、さらに軟質の金属箔を同時に配
置してもよい。例えば、上側の主電極板と中間電極板の
間にはAu箔を挿入し、下側の主電極板と中間電極板の
間に軟質金属細線集合体を挿入する等の方法も有効であ
る。または中間電極、または共通電極板の少なくとも一
方の面に、軟質金属薄膜を形成することも有効である。
In order to optimally realize the height correction and the reduction of the electric resistance and the thermal resistance, at least one of the main electrode, the intermediate electrode plate and the common electrode plate of each semiconductor element is opposed to at least one of the opposing contact surfaces. In addition to sandwiching a metal processed into a roll or an aggregate thereof, a softer metal foil may be simultaneously arranged. For example, a method of inserting an Au foil between the upper main electrode plate and the intermediate electrode plate, and inserting a soft metal thin wire assembly between the lower main electrode plate and the intermediate electrode plate is also effective. Alternatively, it is also effective to form a soft metal thin film on at least one surface of the intermediate electrode or the common electrode plate.

【0025】上記のように種類の異なる半導体チップを
一つのパッケージ内に並列実装する場合で、種類毎にそ
の厚さが大きく異なる様な場合には、チップ種に応じて
中間電極板の平均厚さを変えたものを準備しチップ厚さ
の大きな違いを調整し、さらに本発明のロール状に加工
した金属またはその集合体による変形を主に中間電極板
および半導体チップの厚さのばらつきの吸収に用いる方
法も有効である。
In the case where different types of semiconductor chips are mounted in parallel in one package as described above, and when the thickness of each type is greatly different, the average thickness of the intermediate electrode plate depends on the type of chip. By preparing a material with a different thickness, adjusting the large difference in chip thickness, and further absorbing the deformation due to the rolled metal of the present invention or the aggregate thereof mainly by absorbing the thickness variation of the intermediate electrode plate and the semiconductor chip Is also effective.

【0026】ロール状に加工する金属としては、Ni,
SUS,銅,アルミニウム,銀,金,半田等のあらゆる
金属が使用可能であるが、特に低圧力での変形と熱抵抗
の低減には銅,アルミニウム,銀,金等の軟質高熱伝導
性の金属が好ましい。半導体装置の使用形態,目的に応
じて、熱抵抗,電気抵抗の低減、または変形能の向上の
どちらを優先するかによって最適な材質,表面処理を選
択できる。
As the metal to be processed into a roll, Ni,
Any metal such as SUS, copper, aluminum, silver, gold, solder, etc. can be used. In particular, soft high heat conductive metals such as copper, aluminum, silver, gold, etc. are used to reduce deformation and thermal resistance under low pressure. Is preferred. The optimum material and surface treatment can be selected depending on whether the reduction of thermal resistance and electric resistance or the improvement of deformability is prioritized, depending on the usage form and purpose of the semiconductor device.

【0027】上記中間電極の材料としては、熱膨張係数
がSiと外部主電極材料の中間で、熱伝導性,電気伝導
性の良好な材料が用いられる。具体的にはタングステン
(W)やモリブデン(Mo)等の単体金属、またはそれら
を主たる構成材料とするCu−W,Ag−W,Cu−M
o,Ag−Mo,Cu−FeNi等の複合材料または合
金、さらには金属とセラミックスやカーボンとの複合材
料、たとえばCu/SiC,Cu/C,Al/SiC,
Al/AlN等が好ましい。一方、主電極基板には電気
伝導性で熱伝導性の良い銅やアルミニウム、またはそれ
らを含む前述のような合金または複合材料を使用するの
が好ましい。
As the material of the intermediate electrode, a material having a thermal expansion coefficient between that of Si and the material of the external main electrode and having good thermal conductivity and electric conductivity is used. Specifically, tungsten
Metal such as (W) and molybdenum (Mo), or Cu-W, Ag-W, Cu-M using them as main constituent materials
o, Ag-Mo, Cu-FeNi or other composite materials or alloys, and further, composite materials of metals and ceramics or carbon, such as Cu / SiC, Cu / C, Al / SiC,
Al / AlN and the like are preferable. On the other hand, for the main electrode substrate, it is preferable to use copper or aluminum having good electrical conductivity and thermal conductivity, or the above-mentioned alloy or composite material containing them.

【0028】本発明の実装方式は、もちろんダイオード
を含まないIGBT等のスイッチング半導体のみからな
る圧接型半導体装置にも用いることができる他、例えば
ダイオードチップのみを多数個上記の方法で圧接型パッ
ケージに実装することももちろん有効である。また、上
記実施例では、主としてIGBTを用いて説明したが、
本発明は少なくとも第一主面に第一の主電極と第二主面
に第二の主電極を有する半導体素子全般を対象としてお
り、IGBT以外の絶縁ゲート形トランジスタ(MOS
トランジスタ)や、IGCT(Insulated Gate Control
led Thyristor)などを含む絶縁ゲート形サイリスタ(M
OS制御サイリスタ)や、GTO,サイリスタ、及びダ
イオードなどに対しても同様に実施できる。また、Si
素子以外のSiC,GaNなどの化合物半導体素子に対
しても同様に有効である。
The mounting method of the present invention can of course be used for a pressure contact type semiconductor device comprising only a switching semiconductor such as an IGBT which does not include a diode. For example, a large number of diode chips alone can be used in a pressure contact type package by the above method. Implementation is of course also effective. Further, in the above embodiment, the description has been made mainly using the IGBT.
The present invention is directed to a general semiconductor device having at least a first main electrode on a first main surface and a second main electrode on a second main surface, and uses an insulated gate transistor (MOS) other than an IGBT.
Transistor), IGCT (Insulated Gate Control)
led Thyristor) and other insulated gate thyristors (M
An OS control thyristor), a GTO, a thyristor, a diode, and the like can be similarly implemented. In addition, Si
The present invention is similarly effective for compound semiconductor devices such as SiC and GaN other than the device.

【0029】図3は、半導体チップとしてLSIチップ
10を多層配線基板17上に複数個並列実装した多チッ
プ並列実装型半導体装置の例を示す。本実施例ではLS
Iチップ10は小型のセラミック基板12の上に半田ボ
ール11を用いたフリップチップ接続により搭載されて
いる。これにはさらに高熱伝導のキャップ13が半田付
け14され、LSIチップ10を気密封止している。L
SIチップ10の裏面(素子を形成してない面、図の上
面)は、熱抵抗を低減するためにキャップ材13と半田
接合15されている。
FIG. 3 shows an example of a multi-chip parallel mounting type semiconductor device in which a plurality of LSI chips 10 as semiconductor chips are mounted on a multilayer wiring board 17 in parallel. In this embodiment, LS
The I chip 10 is mounted on a small ceramic substrate 12 by flip chip connection using solder balls 11. In this case, a cap 13 having high thermal conductivity is further soldered 14 to hermetically seal the LSI chip 10. L
The back surface (the surface on which no elements are formed, the upper surface in the figure) of the SI chip 10 is solder-bonded 15 to the cap material 13 to reduce thermal resistance.

【0030】これらのあらかじめ小型パッケージに実装
されたLSIチップを複数個、多層回路基板17上に半
田ボール16を用いて実装した。小型パッケージの高
さ、及び半田ボール高さのばらつきにより小型パッケー
ジの上面の高さは、LSIチップの位置ごとに異なって
いる。従って、このまま放熱部材19を接触させた場合
には高さの低い小型パッケージには接触しない場合が発
生する。
A plurality of these LSI chips previously mounted in a small package were mounted on a multilayer circuit board 17 using solder balls 16. Due to variations in the height of the small package and the height of the solder balls, the height of the upper surface of the small package differs for each position of the LSI chip. Therefore, if the heat dissipating member 19 is kept in contact with the small package, the small package having a small height may not be contacted.

【0031】本実施例では、小型パッケージの上面と放
熱部材19の間に、本発明の薄板をロール状に加工した
金属7を配置した。本実施例では、まずロール状金属7
を複数個配列し半田20で保持した材料をあらかじめ作
製した。ロール状金属7の内部空間は半田で充填されて
おらず変形能は確保されている。これを小型パッケージ
の上面と放熱部材(冷却部材)19の間に配置し加圧して
高さばらつきを吸収するよう変形させる。続いて半田2
0を溶融して小型パッケージの上面と放熱部材19の下
面に接着した。上記方法の変わりに、複数のロール状金
属と半田箔を挟んで加圧,加熱することも可能である。
他に半田ペーストを用いて、ロール状金属集合体の表面
に半田層を印刷することもできる。この多層回路基板1
7の半導体チップ搭載面と反対の面にはI/Oピン、ま
たは電源ピン18が多数設けられており、LSIとの配
線接続を行う。
In this embodiment, the metal 7 obtained by processing the thin plate of the present invention into a roll is disposed between the upper surface of the small package and the heat radiating member 19. In this embodiment, first, the rolled metal 7
Were arranged in advance and a material held by the solder 20 was prepared in advance. The internal space of the roll-shaped metal 7 is not filled with solder, and the deformability is secured. This is arranged between the upper surface of the small package and the heat dissipating member (cooling member) 19, and is deformed by applying pressure to absorb height variations. Then solder 2
0 was melted and bonded to the upper surface of the small package and the lower surface of the heat dissipating member 19. Instead of the above method, it is also possible to press and heat a plurality of roll-shaped metals and solder foils therebetween.
Alternatively, a solder layer can be printed on the surface of the roll-shaped metal assembly using a solder paste. This multilayer circuit board 1
A large number of I / O pins or power supply pins 18 are provided on the surface opposite to the semiconductor chip mounting surface of No. 7 to perform wiring connection with the LSI.

【0032】多層回路基板17は、セラミック基板,プ
リント基板等が用いられる。半導体チップ10、及び小
型基板12の配線接続には半田ボールを用いる方法のほ
かにTAB,PGA,BGA,ワイヤボンド等の方法を
適宜用いることができる。さらに半導体チップ10を本
実施例のように小型パッケージに実装することなく、多
層回路基板17に直接搭載する、いわゆるベアチップ実
装することも可能である。この場合にも気密封止が必要
なら、基板17と冷却部材19の間で側面を封止(図示
せず)する構造とすればよい。冷却方式は、空冷,水
冷、その他の液冷等の方法を用いることが可能で、放熱
部材19には内部に冷却媒体の流路を形成したり、外表
面に放熱効率がよいフィン形状の加工を施し冷却効率を
向上させることが好ましい。
As the multilayer circuit board 17, a ceramic board, a printed board, or the like is used. For the wiring connection between the semiconductor chip 10 and the small substrate 12, a method such as TAB, PGA, BGA, wire bonding or the like can be used as appropriate in addition to the method using solder balls. Further, it is also possible to mount the semiconductor chip 10 directly on the multilayer circuit board 17 without mounting the semiconductor chip 10 in a small package as in the present embodiment, that is, a so-called bare chip mounting. In this case, if air-tight sealing is required, a structure in which the side surface is sealed (not shown) between the substrate 17 and the cooling member 19 may be adopted. As a cooling method, a method such as air cooling, water cooling, or other liquid cooling can be used. The heat dissipating member 19 has a cooling medium flow path formed inside or a fin-shaped processing having good heat dissipating efficiency on the outer surface. To improve the cooling efficiency.

【0033】本発明の多チップ並列実装型半導体装置で
は、大型化(大容量化)しても熱を放散する放熱部材と
の均一な接触状態が得られるため、熱抵抗の小さな半導
体装置が得られる。従って、この半導体装置を用いるこ
とにより、電力変換器としては、変換器容積、及びコス
トを大幅に削減した大容量変換器が実現できるようにな
る。一方、演算制御装置としては特に発熱量が大きい高
速演算装置や高性能制御装置を実現できる。
In the multi-chip parallel mounting type semiconductor device of the present invention, a uniform contact state with a heat dissipating member that dissipates heat can be obtained even when the size (capacity) is increased, so that a semiconductor device with low thermal resistance is obtained. Can be Therefore, by using this semiconductor device, a large-capacity converter can be realized as a power converter in which the volume and cost of the converter are significantly reduced. On the other hand, as an arithmetic and control unit, a high-speed arithmetic unit and a high-performance control unit that generate a large amount of heat can be realized.

【0034】図4には本発明によるIGBTの半導体装
置を主変換素子として電力用変換器に応用した場合の1
ブリッジ分の構成回路図を示す。主変換素子となるIG
BT素子21とダイオード素子22が逆並列に配置さ
れ、これらがn個直列に接続された構成となっている。
これらIGBTとダイオードは、本発明による多数の半
導体チップを並列実装した半導体装置を示している。上
記実施例の逆導通型IGBT半導体装置の場合には図中のI
GBTチップとダイオードチップがまとめて一つのパッ
ケージに収められた形となる。
FIG. 4 shows a case where the IGBT semiconductor device according to the present invention is applied to a power converter as a main conversion element.
FIG. 3 shows a configuration circuit diagram for a bridge. IG to be the main conversion element
The BT element 21 and the diode element 22 are arranged in anti-parallel, and n pieces are connected in series.
These IGBTs and diodes represent a semiconductor device in which a number of semiconductor chips according to the present invention are mounted in parallel. In the case of the reverse conducting IGBT semiconductor device of the above embodiment, I in FIG.
The GBT chip and the diode chip are put together in one package.

【0035】これにスナバ回路23、及び限流回路が設
けてある。図5は、図4の3相ブリッジを4多重した自
励式変換器の構成を示したものである。本発明の半導体
装置は、複数個をその主電極板外側と面接触する形で水
冷電極を挟んで直列接続するスタック構造と呼ぶ形に実
装され、スタック全体を一括で加圧する。本発明によれ
ば、従来より低い加圧力でも均一な接触が得られるの
で、上記スタック構造等を簡略化できるという効果もあ
る。
This is provided with a snubber circuit 23 and a current limiting circuit. FIG. 5 shows a configuration of a self-excited converter in which the three-phase bridge of FIG. 4 is multiplexed by four. The semiconductor device of the present invention is mounted in a so-called stack structure in which a plurality of semiconductor devices are connected in series with a water-cooled electrode therebetween in such a manner as to make surface contact with the outside of the main electrode plate, and pressurize the entire stack at once. According to the present invention, uniform contact can be obtained even with a lower pressing force than in the past, so that the stack structure and the like can be simplified.

【0036】本発明の半導体装置は、上記の例に限らず
電力系統に用いられる自励式大容量変換器やミル用変換
器として用いられる大容量変換器に特に好適で、可変速
揚水発電,ビル内変電所設備,電鉄用変電設備,ナトリ
ウム硫黄(NaS)電池システム,車両等の変換器にも
用いることができる。
The semiconductor device of the present invention is not particularly limited to the above example, and is particularly suitable for a self-excited large-capacity converter used in a power system or a large-capacity converter used as a mill converter. It can also be used for converters in internal substation facilities, substation facilities for electric railways, sodium sulfur (NaS) battery systems, vehicles and the like.

【0037】[0037]

【発明の効果】本発明によれば、高速化や大容量化に対
応する半導体チップの多チップ並列実装化に伴って、ま
すます困難になる大面積域での熱を放散する放熱部材と
の均一接触を比較的簡単に実現することができる、すな
わち接触面の高さのばらつきを十分に吸収し、かつ接触
界面での熱抵抗を低減できる。
According to the present invention, a heat dissipating member for dissipating heat in a large area, which is becoming more and more difficult with the multi-chip parallel mounting of semiconductor chips corresponding to high speed and large capacity, is required. Uniform contact can be achieved relatively easily, that is, variations in the height of the contact surface can be sufficiently absorbed, and thermal resistance at the contact interface can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例である半導体装置の一部を示す
断面図。
FIG. 1 is a sectional view showing a part of a semiconductor device according to an embodiment of the present invention.

【図2】ロール状に加工した金属集合体の実施形態の代
表例を示す図。
FIG. 2 is a view showing a typical example of an embodiment of a metal aggregate processed into a roll.

【図3】LSI実装に適用した本発明の実施例を示す側
断面図。
FIG. 3 is a side sectional view showing an embodiment of the present invention applied to LSI mounting.

【図4】本発明の半導体装置を用いた1ブリッジ分の構
成回路図。
FIG. 4 is a configuration circuit diagram of one bridge using the semiconductor device of the present invention.

【図5】図4の3相ブリッジを4多重した自励式変換器
の構成図。
5 is a configuration diagram of a self-excited converter in which the three-phase bridge of FIG. 4 is multiplexed by four.

【図6】従来方式で加圧した場合の軟質金属の変形挙動
を説明する図。
FIG. 6 is a view for explaining the deformation behavior of a soft metal when pressurized by a conventional method.

【符号の説明】[Explanation of symbols]

1…半導体チップ、2,3…中間電極板(中間部材)、
4,5…共通電極基板、6…ロール状に加工した金属ま
たはその集合体、7…ロール状に加工した金属細線、8
…接着部、10…LSIチップ、11,16…半田ボー
ル、12…小型セラミック基板、13…キャップ、1
4,15,20…半田、17…多層回路基板、18…ピ
ン、19…放熱部材(冷却部材)、21…IGBT素
子、22…ダイオード素子、23…スナバ回路、24…
軟質金属シート、25,26…電極部材、27…摩擦力
(摩擦抵抗)。
1 ... semiconductor chip, 2, 3 ... intermediate electrode plate (intermediate member),
4, 5: common electrode substrate, 6: metal processed into a roll shape or an aggregate thereof, 7: thin metal wire processed into a roll shape, 8
... Adhesive part, 10 ... LSI chip, 11, 16 ... Solder ball, 12 ... Small ceramic substrate, 13 ... Cap, 1
4, 15, 20 solder, 17 multilayer circuit board, 18 pin, 19 heat dissipation member (cooling member), 21 IGBT element, 22 diode element, 23 snubber circuit, 24
Soft metal sheet, 25, 26 ... electrode member, 27 ... frictional force (frictional resistance).

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】複数個の半導体チップが一つの電極基板、
又は配線基板上に並置して組み込まれ、かつ該半導体チ
ップから発生する熱を該複数個の半導体チップに共通の
放熱部材を介して放熱する構造を有する半導体装置であ
って、該半導体チップと該放熱部材との間に薄板をロー
ル状に加工した金属またはその集合体を配置したことを
特徴とする多チップ並列実装型半導体装置。
A plurality of semiconductor chips each comprising one electrode substrate;
Or a semiconductor device having a structure which is incorporated in juxtaposition on a wiring substrate and radiates heat generated from the semiconductor chip to the plurality of semiconductor chips through a common heat radiating member. A multi-chip parallel mounting type semiconductor device, wherein a metal obtained by processing a thin plate into a roll or an aggregate thereof is disposed between the heat radiating member and the heat radiating member.
【請求項2】第一主面に少なくとも第一の主電極、第二
主面に第二の主電極を有する複数個の半導体素子を一対
の放熱部材を兼ねる共通電極基板の間に並置して組み込
んだ半導体装置であって、該半導体チップと共通電極基
板の電極間に薄板をロール状に加工した金属またはその
集合体を配置したことを特徴とする多チップ並列実装型
半導体装置。
2. A plurality of semiconductor elements having at least a first main electrode on a first main surface and a second main electrode on a second main surface are juxtaposed between a pair of common electrode substrates serving also as heat radiating members. A multi-chip parallel mounting type semiconductor device, wherein a metal or a set of rolled thin plates is arranged between the semiconductor chip and an electrode of a common electrode substrate.
【請求項3】該半導体チップがパッケージングされた状
態で一つの電極基板、又は配線基板上に並置して実装さ
れていることを特徴とする請求項1及び2記載の多チッ
プ並列実装型半導体装置。
3. The multi-chip parallel mounted semiconductor according to claim 1, wherein said semiconductor chips are packaged and mounted side by side on one electrode substrate or a wiring substrate. apparatus.
【請求項4】該半導体チップとこれを搭載する電極基
板,配線基板、又は放熱部材の間に、前記両部材の間の
熱膨張係数を有する中間部材を介したことを特徴とする
請求項1乃至3記載の多チップ並列実装型半導体装置。
4. An intermediate member having a thermal expansion coefficient between the semiconductor chip and an electrode substrate, a wiring substrate, or a heat radiating member on which the semiconductor chip is mounted. 4. The multi-chip parallel mounting type semiconductor device according to any one of items 3 to 3.
【請求項5】前記薄板をロール状に加工した金属の集合
体が平面状に配列されて一体の板状に保持されているこ
とを特徴とする1乃至4記載の多チップ並列実装型半導
体装置。
5. A multi-chip parallel mounting type semiconductor device as set forth in claim 1, wherein an assembly of metal obtained by processing said thin plate into a roll is arranged in a plane and held as an integral plate. .
【請求項6】前記薄板をロール状に加工した金属が主と
してCu,Al,Ag,Auまたは半田からなることを
特徴とする請求項1乃至5記載の多チップ並列実装型半
導体装置。
6. The multi-chip parallel mounting type semiconductor device according to claim 1, wherein the metal obtained by processing the thin plate into a roll is mainly made of Cu, Al, Ag, Au or solder.
【請求項7】前記薄板をロール状に加工した金属の表面
に、より軟質、または耐酸化性の良い金属層が形成され
ていることを特徴とする請求項1乃至6記載の多チップ
並列実装型半導体装置。
7. The multichip parallel mounting according to claim 1, wherein a softer or more oxidation-resistant metal layer is formed on a surface of the metal obtained by processing the thin plate into a roll. Type semiconductor device.
【請求項8】複数個の半導体チップが一つの電極基板、
又は配線基板上に並置して組み込まれ、かつ該半導体チ
ップから発生する熱を該複数個の半導体チップに共通の
放熱部材を介して放熱する構造を有し、さらに該半導体
チップと該放熱部材との間に薄板をロール状に加工した
金属またはその集合体を配置した多チップ並列実装型半
導体装置を主変換素子として用いたことを特徴とする電
力変換器。
8. The method according to claim 8, wherein the plurality of semiconductor chips are one electrode substrate.
Or a structure in which heat generated from the semiconductor chip is radiated through a common heat radiating member to the plurality of semiconductor chips, and the semiconductor chip and the heat radiating member are combined. A power converter characterized by using a multi-chip parallel mounting type semiconductor device in which a metal obtained by processing a thin plate into a roll or an aggregate thereof is used as a main conversion element.
【請求項9】複数個の半導体チップが一つの電極基板、
又は配線基板上に並置して組み込まれ、かつ該半導体チ
ップから発生する熱を該複数個の半導体チップに共通の
放熱部材を介して放熱する構造を有し、さらに該半導体
チップと該放熱部材との間に薄板をロール状に加工した
金属またはその集合体を配置した多チップ並列実装型半
導体装置を用いたことを特徴とする演算制御装置。
9. The method according to claim 9, wherein the plurality of semiconductor chips are one electrode substrate.
Or a structure in which heat generated from the semiconductor chip is radiated through a common heat radiating member to the plurality of semiconductor chips, and the semiconductor chip and the heat radiating member are combined. An arithmetic and control unit characterized by using a multi-chip parallel mounting type semiconductor device in which a metal obtained by processing a thin plate into a roll or an aggregate thereof is disposed.
JP34755497A 1997-12-17 1997-12-17 Multi-chip parallel mounting type semiconductor device Pending JPH11186471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34755497A JPH11186471A (en) 1997-12-17 1997-12-17 Multi-chip parallel mounting type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34755497A JPH11186471A (en) 1997-12-17 1997-12-17 Multi-chip parallel mounting type semiconductor device

Publications (1)

Publication Number Publication Date
JPH11186471A true JPH11186471A (en) 1999-07-09

Family

ID=18391021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34755497A Pending JPH11186471A (en) 1997-12-17 1997-12-17 Multi-chip parallel mounting type semiconductor device

Country Status (1)

Country Link
JP (1) JPH11186471A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015511070A (en) * 2012-03-30 2015-04-13 レイセオン カンパニー Conductive cooling of multi-channel flip chip based panel array circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015511070A (en) * 2012-03-30 2015-04-13 レイセオン カンパニー Conductive cooling of multi-channel flip chip based panel array circuits

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