JPH11203342A - Scannet design method and system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the wiring length of a scan net and the processing time thereof. In a scan net design method for designing a scan net provided for detecting a failure of a logic circuit, the logic circuit is divided into a plurality of small logic blocks,
A layout configuration for arranging the blocks in consideration of the connection between the blocks is performed, the number of flip-flops is calculated for each block, and based on the calculation result of the number of flip-flops and the distance between the blocks, Adjacent blocks are grouped together and divided into a plurality of groups, and the flip-flops of the blocks belonging to each group are connected by one scan net and wired by changing the connection order so that the wiring length is shortened. A step of generating a test pattern for detecting a failure of the logic circuit in the scan net.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan net design method and system for designing a scan net provided for detecting a fault in a logic circuit, and more particularly to a scan net design method and system for shortening the scan net wiring length. It is about technology that is effective to apply.

[0002]

2. Description of the Related Art Hitherto, it has been widely practiced to incorporate a scan net into an LSI for testing a logic circuit.
A scan net is a net in which flip-flops included in an LSI are connected in a daisy chain. Both ends are connected to an LSI pin, and the start point is called a scan-in pin and the end point is called a scan-out pin.

In an LSI test using this scan net, first, scan-in data is input from a scan-in pin, a value is stored in each flip-flop, and a circuit is operated by operating a clock. To take out to the scan-out pin.

At this time, if the scan-out data is in accordance with an expected value calculated in advance, it is determined that there is no defect in the LSI, and if it is not in accordance with the expected value, it is determined that there is a manufacturing defect.

In general, not only one scan net but a plurality of scan nets are provided in an LSI. The greater the number, the smaller the number of flip-flops per scan net, so that the time spent on scan-in / scan-out is shortened and the test cost is reduced.

However, since the number of LSI pins is fixed, the number of pins that can physically take scan-in / scan-out pins is limited, and if a general logic pin is also used as a scan-in pin / scan-out pin, a general logic pin is used. Is not always able to increase the number of scan nets because it is affected by delay. There are also cases where there is a limit on scan data that can be simultaneously input and output due to the limitations of the tester.

[0007] Therefore, the designer is required to reduce the test cost, LS
It is necessary to determine the number of scan chains in consideration of the number of I pins, the influence of delay on general logic, and the like.

A conventional scan net design method will be described with reference to FIG. FIG. 14 is a diagram showing a configuration of a conventional system for designing a scan net.

In the conventional scan net design, the designer inputs various information from the terminal 200 while the computer 2
10 to perform processing necessary for LSI design
227, and the processing result is stored in the disk 230.

[0010] In the conventional scan net design procedure, first, in the logical file input processing unit 220 shown in FIG.
It starts by inputting a logical file describing the logic to be realized as an LSI with an abstraction level called RTL (register transfer level). At this time, the logic is generally divided into small logics called a plurality of blocks, and a logical file is input for each block. The processing result of the logical file input is stored in the RTL logical data 231.

When the input of the logical file is completed, the RTL floor plan processing unit 221 performs an RTL floor plan for arranging the blocks in the LSI frame. Information on the arrangement result is stored in the block arrangement data 232. In the RTL floor plan, a rough delay calculation for the inter-block net is performed, and a critical delay defect is extracted early before calculating the delay in the detailed floor plan described later.

Next, in the logic synthesis processing unit 222, the RTL
The logic described is converted to a gate level, and a logic synthesis process for inserting a scan net is performed. The logic after the logic synthesis is stored in the gate logic data 233, and the scan net insertion processing unit 223 further stores the logic in the gate logic data 233.
Is added to the scan information. As a method of connecting flip-flops by a scan net in the scan net insertion processing unit 223, generally, a method of automatically connecting flip-flops in an ascending or descending order of identification information called instance names attached to the flip-flops is generally adopted.

Further, at the time of the connection, the number of flip-flops per scan net determined by the designer is specified.

When the insertion of the scan net is completed, the floor plan of the block is corrected in the detailed floor plan processing section 224, the gate placement processing in the gate placement processing section 225, the wiring processing in the wiring processing section 226, and finally the test pattern. L in the generation processing unit 227
A test pattern for the SI test is generated. The layout information after processing by the wiring processing unit 226 is arrangement / wiring data 234, and the processing result of the test pattern generation processing unit 227 is test data 235. In the conventional method, the process of shortening the scan net is performed by the wiring processing unit 226.

Another conventional technique is disclosed in Japanese Unexamined Patent Publication No.
No. 0889992, entitled "Automatic detection method of approximate shortest connection order in generation of shift register type scan circuit". In the prior art, the connection order is determined for all the flip-flops of the LSI while dividing the entire LSI into four based on a certain standard.

[0016]

SUMMARY OF THE INVENTION As a result of studying the above prior art, the present inventor has found the following problems.

In the above-mentioned conventional method, the processing for shortening the scan net is performed by the wiring processing unit 226. Therefore, the connection order of the flip-flops connected by the scan net insertion processing unit 223 is reviewed based on the flip-flop arrangement position in the gate arrangement processing unit 225, and the net reassignment process is performed so that the scan net length becomes short. However, the scan net replacement is performed only in the flip-flop connection order within the same scan net, and the flip-flop connection order is not switched between the scan nets. Therefore, the reconnection of the net by the wiring processing unit 226 cannot expect a great effect in shortening the wiring length of the scan net. This situation will be described in detail with reference to FIG. FIG.
(A) is a situation after the gate arrangement processing is performed by the gate arrangement processing unit 225. The blocks 300 to
309 (block names a to i), and the blocks 301 to 309 have flip-flops 311 to 31.
9 (the instance names are A to I). At the time of FIG. 15A, the scan net 3 is processed by the scan net insertion
20 to 322 are detached. Here, the maximum number of flip-flops per scan net is three. FIG. 15B shows a state after the wiring processing is performed by the wiring processing unit 226. In the scan nets 320 to 322, the connection order of the flip-flops is exchanged so as to shorten the wiring length to form the scan nets 330 to 332, but the flip-flops included in the scan nets do not change.

However, since the scan net connection taking into account the position of the flip-flop is not performed in the scan net insertion processing unit 223 in the first place, the scan net 331,
There is a problem that a large effect of shortening the wiring length cannot be expected because the wiring may run diagonally in the LSI 300 as in 332.

Further, Japanese Patent Application Laid-Open No. 09-089 of the prior art described above.
In Japanese Patent Application Laid-Open No. 992, since the flip-flop connection order is determined over the entire LSI, the effect of shortening the wiring length can be expected, but the processing becomes complicated and the processing time becomes long.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a technique capable of shortening a scan net wiring length and a processing time thereof. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a scan net design method for designing a scan net provided for detecting a fault in a logic circuit,
The logic circuit is divided into a plurality of small logic blocks, a floor plan for arranging the blocks in consideration of the connection between the blocks is performed, the number of flip-flops is calculated for each block, and the number of flip-flops is calculated. Based on the calculation result of the above and the distance between the blocks, adjacent blocks are respectively grouped into a plurality of groups, and the connection order of the flip-flops of the blocks belonging to each group is changed so that the wiring length is shortened. The method includes a step of connecting and wiring each with one scan net, and generating a test pattern for detecting a failure of a logic circuit with the scan net.

Further, after being divided into the plurality of groups,
The distance between each flip-flop and the center of gravity of the group to which the flip-flop belongs is calculated, and when the calculation result exceeds the reference distance, the group closest to the flip-flop arrangement position is calculated, and the calculated value is calculated. Including the flip-flop in a group.

Further, in a scan net design system for designing a scan net provided for detecting a failure in a logic circuit, a logic file to be realized is divided into a plurality of small logic blocks, and the small logic data is input to a file. Input processing means, floor plan processing means for arranging the blocks in consideration of the connection between the blocks, and conversion of each logical data inputted to the logical file input processing means to data of an element group for realizing the logical data Logic synthesizing means for calculating, the number of flip-flops for calculating the number of flip-flops for each block from the element group data by the logic synthesizing means, the calculation result of the number of flip-flops and the distance between the blocks Group that divides adjacent blocks into multiple groups based on Allocation processing means, detailed floor plan processing means for correcting the physical arrangement of each block based on the data of the element group, element arrangement processing means for arranging the element group for each block, and the element The distance between each of the flip-flops arranged by the arrangement processing means and the center of gravity of the group to which the flip-flop belongs is calculated. If the calculation result exceeds the reference distance, the group closest to the arrangement position of the flip-flop is calculated. And the scan net connection changing means for including the flip-flops in the calculated group and the flip-flops of the blocks belonging to each group are changed in connection order such that the wiring length is shortened to one each. Wiring processing means for connecting and wiring by scan nets; and a circuit for detecting a failure of a logic circuit for each scan net. And a test pattern generating means for generating the door pattern.

Further, in a scan net design system for designing a scan net provided for detecting a failure in a logic circuit, a logic file to be realized is divided into a plurality of small logic blocks, and the small logic data is inputted into a file. Input processing means, floor plan processing means for arranging the blocks in consideration of the connection between the blocks, and conversion of each logical data inputted to the logical file input processing means to data of an element group for realizing the logical data Logic synthesizing means, a flip-flop number calculating means for calculating the number of flip-flops for each block from the element group data by the logic synthesizing means, and a plurality of groups for dividing the adjacent blocks into a plurality of groups. Grouping information obtained from scannet designers Acquisition processing means, group assignment processing means for dividing each block into a plurality of groups based on the calculation result of the flip-flop number calculation means and the grouping information, and physical assignment of each block based on the data of the element group. Detailed floorplan processing means for correcting the global arrangement, element arrangement processing means for arranging the element group for each block, each flip-flop arranged by the element arrangement processing means, and a group to which the flip-flop belongs Is calculated, and when the calculation result exceeds the reference distance, a group closest to the flip-flop arrangement position is calculated, and the scan group including the flip-flop in the calculated group is calculated. And the flip-flops of the blocks belonging to each group so as to reduce the wiring length. It includes a routing processing means for wiring connected by one scan nets respectively interchanged order, a test pattern generating means for generating a test pattern for performing failure detection logic circuit the each scan net.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the configuration of a scan net design system for implementing a scan net design according to an embodiment of the present invention.

As shown in FIG. 1, the scan net design system according to the present embodiment has a terminal 2 on which a designer inputs information.
00, a computer 210 for performing calculations based on the input information, and a disk 230 for storing the calculation results.

The above-described computer 210 includes a logical file input processing unit 220 and an RTL floor plan processing unit 221.
, Logic synthesis processing unit 222, flip-flop number calculation processing unit 100, scan group assignment processing unit 10
1, a grouping information acquisition unit 101A, a scan net insertion processing unit 223, and a detailed floor plan processing unit 22
4, a gate arrangement processing unit 225, a scan chain reassignment processing unit 102, a wiring processing unit 226, and a test pattern generation processing unit 227.

The disk 230 is composed of a disk 230 storing RTL logical data 231, block arrangement data 232, gate logical data 233, arrangement / wiring data 234, and test data 235.

The same components as those shown in FIG. 14 described in the prior art are denoted by the same reference numerals. In FIG. 1, 200 to 235 correspond thereto. 1 shown in FIG.
00, 101, 101A, and 102 and 400, 90
Numerals 0 and 1000 are newly added portions for realizing the scan net design system of the present embodiment. In this embodiment, only the newly added part will be described.

The flip-flop number calculation processing section 100
The logic synthesis processing unit 222 reads the gate logic data 233 as the logic synthesis result, and performs a process of calculating the number of flip-flops of each block.

The grouping information acquisition processing unit 101A
A process of acquiring grouping information defining a scan group to which each block belongs from a designer is performed.

Scan group assignment processing unit 101
Performs a process of assigning a scan group number to each block based on the grouping information when the grouping information is acquired by the grouping information acquisition processing unit 101A described above. A process of assigning a scan group number to each block based on the distance and the number of flip-flops calculated by the flip-flop number calculation processing unit 100 is performed.

The scan chain reassignment processing unit 10
2 performs a process of replacing the flip-flop with a scan chain of a neighboring scan group when the flip-flop is arranged beyond the frame of the scan group to which the flip-flop belongs.

Reference numerals 400, 900, and 1000 denote a scan group table, a block frame table, and a replacement FF table, respectively, added for this embodiment.

Next, the processing of the above-described flip-flop number calculation processing section 100 and scan group assignment processing section 101 will be described with reference to FIGS.

A scan group table 400 shown in FIGS. 2 to 5 is a table used for scan group assignment. A module 410 stores a block name of a block constituting an LSI, and a flip-flop number 420 indicates each block. , The origin 430 and the diagonal point 440 are the RTL floor plan 2
This is a column for storing the coordinates of the origin and the diagonal point of the arrangement frame of the block determined in 21. Also, distance 450
Is a column for storing the distance between blocks, and the scan group number 460 is a column for storing the scan group number of each block determined by scan group assignment.

FIGS. 6 to 8 show the LSI used in this embodiment.
300, which is the same as FIG. 15 shown in the prior art. However, unlike FIG. 15, the number of flip-flops present in each block is not one but a numerical value surrounded by a circle in a block frame. For example, the number of flip-flops in block a is two, and the number of flip-flops in block g is four. The coordinate origin at the time of layout is LSI300
, And the horizontal direction is the y-axis and the vertical direction is the x-axis.

The origin 430 shown in FIGS. 2 to 5 indicates the side of the block frame closer to the coordinate origin, that is, the upper left vertex of the block frame, and the diagonal point 440 is far from the coordinate origin of the block frame. Shows the side, that is, the lower right vertex of the block frame. For example, the origin of block a shown in FIG.
The diagonal point is 502, specifically, the origin (0, 0) and the diagonal point (200, 200).

In the processing of the number-of-flip-flops calculation processing unit 100, first, the gate logical data 233 is read, and information on the module name of each module and the number of flip-flops is stored in the module 410 and the number of flip-flops 420 of the scan group table 400. .

The gate logic data 233 includes the gate names of all the gates constituting the logic and an instance name for identifying each gate. Since the block to which the gate belongs can be identified from the instance name, the flip-flop number calculation processing unit 100 of the present embodiment calculates the number of flip-flops using this. FIG. 2 shows the state of the scan group table 400 at this time.

Next, the scan group assignment processing section 1
01 will be described with reference to the flowchart shown in FIG. In the process of the scan group assignment processing unit 101, when the grouping information is input from the designer, the scan group is assigned based on the grouping information. Therefore, the grouping information is not input here. A description will be given of a process performed when a scan group is assigned based on the distance between blocks and the number of flip-flops calculated by the flip-flop number calculation processing unit 100.

As shown in FIG. 9, the scan group assignment processing unit 101 first reads the block arrangement data 232 and inserts the coordinates of the frame of each block into the origin 430 and the diagonal point 440 of the scan group table 400. (Step 600) Further, the scan group number 460 of each block is cleared to "0" for initial value setting (Step 601), and the scan group number counter is cleared to "0" (Step 602). The scan group number counter shown here is a work area temporarily used in the scan group assignment processing, and is an area storing the scan group number being processed.

Next, 1 is set to the scan group number counter.
Is added (step 603). First this step 60
When the process 3 is performed, the scan group number counter is "1". That is, the block belonging to the scan group with the scan group number 1 is to be determined. First, one block belonging to scan group number 1 is determined. In this embodiment,
Scan group number 460 is the first sort key, origin 4
Using the y-coordinate of the scan group 30 as the second sort key and the x-coordinate of the origin 430 as the third sort key, the scan group table 40
0, and scan group table 4 after sorting
The first entry of 00 is a block that first belongs to scan group number 1 (step 604). This state is the scan group table 400 shown in FIG.

Here, the reason why the scan group number 460 is used as the first sort key is that when the block belonging to the scan group number 2 is determined, the process of step 604 is performed again. The block has a scan group number 460 "
1 ", scan group number 4 of the block which does not belong
Reference numeral 60 denotes “0” as it was in the processing of step 601.
This is because the blocks for which the scan group is not determined at the time of sorting are gathered at the top of the scan group table 400.

Next, since the first block belonging to the scan group number 1 is "a", the distance between the block a and another block is determined and stored in the distance 450 (step 605). In the present embodiment, as shown in FIG. 7, the distance between the centers of gravity of the blocks is used.

Then, in order to rearrange the scan group table 400 in the order closer to the block a, the scan group table 400 is sorted by the distance 450 (step 606). This state is the scan group table 400 shown in FIG. From this state, blocks belonging to scan group number 1 are determined. Before that, the value of the entry counter is set to 1 (step 60).
7) The scan group table 40 is stored in the FF counter.
The value of the flip-flop number 420 of the first entry of 0 is set (step 608), and the value of the scan group number counter is set to the scan group number of the first entry of the scan group table 400 (step 609). The entry counter and the number of FFs shown here are work areas temporarily used in the processing of the scan group assignment processing unit 101, and the entry counter is a counter indicating an entry of the scan group table 400. The number counter is an area for storing the total number of flip-flops of the block belonging to the scan group number.

Next, it is confirmed whether a scan group number has been assigned to all blocks in the scan group table 400, and if so, the process is terminated (step 610). In the present embodiment, when step 610 is first processed, of the nine blocks, only the block a is assigned a scan group number, so that the process proceeds to step 611 as the next process.

In step 611, the value of the entry counter is incremented by 1 to refer to the next entry of the scan group table 400, and the number of flip-flops of the next block is read from the scan group table 400 using the value of the entry counter. The value is added to the number counter (step 612).

If the value of the FF counter exceeds the maximum number of FFs specified in advance by another means, the process returns to step 603 to process the next scan group (step 613). The current scan group number is input to the scan group number 460 of the group table 400 (step 614).
FIG. 5 shows the state of the scan group table 400 when the scan group of scan group number 1 is determined. When the present embodiment is completed, the blocks belonging to scan group number 1 are blocks a, g, i, the blocks belonging to scan group number 2 are blocks d, f, h, the blocks belonging to scan group number 3 are blocks b, c, e
If the blocks belonging to the same scan group are connected by a scan chain using the result of the present embodiment after the processing of the scan group assignment processing unit 101, the wiring processing unit 226 performs the wiring processing shown in FIG. As a result, the wiring does not run along the diagonal line of the LSI as shown in FIG. 15B, and the wiring length of the scan chain is reduced.

As described above, the assignment of each block to a scan group is performed on the basis of the grouping information defining the scan group information to which each block belongs, as described above.

Next, the scan chain reassignment processing section 10
The process 2 will be described with reference to FIGS.

In the processing of the scan group assignment processing unit 101 described above, consideration is not given to flip-flops being arranged in gates beyond the block frame. However, in practice, the gate arrangement processing unit 2 is
In general, gates are arranged at 25 beyond the block frame. This situation is shown in FIG.

FIG. 10 is an enlarged view of blocks d, g, and i. In this embodiment, each block has a flip-flop having instances D1 to D3, G1 to G2, and I1 to I2. Shall be.

As shown in FIG. 10, when the flip-flop having the instance D2 greatly exceeds the frame of the block d, the flip-flop D2 has the scan group number 1 even though the block d belongs to the scan group number 2.
If the scan chain is included, the wiring length of the entire LSI becomes shorter.

That is, the wiring length is shorter when G1 → D2 → I1 is used instead of a broken line such as D1 → D2 → D3.

For this reason, the scan chain reassignment processing unit 1
02 is a process of re-evaluating the scan group number to which each flip-flop belongs so that the wiring length of the scan chain in the entire LSI is shortened from the gate arrangement result of the gate arrangement processing unit 225 performed after the allocation processing by the scan group allocation processing unit 101. Do.

The block frame table 900 and the replacement FF table 1000 used in the processing of the scan chain replacement processing unit 102 will be described with reference to FIGS.

The block frame table 900 shown in FIG. 11 is a table for storing a block frame 920, an extended block frame 930, and a scan group number 940 for each block (module) 910.

Here, the extended block frame 930 is information calculated by the block frame 920 and a reference value given by another means, and the scan chain extension is applied to flip-flops arranged beyond the extended block frame 930. Replacement is performed.

The reassignment target FF table 1000 shown in FIG. 10 includes the flip-flop instance name 1010 to which the scan chain is to be reassigned determined by the scan chain reassignment processing unit 102 and the scan group number 1020 to which the reassignment belongs. Is stored.

Next, the scan chain reassignment processing unit 102
Will be described. FIG. 13 is a flowchart illustrating the processing of the scan chain reassignment processing unit 102.

As shown in FIG. 13, the processing of the scan chain reassignment processing unit 102 first includes the module 410, the origin 430, the diagonal point 440, and the like from the scan group table 400 determined by the processing of the scan group assignment processing unit 101. The information of the scan group number 460 is stored in the module 910 of the block frame table 900, the origin 921, the diagonal point 922, and the scan group number 940 of the block frame 920, respectively (step 800).

Next, the origin 93 of the extended block frame 930 is set.
1. The diagonal point 932 is calculated (step 810). In this calculation method, the origin 931 of the extended block frame is a numerical value obtained by subtracting a separately specified reference value from the origin 921 of the block frame 920 for both x and y. However, when the subtracted numerical value becomes negative, it is set to “0”. Also, the diagonal points 932 of the extended block frame are the diagonal points 922 of the block frame 920 for both x and y.
Is a numerical value obtained by adding a separately specified reference value to However,
If the added numerical value exceeds the frame of the LSI, the maximum coordinate of the LSI frame is used. The contents of the block frame table 900 shown in FIG. 11 described above are values when the processing of step 810 is completed. The reference value specified separately is 50.

Next, information on one gate is read from the placement / wiring data 234 (step 820), and it is determined whether the gate is a flip-flop (step 830). A determination is made (step 840). For example, it is determined that the flip-flop of the instance D2 in FIG. 10 is a gate to which the block d belongs. FIG.
Although the instance name is set to D2 above 0, the module name can be easily determined from the instance name because the instance name of the gate usually has a module name such as d_d2 in the synthesis processing. .

Next, it is determined whether or not the extended block frame is protruded (step 850). This is because either the x or y coordinate of the flip-flop is smaller than the origin 931 of the block to which the flip-flop belongs, or the diagonal point 932
You can judge by the bigger. If so, it is determined in which block frame the flip-flop is located (step 860). This is because both the x and y coordinates of the flip-flop are larger than the block origin 921 and the diagonal point 9
A block smaller than 22 is searched in the block frame table 900.

Next, the instance name of the flip-flop and the scan group number of the block obtained in the processing of step 860 are stored in the FF table to be replaced (step 870), and the next gate information is processed (step 8).
80).

Finally, the scan chain connection information (not shown) in the arrangement / wiring data 234 is rewritten based on the information of the FF table to be replaced (step 89).
0). For example, in the case of the example of FIG. 10, the scan chain connection order of the scan group number 2 is D1 → D2 → D3 from D1 → D3, and the flip-flop of the instance D1 is connected to the last scan chain of the scan group number 1. The connection of the flip-flop of the instance D1 is made last because the wiring processing unit 226 in the subsequent stage performs the scan chain reconnection based on the gate position again.
It may be connected temporarily at the end.

Therefore, in a scan net design method for designing a scan net provided for detecting a fault in a logic circuit, a logic circuit for realizing an LSI is divided into a plurality of small logic blocks and connection between the blocks is taken into consideration. The arrangement of the blocks is performed, the number of flip-flops is calculated for each block, and based on the calculation result of the number of flip-flops and the inter-block distance, adjacent blocks are collectively divided into a plurality of groups. The order of connecting flip-flops of the block to which they belong is changed so that the wiring length is shortened, and the wiring is connected and wired by one scan net. Having scan nets connects flip-flops in adjacent blocks Because it is designed to, it is possible to shorten the wiring length of the scan net.

Further, since the design of the scan net is performed in units of blocks, not in units of individual flip-flops, the processing time can be reduced.

Further, flip-flops adjacent to the scan chain before the re-switching process can be included in one scan chain. Only flip-flops that greatly exceed the scan group frame due to the gate arrangement result, instead of all flip-flops, can be included. Since the scan group is to be reviewed, the wiring length of the scan chain can be easily reduced.

Each of the above-described processing units may be realized by a program that can be executed by a computer (computer), and the program at that time may be a floppy disk,
The storage medium such as a CD / ROM or a mask ROM is provided to general users. In this case, in addition to these processes, G
It may be provided to the user in combination with another program such as a UI program.

As an alternative means provided by the above-mentioned storage medium, it may be provided through a network such as the Internet for a fee.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0077]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

The scan net is designed so as to connect flip-flops in adjacent blocks, and the scan net is designed in units of blocks, not in units of individual flip-flops. And the processing time can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of a scan net design system for implementing a scan net design according to an embodiment of the present invention.

FIG. 2 is a diagram showing a scan group table 400 for explaining the flip-flop number calculation processing unit 100.

FIG. 3 is a diagram showing a scan group table 400 for explaining a scan group assignment processing unit 101;

FIG. 4 is a diagram showing a scan group table 400 for explaining a scan group assignment processing unit 101;

FIG. 5 is a diagram showing a scan group table 400 for explaining the scan group assignment processing unit 101.

FIG. 6 is a diagram for explaining processing of a flip-flop number calculation processing unit 100;

FIG. 7 is a diagram for explaining a scan group assignment processing unit 101;

FIG. 8 is a diagram for explaining a scan group assignment processing unit 101;

FIG. 9 is a flowchart for explaining processing of a scan group assignment processing unit 101;

FIG. 10 is a diagram for explaining processing of a scan chain reassignment processing unit 102;

11 is a diagram for explaining a block frame table 900. FIG.

FIG. 12 is a diagram for explaining a replacement FF table 1000;

FIG. 13 is a flowchart for explaining processing of a scan chain reassignment processing unit 102;

FIG. 14 is a diagram for explaining a configuration of a scan net design system that realizes a conventional scan net design.

FIG. 15 is a diagram for explaining a conventional scan net design process.

[Explanation of symbols]

100: flip-flop number calculation processing unit, 101: scan group assignment processing unit, 101A: grouping information acquisition processing unit, 102: scan chain reassignment processing unit, 200: terminal, 210: computer, 230: disk, 220: logic File input processing unit, 221 ... RTL
Floor plan processing unit, 222 ... Logic synthesis processing unit, 223
... Scannet insertion processing section, 224 detailed floor plan processing section, 225 gate placement processing section, 226 wiring processing section, 227 test pattern generation processing section, 231 R
TL logical data, 232... Block arrangement data, 233
... gate logic data, 234 ... placement / wiring data, 23
5: test data, 400: scan group table, 900: block frame table, 1000: FF table to be replaced.

Claims (4)

[Claims] 1. A scan net designing method for designing a scan net provided for detecting a failure of a logic circuit, comprising: dividing the logic circuit into a plurality of small logic blocks; A floor plan for arranging the blocks is calculated, the number of flip-flops is calculated for each block, and based on the calculation result of the number of flip-flops and the distance between the blocks, adjacent blocks are grouped together to form a plurality of groups. And the flip-flops of the blocks belonging to each group are connected and wired by one scan net with the connection order changed so that the wiring length is shortened, and the failure of the logic circuit is detected by the scan nets. A method for designing a scan net, comprising: generating a test pattern. 2. The scan net design method according to claim 1, wherein after dividing the plurality of groups, a distance between each flip-flop and a center of gravity of the group to which the flip-flop belongs is calculated, and the calculation result is obtained. A step of calculating a group closest to the flip-flop from the position where the flip-flop is located when the distance exceeds a reference distance, and including the flip-flop in the calculated group. 3. A scan net design system for designing a scan net provided for detecting a fault in a logic circuit, wherein a logic circuit to be realized is divided into a plurality of small logic blocks, and the small logic data is input to a file. Input processing means, floor plan processing means for arranging the blocks in consideration of the connection between the blocks, and conversion of each logical data input to the logical file input processing means to data of an element group for realizing the logical data Logic-synthesis processing means, flip-flop-number calculation means for calculating the number of flip-flops for each block from the element group data by the logic synthesis processing means, a calculation result of the flip-flop number calculation means, and a distance between the blocks. Group that divides adjacent blocks into multiple groups based on Allocation processing means, detailed floor plan processing means for correcting the physical arrangement of each block based on the data of the element group, element arrangement processing means for arranging the element group for each block, and the element The distance between each of the flip-flops arranged by the arrangement processing means and the center of gravity of the group to which the flip-flop belongs is calculated. If the calculation result exceeds the reference distance, the group closest to the arrangement position of the flip-flop is calculated. And a scan net connection reassigning unit that includes the flip-flop in the calculated group, and a flip-flop of a block belonging to each group, the connection order of which is reduced so that the wiring length is shortened by one.
A scan net design comprising: wiring processing means for connecting and wiring with scan nets of a book; and test pattern generation processing means for generating a test pattern for detecting a failure of a logic circuit for each scan net. system. 4. A scan net design system for designing a scan net provided for detecting a failure of a logic circuit, wherein a logic circuit to be realized is divided into a plurality of small logic blocks, and the small logic data is inputted to a file. Input processing means, floor plan processing means for arranging the blocks in consideration of the connection between the blocks, and conversion of each logical data input to the logical file input processing means to data of an element group for realizing the logical data Logic-synthesis processing means, and flip-flop number calculation means for calculating the number of flip-flops for each block from the element group data by the logic synthesis processing means; and for dividing each of the adjacent blocks into a plurality of groups. Acquisition of grouping information to acquire grouping information from scannet designer Processing means; group assignment processing means for dividing each block into a plurality of groups based on the calculation result of the flip-flop number calculation means and the grouping information; and physical assignment of each block based on the data of the element group. Detailed floor plan processing means for correcting the arrangement, element arrangement processing means for arranging the element group for each block, and each of the flip-flops arranged by the element arrangement processing means and the group to which the flip-flop belongs. The distance from the center of gravity is calculated, and when the calculation result exceeds the reference distance, the group closest to the flip-flop arrangement position is calculated, and the scan group including the flip-flop in the calculated group is calculated. Connection reconnection means and flip-flops of blocks belonging to each group are connected such that the wiring length is reduced. Swap the order and each one
A scan net design comprising: wiring processing means for connecting and wiring with scan nets of a book; and test pattern generation processing means for generating a test pattern for detecting a failure of a logic circuit for each scan net. system.