JPH11212942A5 - - Google Patents

Description

[0010]
[Means for solving the problem]
This invention combines the advantages of an inverted-graph topological interconnection network with a crossbar switch or a high-speed bus to propose a new interconnection network suitable for massively parallel processing computer systems, which has a wide communication bandwidth, short latency, and good scalability.
The primary goal of inverse graph topological interconnection networks is to reduce the number of routers and network channels. However, in terms of the number of nodes, a k-ary n-dimensional inverse graph topological interconnection network can connect more nodes than a k-ary n-cube interconnection network for the same k and n. In a 4-ary 2-dimensional inverse graph topological interconnection network as shown in Figure 6, the number of connected nodes is 32, double the 16 nodes in Figure 3. The lines, circles, and black dots in Figure 6 are the same as those in Figure 5. If NIG is the number of nodes that can be connected in an inverse graph topological interconnection network, then for two dimensions, NIG = 2N, for three dimensions, NIG = 3N, and for n dimensions, NIG = nN.

[0016]
Similarly, using a k-ary cubic new interconnection network as a supernode, multiple such supernodes can be combined into a larger cubic new interconnection network. The number of nodes can be further increased, and network latency only increases with the latency of three buses and associated interconnection circuits. Figure 10 shows a 64-node new interconnection network. Each small cube in the figure represents a supernode (e.g., SN030), and each supernode consists of an 8-ary cubic new interconnection network. If each supernode contains two processors, this interconnection network can connect 3 x 83 x 2 x 64 = 196,608 processors. If each processor can perform 500 million operations per second, the speed of such a massively parallel processing computer system would be 100 trillion operations per second.