JPH11225287A - Solid-state imaging device for change detection - Google Patents

Abstract

(57) Abstract: The present invention relates to a change detection solid-state imaging device that generates a different value signal indicating a change in a subject between successive frames, and accurately detects a change in the subject with a simple circuit configuration. It is another object of the present invention to associate the different value signal with the position of the pixel. SOLUTION: A plurality of light receiving units, a plurality of vertical read lines, a pixel output generated by the light receiving unit are held, and a pixel output for the immediately preceding frame already held and a pixel output for a newly generated current frame are held. And a plurality of comparing means for comparing the pixel output for the immediately preceding frame transferred to the vertical read line with the pixel output for the current frame to generate a different value signal. And a position for generating position information indicating the position of the light receiving unit in association with the different value signal based on the driving timing of at least one of the vertical transfer unit and the horizontal transfer unit. And information generating means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a change detection solid-state imaging device that generates a pixel output corresponding to incident light in a frame unit and generates an outlier signal indicating a change in a subject between successive frames.

[0002]

2. Description of the Related Art Conventionally, there has been known a change detection image processing apparatus for sequentially generating image signals by a solid-state imaging device and detecting a change in a subject between successive frames. FIG.
FIG. 7 is a diagram showing the configuration of this type of change detection image processing apparatus 100. In FIG. 17, a change detection image processing apparatus 100 includes a solid-state imaging device 101 and a solid-state imaging device 10.
1 converts an image signal (analog signal) generated into a digital signal into an analog signal, and a first image memory 103 and a second image memory 104 that store the digital signal output from the AD converter circuit 102.
And the first image memory 103 and the second image memory 1
And an image processing circuit 105 for detecting a change in the subject by comparing the digital signals stored in the image processing circuit 04.

In the change detection image processing apparatus 100 having such a configuration, first, an image signal (analog signal) for the first frame (the immediately preceding frame) is generated by the solid-state imaging device 101, and the image signal is subjected to AD conversion. Circuit 10
After being converted into a digital signal in step 2, the signal is stored in the first image memory 103. Next, the solid-state imaging device 101 generates an image signal (analog signal) for a second frame (current frame) subsequent to the first frame (previous frame), and the image signal is converted to an AD conversion circuit 10.
After being converted into a digital signal by the second image memory 2, the digital signal is stored in the second image memory 104.

The image processing circuit 105 compares the magnitude of the digital signal stored in the first image memory 103 with the magnitude of the digital signal stored in the second image memory 104 for each pixel. Pixels having a difference in signal magnitude equal to or greater than a predetermined value are detected. That is, the change detection image processing apparatus 100 generates a different value signal indicating a change in the subject based on a difference in luminance between two consecutive frames (an immediately preceding frame and a current frame) in pixel units.

[0005] The change of the subject corresponds to, for example, movement of an object in the subject.

[0006]

However, in such a change detection image processing apparatus 100, the solid-state imaging device 101 is used.
In addition, a peripheral circuit such as the AD conversion circuit 102 is required, and there has been a problem that the entire device becomes large and expensive.

Further, in the change detection image processing apparatus 100, since the solid-state imaging device 101 and the AD conversion circuit 102 are separately provided, an image signal (analog signal) output from the solid-state imaging device 101 is AD-converted. There is a possibility that the sampling timing in the circuit 102 may be slightly shifted for each frame. That is, the digital signal output from the AD conversion circuit 102 may not be accurately associated with each pixel in the solid-state imaging device 101.

Therefore, the image processing circuit 105 cannot accurately compare the difference in luminance of the same pixel due to the shift of the sampling timing in the AD conversion circuit 102, and detects a change in the subject. There is a problem that the accuracy and reliability at the time of performing the operation are impaired. In particular, in areas where the luminance difference between adjacent pixels is large, such as at the edge of an object, it is susceptible to sampling timing deviations, and a stationary object may be erroneously identified as a moving object. was there.

As a method for solving the above problems,
A memory for storing the image signals of the immediately preceding frame and the current frame is provided for each pixel, and a circuit for comparing the image signals stored in this memory is provided for each pixel, and the change of the subject is determined for each pixel. A solid-state imaging device that generates the indicated signal is conceivable. However, in such a method, the configuration of each pixel becomes complicated, and the aperture ratio of the solid-state imaging device decreases,
There is a problem that the resolution is lowered and it is not possible to respond to the increase in the number of pixels.

By the way, as a use of the change detecting image processing apparatus 100 for detecting a change of a subject, a security monitoring apparatus or the like can be considered. Such a monitoring device can easily determine the presence or absence of an intruder based on the change of the subject detected by the image processing circuit 105 in the change detection image processing device 100. However, when monitoring a wide area with one monitoring device, it is desirable that the position of the intruder can be identified.

However, the conventional change detection image processing apparatus 1
When the different value signal and the position of each pixel are associated with each other by 00, it is necessary to recalculate the position of each pixel based on the synchronization signal of the image signal generated by the solid-state imaging device 101, and the accuracy is low. There was also a defect. Therefore, according to the first to seventh aspects of the present invention, a change in a subject can be accurately detected with a simple circuit configuration, and a different value signal indicating the change in the subject can be reliably associated with a pixel position. It is an object to provide a change detection solid-state imaging device.

In particular, it is an object of the present invention to provide a change detection solid-state imaging device capable of easily identifying a position in a subject where a change has been detected. It is another object of the present invention to provide a change detection solid-state imaging device capable of simultaneously generating an outlier signal and an image signal. A further object of the present invention is to provide a change detection solid-state imaging device that enables an electronic shutter operation.

Another object of the present invention is to provide a solid-state imaging device for detecting a change for infrared rays.

[0014]

According to a first aspect of the present invention, there is provided a solid state imaging device for detecting a change, wherein a plurality of light receiving units are arranged in a matrix and generate a pixel output corresponding to incident light; A plurality of vertical read lines provided in association with each column, and a pixel output generated by each of the plurality of light receiving units are held, and the already held “pixel output for the immediately preceding frame” is stored in the light receiving unit. A vertical transfer unit that transfers the newly generated “pixel output for the current frame” to the vertical read line on a row-by-row basis, and is provided in association with each of the vertical read lines and transferred to the vertical read line. A plurality of comparing means for comparing the "pixel output for the immediately preceding frame" with the "pixel output for the current frame" to generate an outlier signal indicating a change in the subject between successive frames; The horizontal transfer means for horizontally transferring the different value signal generated by each of the above, based on the drive timing of at least one of the vertical transfer means and the horizontal transfer means, the position of the light receiving unit in association with the different value signal And position information generating means for generating the position information shown.

That is, according to the change detection solid-state imaging device having such a configuration, the "pixel output for the immediately preceding frame" and the "pixel output for the current frame" are sequentially transferred by the vertical transfer means. Since “pixel output for the immediately preceding frame” and “pixel output for the current frame” can be compared, a different value signal can be reliably generated with a simple circuit configuration.

Further, since the position information is generated based on the driving timing of the vertical transfer means and the horizontal transfer means, it is possible to reliably associate the different value signal with the position information. The solid-state imaging device for change detection according to claim 2 is the solid-state imaging device for change detection according to claim 1, wherein a pixel output changes between a previous frame and a current frame based on the outlier signal. And a change position information generation unit that generates change position information indicating a position of the light reception unit whose pixel output has changed from the position information generated by the position information generation unit.

That is, in the change detection solid-state imaging device having such a configuration, the change position information generating means generates change position information indicating the position of the light receiving section where the pixel output has changed between the immediately preceding frame and the current frame. Can be generated. A solid state imaging device for change detection according to a third aspect is the solid state imaging device for change detection according to the second aspect, based on the change position information generated by the change position information generating means, the immediately preceding frame in the current frame. The image processing apparatus further includes a center position information generating unit that generates center position information indicating a center position of a region where a change has occurred in the frame.

In the solid state imaging device for change detection having such a configuration, the center position of the area where the change has occurred can be detected by the center position information generating means. The solid-state imaging device for change detection according to claim 4 is the solid-state imaging device for change detection according to claim 2, based on the change position information generated by the change position information generating means, in a current frame. The image processing apparatus further includes a center-of-gravity position information generating unit that generates center-of-gravity position information indicating the position of the center of gravity of a region where a change has occurred in the frame.

In the solid state imaging device for change detection having such a configuration, the position of the center of gravity of the area where the change has occurred can be detected by the center of gravity position information generating means. According to a fifth aspect of the present invention, there is provided a solid-state imaging device for detecting a change.
In the change detection solid-state imaging device according to any one of the above, one of the pixel outputs of “pixel output for the immediately preceding frame” and “pixel output for the current frame” transferred to the vertical readout line is acquired. And an image generating means for horizontally transferring the pixel output to generate an image signal.

In the solid-state imaging device for change detection having such a configuration, the image signal of the immediately preceding frame or the current frame can be generated by the image generating means. The solid state imaging device for change detection according to claim 6 is the solid state imaging device for change detection according to any one of claims 1 to 5, wherein the solid state imaging device is provided corresponding to each row of the plurality of light receiving units. A plurality of switch means for intermittently switching between the light receiving unit and a predetermined reset voltage; and a point in time at which a pixel output is taken in from the light receiving unit by the vertical transfer unit by a predetermined time, and Electronic shutter control means for turning on the corresponding switch means only for a predetermined period.

In the solid state imaging device for change detection having such a configuration, an electronic shutter operation can be easily realized. Claim 7
The solid-state imaging device for change detection according to any one of claims 1 to 6, wherein the light-receiving unit is formed by reacting platinum, nickel, chromium, tungsten, or silicon with silicon. It is formed by a Schottky junction between the generated silicide and P-type silicon.

In the solid state imaging device for change detection having such a configuration, a monolithic type solid state imaging device for change detection for infrared rays can be easily configured.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic circuit diagram showing a schematic configuration of a change detection solid-state imaging device 10 according to a first embodiment. Note that the first embodiment corresponds to an embodiment corresponding to the first and fifth aspects of the present invention.

In FIG. 1, a solid state imaging device 1 for detecting a change is provided.
At 0, a plurality of pixels 1 are arranged in a matrix (here, arranged in a matrix of m rows and n columns).
These pixels 1 are connected to a vertical readout line 2 for each column, and to a vertical scanning circuit 6 via clock lines 3, 4, and 5 for each row.

The vertical scanning circuit 6 supplies driving pulses φTG1 to φTGm, φ via clock lines 3, 4, and 5.
Pixel 1 corresponding to RG1 to φRGm, φPX1 to PXm
To supply. The vertical read line 2 has a reset MOS
A switch QRSV, a constant current source 17 for supplying a bias current, a different value detection circuit 20, and a video signal generation circuit 30 are individually connected.

The gate of the reset MOS switch QRSV is connected to a node 16 on the side of a drive pulse generating circuit (not shown) via a clock line 16a, and is supplied with a drive pulse φRSV. The outlier detection circuit 20 is connected to nodes 8 and 9 on the side of a drive pulse generation circuit (not shown) via clock lines 8a and 9a.
A, φSB are supplied. The output of the outlier detection circuit 20 is
Connected to corresponding data input terminals Q1 to Qn of shift register 13 via selection signal line 14.

The load signal input terminal LD of the shift register 13 is connected to a node 11 on the side of a drive pulse generating circuit (not shown) via a clock line 11a.
A driving pulse φLD is supplied. The clock signal input terminal CK of the shift register 13 is connected to a node 15 on the side of a drive pulse generation circuit (not shown) via a clock line 15a, and is supplied with a clock pulse φCK. The output of the shift register 13 is
Is connected to the output terminal VO.

The video signal generation circuit 30 is connected to a node 32 on a drive pulse generation circuit (not shown) side via a clock line 32a, and is supplied with a drive pulse φV. The output of the video signal generation circuit 30 is connected to a horizontal read line 34 via a horizontal transfer MOS switch (n-channel type) QH. A horizontal scanning circuit 35 is connected to the gate of the horizontal transfer MOS switch QH via a horizontal selection signal line 33. Horizontal scanning circuit 35
Is the horizontal transfer M corresponding to the drive pulses φH1 to φHn.
Supply to OS switch QH.

The horizontal read line 34 is connected to an output buffer amplifier 37 and a reset MOS switch (n-channel type) QRSH. Output buffer amplifier 3
7 is connected to the output terminal Ao, and the reset MOS switch QRSH is connected to the clock line 36a.
Through a node 3 on the side of a drive pulse generation circuit (not shown)
6 is connected, and a drive pulse φRSH is supplied.

Incidentally, φCK and φLD supplied to the shift register 13 correspond to the horizontal address counter 200.
Are connected to the clock signal input terminal CK and the reset signal input terminal RESET. Horizontal address counter 20
0 outputs address signals ADRH0, ADRH1,..., ADRHk via a plurality of address output lines.
The drive pulse φRSV supplied to the gate of the reset MOS switch QRSV is connected to the clock signal input terminal CK of the vertical address counter 202. Reset signal input terminal RES of vertical address counter 202
ET is supplied with an EOS (end of scan) signal output from the vertical scanning circuit 6. The vertical address counter 202 outputs address signals ADRV0, ADRV1,..., ADRVi via a plurality of address output lines.
Is output.

FIG. 2 is a circuit diagram showing an internal configuration of the pixel 1 according to the first embodiment. Note that the pixel 1 shown in FIG.
This is a pixel arranged in the first row. In FIG. 2, the pixel 1 has a photodiode PD that generates and accumulates charges according to incident light. The anode of the photodiode PD is connected to one end of a charge storage capacitor CS1 and the gate of an amplification MOS transistor (N-channel type) QA via a charge transfer MOS switch QT. The gate of the amplification MOS transistor (N-channel type) QA is connected to a reset MOS switch (P-channel type) QR1.
Is connected to a wiring layer maintained at a constant reset potential VRD. The source of the amplification MOS transistor QA is connected to the vertical read line 2 via a vertical transfer MOS switch (P-channel type) QX.

The drive pulse φTG1 is supplied to the gate of the charge transfer MOS switch QT, and the drive pulse φRG is supplied to the gate of the reset MOS switch QR1.
1 is supplied, and the drive pulse φPX1 is supplied to the gate of the vertical transfer MOS switch QX. FIG. 3 is a circuit diagram showing an internal configuration of the outlier detection circuit 20.

In FIG. 3, the outlier detection circuit 20 has an outlier detector XA. The different value detector XA includes two voltage comparators AP1 and AP2 and a logical sum operator OR. Note that the vertical read line 2 is branched into a read line 2-1 and a read line 2-2 at a node n1.

The non-inverting input terminal of the voltage comparator AP1 is connected to the read line 2-1 and one terminal of the signal storage capacitor CL. The inverting input terminal of the voltage comparator AP1 is connected to the read line 2-2 and the signal. One terminal of the storage capacitor CS is connected. The non-inverting input terminal of the voltage comparator AP2 is connected to the read line 2-2 and the signal storage capacitor CS.
Of the voltage comparator AP2 is connected to the read line 2-1 and the signal storage capacitor CL.
Are connected to each other.

These two voltage comparators AP1, AP2
Is connected to the input terminal of the OR operator OR, and the output of the OR operator OR is connected to the selection signal line 14 as the output of the different value detection circuit 20. Note that the read line 2
−1 and 2-2 include a switching MOS transistor Q
L and QS, and the driving pulses φSA and φS are connected to the gates of the switching MOS transistors QL and QS, respectively.
B is supplied.

FIG. 4 is a circuit diagram showing the internal configuration of the video signal generation circuit 30. In FIG. 4, the video signal generation circuit 30 includes a hold capacitor CV and a switching MOS transistor (n-channel type) QV for switching the sample and hold.

One end of the hole capacitance CV is connected to the vertical read line 2
, And the other end of the Hall capacitance CV is a switch MOS.
It is connected to the transistor QV and the horizontal transfer MOS switch QH. The switching MOS transistor QV
Are supplied with a driving pulse φV.

By the way, regarding the correspondence between the first and fifth embodiments of the present invention and the first embodiment, the light receiving section corresponds to the photodiode PD, and the vertical read line corresponds to the vertical read line 2. Vertical transfer means include a vertical scanning circuit 6, an amplification MOS transistor QA, and a charge transfer MO.
The S switch QT, the reset MOS switch QR1, the vertical transfer MOS switch QX, the comparison means correspond to the different value detection circuit 20, the horizontal transfer means corresponds to the shift register 13, and the position information generation means corresponds to the horizontal address. The image generating means corresponds to the video signal generating circuit 30 and the horizontal readout line 3 corresponding to the counter 200 and the vertical address counter 202.
4, corresponding to the horizontal scanning circuit 35.

FIG. 5 is a timing chart for explaining the operation of generating a different value signal in the first embodiment. FIG. 5 shows one of the N-th frame (current frame).
The operation relating to pixel 1 in the first and second columns in the second and third rows will be described. FIG. 6 is a timing chart illustrating an operation of outputting an address signal in the first embodiment.

FIG. 6 shows an operation related to the pixel 1 in the first to third columns in the first and second rows in the N-th frame. Hereinafter, the operation of the first embodiment will be described with reference to FIGS. In the present embodiment, the N-th
The following description focuses on the operation related to each pixel 1 in the first row in the frame.

As shown in FIG. 5, the period t1 of the N-th frame
Immediately before reaching 0 (the end of the period t26 of the (N-1) th frame)
, Drive pulses φTG1, φPX1, φRG1,
TG2, φPX2, φRG2, φRSV, φSA, φS
B, φLD, φV, φH1, φH2, φRSH and the clock pulse φCK are kept at low level. Here, since the drive pulses φTG1 and φTG2 are at low level, the charge transfer MOS switch QT of each pixel 1 is turned off, and since the drive pulses φRG1 and φRG2 are at low level, the reset MOS switch QR1 of each pixel 1 is turned off. ing.

Therefore, the amplification MOS transistor Q
The gate of A is in a floating state,
The electric charge (hereinafter, referred to as “first signal electric charge”) transferred to the gate of each amplifying MOS transistor QA through the electric charge transfer MOS switch QT during the period t14 of the −1 frame is the parasitic capacitance (CS1). Even after the charge transfer MOS switch QT is turned off due to the effect, the amplification MO
It is held at the gate of S transistor QA.

The amplification MOS transistor QA is
While the charge held in the gate remains (until reset), the vertical transfer MOS switch QX
Is turned on, an electric signal corresponding to the gate voltage is output by the source follower operation. The vertical transfer MOS switch QX is turned off because the drive pulses φPX1 and φPX2 are at a low level, and each pixel 1 is separated from the vertical readout line 2. The reset MOS switch QRSV is turned off because the drive pulse φRSV is at a low level.

Further, since the driving pulses φSA and φSB are at a low level, the switching MOS
The transistors QL and QS are turned off, and no electric signal on the vertical read line 2 is supplied to the signal storage capacitors CL and CS. Further, since the drive pulse φLD is at a low level, no signal is input to the register of the shift register 13 corresponding to each bit.

After the charge transfer MOS switch QT is turned off in the (N-1) th frame (immediately before the frame), each of the photodiodes PD has a new charge (hereinafter, referred to as "second charge") corresponding to the incident light. Signal charge).
Stored. In the period t10, the driving pulse φRSV
Is inverted from the low level to the high level, the reset MOS switch QRSV is turned on, and the reset operation of the electric signal remaining on the vertical read line 2 is performed.

In the period t11, the driving pulse φPX1
Is inverted to the high level, and the vertical transfer MOS switch QX of each pixel 1 in the first row is turned on, and the amplification MO switch is turned on.
The source of S transistor QA is connected to vertical read line 2. Since the drive pulse φPX2 is at the low level, the vertical transfer MOS switch QX of each pixel 1 in the second row is off, and the source of the amplification MOS transistor QA of each pixel 1 in the second row is Not connected to vertical read line 2.

That is, in the period t11, the amplification MOS transistor QA of each pixel 1 in the first row is selected. Also, the reset MOS switch QRS
Since V is off, the amplifying MOS transistor Q of each pixel 1 in the first row selected in the period t11
In A, the current (drain current) flowing between the source and the drain due to the source follower operation is changed to IB (constant current source 1).
7).

At this time, the amplification MO of each pixel 1 in the first row is
As described above, the gate of the S transistor QA has the first
Therefore, an electric signal (hereinafter, referred to as “first output signal”) corresponding to the first signal charge is output to the vertical read line 2. Further, a period t11
, The drive pulse φRSV is inverted to low level,
The drive pulse φSA is inverted to a high level. for that reason,
The reset MOS switch QRSV is turned off, and the switching MOS transistor QL in the different value detection circuit 20 is turned on. At this time, the switching MOS transistor QS in the different value detection circuit 20 remains off.

Therefore, the first output signal is charged into the signal storage capacitor CL via the switching MOS transistor QL. Then, at the start of the period t12 (at the end of the period t11), the driving pulse φSA is inverted to a low level, and the driving pulse φRG1 is inverted to a high level. Here, since the drive pulse φSA becomes low level, the switching MOS transistor QL is turned off, and the signal storage capacitor CL is set in a floating state, and holds the above-mentioned first output signal as it is.

As described above, the first output signal held in the signal storage capacitor CL is, as described above, the current of the amplifying MOS transistor QA when the current flowing between the source and the drain becomes IB due to the source follower operation. Output signal. Assuming that the first output signal is VSS1, the value of VSS1 is a value represented by the following equation (1).

VSS1 = VRD + VS1-VT (1) Here, VRD is a reset MOS in the (N-1) th frame.
The power supply voltage supplied when the switch QR1 is turned on, VS1 is a change in the gate potential of the amplification MOS transistor QA according to the first signal charge in the (N-1) th frame, and VT is an amplification MOS transistor. This is the voltage between the gate and source when the drain current of QA is IB. Note that the value of VS1 is obtained by “first signal charge / gate capacitance according to incident light”.

That is, in the period t11, since the driving pulse φSA is at the high level, the switching MOS transistor QL is turned on, and the signal storage capacitor CL is turned on.
Is the potential VSS1 represented by the equation (1). At the end of the period t11 (at the start of the period t12)
By the time the drive pulse φSA is inverted to low level and the switching MOS transistor QL is turned off,
The potential VSS1 is charged in the signal storage capacitor CL and is maintained as it is.

In period t12, drive pulse φRG1
Becomes high level, the reset MOS switch QR1 of each pixel 1 in the first row is turned on, and the power supply voltage VR
D is supplied as a read level to the gate of the amplification MOS transistor QA of each pixel 1 in the first row. That is, when the reset MOS switch QR1 is turned on, the first signal charge is reset (discharged) from the gate of the amplification MOS transistor QA, and the gate of the amplification MOS transistor QA is connected to the power supply voltage VRD.
Bias to the read level.

At the start of period t13 (at the end of period t12), drive pulse φRG1 is inverted to a low level, and drive pulse φV is inverted to a high level. here,
Since the driving pulse φRG1 is inverted to a low level, the first
The reset MOS switch QR1 of each pixel 1 in the row is turned off again, and the gate of the amplification MOS transistor QA of each pixel 1 in the first row is in a floating state.
Due to the effect of the parasitic capacitance, the gate is kept in a state of being biased to the read level.

On the other hand, since the drive pulse φV is inverted to the high level, the switching MO in the video signal generation circuit 30 is switched.
The S transistor QV is turned on, and the electrode CVB of the hold capacitor CV is connected to the power supply. Therefore, the potential difference between both ends of the hold capacitor CV (between the electrode CVA and the electrode CVB) is equal to the dark output signal VD (details will be described later).
Note that the dark output signal VD is charged to the hold capacitor CV before the drive pulse φV is inverted to a low level and the switching MOS transistor QV is turned off.

At the start of period t14 (at the end of period t13), drive pulse φV is again inverted to a low level, and drive pulse φTG1 is inverted to a high level. Here, since the drive pulse φTG1 is inverted to a high level,
The charge transfer MOS switch QT of each pixel 1 in the first row is turned on, and the photodiode P of each pixel 1 in the first row is turned on.
D corresponding to the incident light generated and accumulated in D (second
Is transferred directly to the gate of the amplification MOS transistor QA of each pixel 1 in the first row. Note that such a second signal charge is a charge corresponding to incident light in the Nth frame.

As described above, the amplification MOS transistor QA
When the charge (second signal charge) corresponding to the incident light in the N-th frame is transferred to the gate of the Nth frame, the gate potential of each amplifying MOS transistor QA changes by the amount of the transferred charge. The amplification MOS transistor QA of each pixel 1 in the first row performs a source follower operation, and the amplification MOS transistor QA
The source potential of the transistor QA changes by the change in the gate potential.

At this time, the amplifying MOS transistor QA of each pixel 1 in the first row performing the source follower operation responds to the second signal charge via the already-on vertical transfer MOS switch QX. Electrical signal (hereinafter referred to as “second
Output signal. " ) Is output to the vertical read line 2. At the start of period t15 (at the end of period t14), drive pulse φTG1 is inverted to a low level, and drive pulse φSB and drive pulse φLD are inverted to a high level.

Here, since the driving pulse φTG1 is inverted to the low level, the charge transfer MO of each pixel 1 in the first row is changed.
The S switch QT is turned off, and the charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD of each pixel 1 in the first row is transferred to the gate of the amplification MOS transistor QA. The gate of the amplifying MOS transistor QA is again brought into the floating state, but the potential of the gate changes by the transferred charge (second signal charge) due to the effect of the parasitic capacitance (CS1). That state is maintained.

By the way, the charge transferred to the gate of the amplification MOS transistor QA as the second signal charge for the Nth frame is the next (N + 1) th frame (not shown).
Is held until the gate is reset (until the reset MOS switch QR1 is turned on). That is, the second signal charge in the Nth frame is (N + 1) th.
It is used as the first signal charge in the frame (charge generated and accumulated in the immediately preceding frame).

As described above, the charge transfer MOS switch QT
Is turned off, the second signal charge is held at the gate of the MOS transistor for amplification QA.
From the transistor QA, an electric signal (second output signal) corresponding to the charge (second signal charge) accumulated in the gate by the source follower operation until the gate is reset is output.

Further, since the driving pulse φSB is inverted to the high level, the switching MOS transistor QS is turned on, and the amplification MOS transistor QA of each pixel 1 in the first row in which the second signal charge is stored. Output second
The output signal of the vertical transfer MOS already turned on
The signal storage capacitor CS is charged via the switch QX and the vertical read line 2.

That is, in the period t15, the current flowing between the source and the drain due to the source follower operation becomes I
When the potential becomes B, the potential of the source of the amplifying MOS transistor QA (corresponding to a second output signal; denoted as VSS2) VSS2 becomes a value represented by the following equation (2). VSS2 = VRD + VS2-VT (2) Here, VS2 is an amplifying MOS corresponding to the second signal charge.
This is a change in the gate potential of the transistor QA. In addition,
The value of VS2 is expressed as “second signal charge / gate capacitance according to incident light”, similarly to VS1 described above.

That is, in the period t15, the driving pulse φ
Since SB is at the high level, the switching MOS transistor QS is turned on, and the potential at both ends of the signal storage capacitor CS becomes the potential VSS2 represented by Expression (2).
At the end of the period t15 (at the start of the period t16),
The drive pulse φSB is inverted to low level and the switch M
By the time the OS transistor QS is turned off, the potential V
SS2 is charged in the signal storage capacitor CS.

As described above, the signal storage capacitor CS holds the second output signal represented by the equation (2), and the signal storage capacitor CL has the equation (1) as described above.
Is held. Then, the second output signal and the first output signal are supplied to the outlier detector XA. Then, from the outlier detector XA,
Only when the difference between the first output signal (analog signal) and the second output signal (analog signal) is equal to or greater than a predetermined value, is the high level (high level of logic level) or low level (low level of logic level). A different value signal (digital signal) having the same level is output (the details will be described later).

Since the drive pulse φLD is inverted to the high level, a different value signal (digital signal) is stored in the register corresponding to each bit of the shift register 13 via the data input terminals Q1 to Qn. At the start of the period t16 (at the end of the period t15), the driving pulse φLD and the driving pulse φSB are again inverted to the low level. here,
Since the drive pulse φSB is inverted to a low level, the switching MOS transistor QS is turned off.

In the period t16, the driving pulse φ
H1 to φHn are sequentially activated at regular intervals, and the horizontal transfer MOS switch QH is activated at a predetermined timing.
Turn on alternately. When the horizontal transfer MOS switch QH is turned on in this manner, the video signal generated by the video signal generation circuit 30 is transferred to the horizontal read line 34.

Further, in a period t16, the drive pulse φRSH for reset rises to a high level at a predetermined timing. Then, the driving pulse φRSH
Becomes high level, the reset MOS switch QRSH is turned on, and the charges remaining on the horizontal read line 34 are reset (discharged). Before the period t20 of the period t16, the driving pulse φPX1 is inverted to a low level, so that the vertical transfer MOS switch QX of each pixel 1 in the first row is turned off, and each pixel 1 in the first row is turned off.
Are separated from the vertical read line 2.

At the end of period t16 (period t20)
), The drive pulse φRSV is inverted to the high level, the reset MOS switch QRSV is turned on, and the reset operation of the vertical read line 2 is started. Note that when the clock pulse φCK is input to the shift register 13 during the period t16, the different value signal held in the register corresponding to each bit is output to the horizontal read line 1
2 sequentially output from the output terminal VO.

In the periods t20 to t26, the same operation as the readout operation of the pixels 1 in the first row in the periods t10 to t16 is repeatedly performed on each pixel 1 in the second row. Different value signals in the Nth frame are sequentially output from the output terminal VO from each pixel 1 in the second row. As described above, in the present embodiment, two consecutive
An analog signal (electric signal representing luminance) corresponding to the incident light obtained between two frames (the (N-1) th frame and the Nth frame) is compared, and when the difference is larger than a predetermined value, it is determined in advance. A signal indicating the level (a different value signal) is output.

Therefore, in this embodiment, two consecutive
Pixels in which the magnitude of the difference between the electric signals representing the luminance differs between the two frames can be detected. Next, a specific operation will be described focusing on the outlier detection circuit 20 only. As described above, in FIG. 5, in the period t10 of the N-th frame, the vertical transfer MOS switch QX is turned off because the drive pulse φPX1 is at the low level, and each pixel 1 is separated from the vertical readout line 2. . In this period t10, as described above, the reset M
The OS switch QRSV is turned on, and the reset operation of the electric signal remaining on the vertical read line 2 is performed.

In the next period t11, an electric signal corresponding to the electric charge held in the gate of the amplification MOS transistor QA is output to the vertical read line 2, and the first output signal VSS
It is held as 1 in the signal storage capacitor CL. That is, the reading of the electric signal for the (N-1) th frame is performed. Further, in the period t12, the electric signal accumulated in the gate of the amplification MOS transistor QA is reset as described above.

Further, in the period t13, reading of the dark output signal (charging of the hold capacitance CV) is performed. Then, in the period t14, the charge newly generated and stored in the photodiode PD is transferred to the gate of the amplification MOS transistor QA, and an electric signal corresponding to the charge is output to the vertical read line 2. That is, in the period t14,
The charge transfer for the Nth frame is performed.

The electric signal output to the vertical read line 2 as described above passes through the switching MOS transistor QS turned on during the period t15, and the second output signal VS
It is stored in the signal storage capacitor CS as S2. That is, in the period t15, the reading of the electric signal for the N-th frame is performed. Then, in a period t16, the output of the different value signal to the horizontal read line 12 and the output of the video signal to the horizontal read line 34 are performed.

By the time t15, the first output signal VSS has already been applied to the signal storage capacitor CL.
1 is stored and held, and the first output signal VSS1 is supplied to the non-inverting input terminal of the voltage comparator AP1 and the inverting input terminal of the voltage comparator AP2.

In the period t15, the second output signal VSS2 is newly stored in the signal storage capacitor CS.
When held, the second output signal VSS2 is supplied to the non-inverting input terminal of the voltage comparator AP2 and the inverting input terminal of the voltage comparator AP1. In the different value detection circuit 20, the voltage comparator AP1 and the voltage comparator AP2 separately output the first output signal VSS1 and the second output signal VSS.
2 will be compared.

Here, the first output signal VSS1 is represented by the above equation (1), and the second output signal VSS2 is represented by the above equation (2). Therefore, the voltage comparator AP1
The voltage comparator AP2 compares the magnitude of the first output signal VSS1 with the magnitude of the second output signal VSS2 as shown in the following equation (3). VSS1−VSS2 = (VRD + VS1−VT) − (VRD + VS2−VT) = VS1−VS2 (3) In this way, comparing the magnitudes of the first output signal VSS1 and the second output signal VSS2 is as follows. Specific pixel 1
Of the incident light in the (N-1) th frame at (VS1)
To the luminance (VS2) of the incident light in the Nth frame, that is, to detect a luminance change between two consecutive frames.

By the way, in each of the voltage comparator AP1 and the voltage comparator AP2 which compare the value shown in the above equation (3), the signal input to the non-inverting input terminal is input to the inverting input terminal. If the signal is larger than the signal, the power supply voltage level (high level) is output. If the signal input to the non-inverting input terminal is equal to or smaller than the signal input to the inverting input terminal, the ground level (low) is output. Level).

That is, the first output signal VSS1 is changed to the second output signal VSS1.
Is larger than the output signal VSS2, the output of the voltage comparator AP1 becomes the power supply voltage level (high level),
Conversely, the second output signal VSS2 becomes the first output signal VSS
If it is larger than 1, the output of the voltage comparator AP2 becomes the power supply voltage level (high level).

When the first output signal VSS1 is equal to the second output signal VSS2, the voltage comparator AP
The outputs of AP1 and AP2 are both at the ground level (low level). The voltage comparators AP1, AP2 thus obtained
Are supplied to a logical sum operation unit OR to perform a logical sum operation. Note that, in the present embodiment, only when the magnitude of the first output signal VSS1 and the magnitude of the second output signal VSS2 are different (when either one is larger or smaller than the other), the OR operation unit OR The output (the output of the different value detector XA) is at the high level (the high level of the logic level).

When the magnitude of the first output signal VSS1 is equal to the magnitude of the second output signal VSS2,
The output of the OR operator OR (the output of the different value detector XA) becomes low level (low level of the logic level). It is known that the value of VT (gate-source voltage) in the above equations (1) and (2) varies for each amplifying MOS transistor QA and causes so-called fixed pattern noise. . However, as shown in the above equation (3), since the different value signal is not affected by the VT value, the different value detection is performed without being affected by the fixed pattern noise (the first output signal VSS1). Magnitude and second output signal VSS
2 is compared).

It is known that the first output signal VSS1 and the second output signal VSS2 generally include a random noise component in addition to a fixed pattern noise component. Therefore, when detecting an outlier, an erroneous signal may be generated due to these random noise components. However, in the present embodiment, the voltage comparator AP
1, when the difference between the signal voltage input to the non-inverting input terminal of AP2 and the signal voltage input to the inverting input terminal exceeds a certain threshold voltage, the outputs of the voltage comparators AP1 and AP2 are inverted. By doing so, it is possible to prevent the generation of an erroneous signal due to a random noise component.

FIG. 7 is a characteristic diagram showing an example of the input / output characteristics of the voltage comparators AP1 and AP2 constituting the outlier detector XA of the present embodiment. In FIG. 7, the voltage ΔH is a threshold voltage, and is set to be sufficiently higher than the magnitude of a normal random noise component. V1 indicates an input voltage value input to the non-inverting input terminals of the voltage comparators AP1 and AP2, V2 indicates an input voltage value input to the inverting input terminals, and Vout indicates an output voltage value.

Here, the value of “V1−V2” is the threshold voltage Δ
When it becomes larger than H, the output Vout is inverted from low level to high level. Therefore, the outlier detector X
By setting the voltage comparators AP1 and AP2 constituting A to have the characteristics shown in FIG. 7 (especially, the threshold voltage ΔH is set sufficiently large compared to the magnitude of the random noise component).
The output of the voltage comparator AP1 is the first output signal voltage VSS
1 and the second output signal voltage VSS2 is equal to the threshold voltage ΔH
Only when it is larger than (VSS1−VSS2> ΔH), it becomes the power supply voltage level (high level).

Similarly, the output of the voltage comparator AP2 is output when the difference between the second output signal voltage VSS2 and the first output signal voltage VSS1 is larger than the threshold voltage ΔH (VS
Only when (S2−VSS1> ΔH) is the power supply voltage level (high level). That is, the magnitude of the difference between the first output signal VSS1 and the second output signal VSS2 (absolute value | VS
Only when S1−VSS2 |) is greater than the threshold voltage ΔH, one of the outputs of the voltage comparators AP1 and AP2 becomes the power supply voltage level (high level).

Therefore, in this embodiment, outlier detection can be performed without generating an erroneous signal due to random noise components. Next, the specific operation of the video signal generation circuit 30 will be described focusing on the video signal generation circuit 30 alone. Note that, in the following, in particular, the period t10 to the period t16 of the N-th frame
(Operation of each pixel 1 in the first row) will be described.

First, immediately before the period t10 of the Nth frame (the end of the period t26 of the (N-1) th frame),
Drive pulse φPX1, PX2, φTG1, φRG1, φ
V is kept at a low level. Note that since the drive pulse φPX2 is kept at the low level until the period t21, each pixel 1 in the second row is separated from the vertical read line 2 from the period t10 to the period t16 of the Nth frame.

Immediately before the period t10, since the driving pulse φTG1 is at a low level, the charge transfer MOS
The transistor QT is turned off, and since the drive pulse φRG1 is at a low level, the reset MOS transistor QR1
Is also off. At this time, the gate of the amplifying MOS transistor QA is in a floating state, but due to the effect of the parasitic capacitance (CS1), the charge already transferred to the gate (the charge corresponding to the incident light in the immediately preceding frame;
The first signal charge) is held in a biased state. In the photodiode PD, charges (second signal charges) corresponding to the incident light in the current frame are generated and accumulated.

Thereafter, during the period t11, the driving pulse φPX1 is inverted from the low level to the high level.
Already in the (N-1) th frame, the amplifying MOS transistor QA
An electric signal corresponding to the electric charge (first signal electric charge) transferred to and held by the gate is output to the vertical read line 2 by the source follower operation. At the start of period t12 (at the end of period t11), drive pulse φ
Since RG1 is inverted to the high level, the reset MOS
The switch QR1 is turned on, and the charge stored in the gate of the amplification MOS transistor QA is reset (discharged).

At the start of period t13 (at the end of period t12), drive pulse φRG1 is inverted to a low level, so that switching MOS transistor QL is turned off and signal storage capacitor CL enters a floating state. However, due to the effect of the parasitic capacitance (CS1),
The bias state at the time of reset is maintained. At this time, the amplifying MOS transistor QA performs a source follower operation, so that one electrode CVA of the hold capacitor CV is supplied with an electric signal (hereinafter, referred to as a bias signal) according to the bias state.
It is described as “dark output signal VD”. ) Is supplied.

Further, at the start of period t13 (period t12
), The drive pulse φV is inverted to the high level, the switching MOS transistor QV is turned on, and the other electrode CVB of the hold capacitor CV is grounded. With these operations, the potential difference between both ends of the hold capacitor CV becomes equal to the dark output signal VD as described above.

Then, at the start of the period t14 (the period t13
), The dark output signal VD is charged to the hold capacitor CV by the time the drive pulse φV is inverted to the low level and the switching MOS transistor QV is turned off. In addition, at the start of the period t14 (at the end of the period t13), the drive pulse φTG1 becomes high level, so that the charge transfer MOS switch QT is turned on, and the incident light generated and accumulated in the photodiode PD by this time. The charge (second signal charge) corresponding to the light is newly transferred directly to the gate of the amplification MOS transistor QA.

At this time, the amplifying MOS transistor QA performs a source follower operation, and the second MOS transistor QA responds to the second signal charge.
Is output to the vertical readout line 2. And
At the start of period t15 (at the end of period t14),
Since the drive pulse φTG1 is inverted to the low level, the charge transfer MOS switch QT is turned off, and the MOS transistor for amplifying the charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD. QA
Transfer to the gate ends.

At this time, the gate of the amplifying MOS transistor QA is again in a floating state, but the voltage of the gate is changed by the transferred electric charge (the electric charge for the current frame = the second signal) due to the effect of the parasitic capacitance (CS1). Charge), and the state is maintained. Further, an electric signal (second output signal; hereinafter, referred to as “electric signal VB”) corresponding to the electric charge (second signal electric charge) stored in the gate of the amplification MOS transistor QA is a hold capacitance CV. Is output to one of the electrodes CVA.

The electric signal VB is equal to the hold capacitance C.
Immediately before the voltage is output to one electrode CVA of V, both ends of the hold capacitor CV are connected to the dark output signal V
D is stored. Therefore, when the electric signal VB is output to one electrode CVA of the hold capacitor CV, the potential of the other electrode CVB of the hold capacitor CV becomes “VB−VD”.
Becomes

Here, the electric signal VB is the dark output signal VD
And a signal corresponding to a change in the gate potential of the amplifying MOS transistor QA due to the electric charge (second signal electric charge) obtained in the Nth frame (hereinafter, referred to as “optical signal VS”).
Is considered to be the sum of That is, VB = VD + VS (4)

Therefore, in the period t15, the output of the video signal generation circuit 30 becomes VB−VD = VD + VS−VD = VS (5) because the amplifying MOS transistor QA performs the source follower operation, and the optical signal VS Only will be obtained. By the way, the dark output signal VD includes the variation in the voltage between the gate and the source of the amplification MOS transistor QA which causes fixed pattern noise and the amplification MO which causes random noise.
It is known that reset noise immediately after resetting the gate of the S transistor QA is included. But,
As shown in the above equation (5), the output of the video signal generation circuit 30 is not affected by the dark output signal VD.

Therefore, in this embodiment, it is possible to obtain a video signal from which fixed pattern noise and random noise have been removed. As described above, since the different value signal is output from the different value detection circuit 20 in the period t15, in this embodiment, the generation of the different value signal and the generation of the video signal can be performed simultaneously.

Next, the operation of outputting an address signal will be described with reference to FIG. First, immediately before reaching the period t10 of the N-th frame (the end of the period t26 of the (N-1) th frame), an EOS (end of scan) signal φEOS
Is inverted to a low level, the vertical address counter 2
02 holds the output levels of the addresses ADRV0 to ADRVi at a low level.

In period t10, drive pulse φRSV
Is inverted to a high level, the vertical address counter 2
02 outputs an address signal indicating "1" in binary notation with only the output level of the address ADRV0 as a high level. In addition, the vertical address counter 202 operates in the period t2.
At 0, when the drive pulse φRSV is inverted to the high level, only the output level of the address ADRV1 is set to the high level, and “10” in binary notation (“2” in decimal notation)
Is output.

When the drive pulse φRSV is inverted to the high level during the period 30 (not shown), the vertical address counter 202 outputs the addresses ADRV0 and ADRV1.
"11" in binary notation with the output level of
An address signal indicating ("3" in decimal notation) is output. That is, the vertical address counter 202 is reset by the EOS signal φEOS of the vertical scanning circuit 6,
Each time the drive pulse φRSV is supplied, the address signal counted up (incremented) by 1
Output via DRV0 to ADRVi.

In the period t15, the driving pulse φ
When the LD is inverted to the high level, the horizontal address counter 200 holds the output levels of the addresses ADRH0 to ADRHk at the low level. In the period t16, when the clock pulse φCK is inverted to the high level for the first time, the horizontal address counter 200 sets the address ADRH
Only the output level of 0 is set to high level, and an address signal indicating “1” in binary notation is output. Further, when the clock pulse φCK is again inverted to the high level in the period t16, the vertical address counter 202 sets only the output level of the address ADRH1 to the high level, and sets “10” in binary notation (“2” in decimal notation). ) Is output.

Further, the horizontal address counter 200
When the clock pulse φCK is again inverted to the high level, the output level of the addresses ADRH0 and ADRH1 is set to the high level, and an address signal indicating “11” in binary notation (“3” in decimal notation) is output. That is, the horizontal address counter 200 is reset by the drive pulse φLD, and outputs an address signal counted up (incremented) by one each time the clock pulse φCK is supplied via the addresses ADRH0 to ADRHk.

As described above, according to the present embodiment, the different value detection circuit 20 can easily generate the different value signal indicating the difference in luminance between two consecutive frames. In addition, since the outlier signal generated by the change detection solid-state imaging device 10 is binarized when it is transferred to the horizontal read line 12, it is less susceptible to noise than analog signals, and The output can be performed at high speed by the register 13.

Further, in the change detection solid-state imaging device 10, the different value signal and the video signal are associated with each other on a pixel-by-pixel basis.
At the same time, it is possible to generate an address signal indicating the position of the corresponding pixel. Therefore, the change detection solid-state imaging device 10 can reliably establish an interface with an information processing device such as a microcomputer, so that various information processing systems can be easily constructed.

When the change detection solid-state imaging device 10 is used in a monitoring system or the like, the following uses are conceivable. For example, in a monitoring system in which a display device (such as a CRT) and a recording device are connected to the change detection solid-state imaging device 10, a moving object based on an outlier signal is always displayed on the display device, and a video signal is transmitted to the recording device. Can be recorded.

That is, according to such a monitoring system, the observer can monitor only the movement of the subject,
By reproducing an image based on a video signal as needed, it is possible to perform monitoring efficiently. Also,
An analog image based on a video signal generated by the change detection solid-state imaging device 10 and an analog image based on a different value signal.
A monitoring system that displays at least one of the value image and the value image is also conceivable. That is, according to such a surveillance system, a surveillant can appropriately add an analog image and a two-
Optimal monitoring can be performed using both or one of the value images.

The timing of switching between an analog image and a binary image (for example, display on a monitor screen) is as follows.
It may be performed automatically at predetermined time intervals, or the state of change of the different value signal is detected, and an analog image is displayed when the change amount is equal to or more than a predetermined value, and a binary image is displayed when the change amount is equal to or less than a predetermined value. You may. In a monitoring system that monitors a wide range with a camera including the change detection solid-state imaging device 10, it is easy to identify where an abnormality is detected in the monitoring area by associating an outlier signal with an address signal. be able to. Therefore, for example, when there are a plurality of entrances, it is possible to detect only an abnormality in a specific area, such as detecting an intruder from a specific entrance.

Further, in this embodiment, the vertical transfer MO
The connection / separation between the pixel 1 and the vertical readout line 2 is performed by the S switch QX. For such a connection / separation method, for example, one of the capacitors is connected to the gate of the amplification MOS transistor QA of the pixel 1. Any method may be used, such as connecting the electrodes and controlling the voltage applied to the other electrode.

(Second Embodiment) FIG. 8 is a diagram for explaining the operation of the second embodiment. Note that the second embodiment corresponds to an embodiment corresponding to the invention described in claims 2 and 3. A feature of the configuration of the second embodiment is that a circuit configuration shown in FIG. 8 is added to each of the horizontal address counter 200 and the vertical address counter 202 in FIG. Therefore, here, the second embodiment will be described with reference to FIG. 8 while avoiding overlap with the first embodiment.

Referring to FIG. 8, address signals ADR0, ADR0, A
, ADRn are address signals ADRH0, ADR0 output from the horizontal address counter 200 shown in FIG.
DRH1,..., ADRHk or the address signals ADRV0, ADR output from the vertical address counter 202
V1,..., ADRVi. The address signals ADR0, ADR1,.
10 and 211 and the input B of the comparison circuits 212 and 213.

The output of the register 210 is connected to the input A of the comparator 212 and the input A of the adder 214, and the output of the register 211 is connected to the input A of the comparator 213 and the adder 214.
Is connected to the input B. The output of the comparison circuit 212 is connected to the load signal input terminal LD of the register 210, and the output of the comparison circuit 213 is connected to the load signal input terminal LD of the register 211. The output of the adder 214 is connected to the input A of the divider 215.

The enable signal EN of the comparison circuits 212 and 213 is supplied with a different value signal output from the output terminal VO shown in FIG. Further, the registers 210, 2
11 reset signal input terminal RESET and divider 21
The EOS signal output from the vertical scanning circuit 6 shown in FIG. In the present embodiment, the magnitude of the difference between the analog signals (electric signals representing luminance) corresponding to the incident light obtained between two consecutive frames (the (N-1) th frame and the Nth frame) is equal to or greater than a certain value. In this case (when an outlier is detected), the outlier signal output from the output terminal VO indicates a high level.

The operation of the second embodiment will be described below with reference to FIG. First, a description will be given of a method for obtaining the minimum value of the address at which an outlier is detected. When the EOS signal is inverted to the high level, the register 210 is loaded with the maximum possible address value as the initial value of the address signal. For example, when the address signal is 8 bits, “FF” is loaded in BCD notation as an initial value.

The EOS signal is a signal indicating that the scanning of the vertical scanning circuit 6 shown in FIG. 1 has been completed, and goes high when reading of one frame is completed. Therefore, the register 210 is reset when reading of one frame is completed. The input A of the comparison circuit 212 is supplied with the address signal stored in the register 210, and the input B is supplied with the address signals ADR0, ADR0, ADR0,
ADR1,..., ADRn are supplied.

Here, when the different value signal output from the output terminal VO becomes high level (corresponding to the detection of a different value), the comparison circuit 212 becomes valid and compares the input A with the input B. I do. The comparison circuit 212 outputs a high-level signal only when “A> B” is established between the value of the input A and the value of the input B. When the signal output from the comparison circuit 212 becomes high level in this manner,
Register 210 has address signals ADR0, ADR
1, ..., ADRn are loaded.

That is, when the address indicated by the address signals ADR0 to ADRn is smaller than the address stored in the register 210, the register 210 is loaded with the address signals ADR0, ADR1,..., ADRn.
Therefore, when such an operation is completed for one frame, the minimum value of the address at which the different value is detected is stored in the register 210 and supplied to the input A of the adder 214.

Next, a description will be given of a method of obtaining the maximum value of the address at which the different value is detected. When the EOS signal is inverted to the high level, the register 211 is loaded with the minimum address value (for example, “0”) as the initial value of the address signal. The input signal A stored in the register 211 is supplied to the input A of the comparison circuit 213, and the address signals ADR0, ADR
, ADRn are supplied.

Here, when the different value signal output from the output terminal VO becomes high level (a different value is detected), the comparison circuit 213 becomes valid and compares the input A with the input B. . The comparison circuit 213 outputs a high level signal only when “A <B” is established between the value of the input A and the value of the input B. When the signal output from the comparison circuit 213 goes high in this way, the register 21
1, address signals ADR0, ADR1,..., ADR
n is loaded.

That is, when the address indicated by the address signals ADR0 to ADRn is larger than the address stored in the register 211, the register 211 is loaded with the address signals ADR0, ADR1,.
Therefore, when such an operation is completed for one frame, the maximum value of the address at which the different value is detected is stored in the register 211 and supplied to the input B of the adder 214.

The adder 214 has the register 2
The address signal stored in each of the reference numerals 10 and 211 is constantly supplied. The adder 214 supplies a value obtained by adding the addresses indicated by these address signals to the input A of the divider 215. When the EOS signal is inverted to a high level, the divider 215 becomes valid and divides the value supplied to the input A by two. That is, the divider 215 adds the minimum value and the maximum value of the address where the different value is detected to the adder 214.
, The result of the addition will be divided by two.

Therefore, according to the present embodiment, the minimum address and the maximum address of the area in which the outlier is detected are obtained, and the horizontal address and the vertical direction with respect to the center of the area in which the outlier is detected are obtained by the average value. Can be obtained reliably. (Third Embodiment) FIG. 9 is a view for explaining the operation of the third embodiment.

The third embodiment corresponds to an embodiment corresponding to the second and fourth aspects of the present invention.
The configuration of the third embodiment is characterized in that the circuit configuration shown in FIG. 9 is added to each of the horizontal address counter 200 and the vertical address counter 202 in FIG. Therefore, here, the third embodiment will be described with reference to FIG. 9 while avoiding overlap with the first embodiment.

In FIG. 9, address signals ADR0, ADR0, A
, ADRn are address signals ADRH0, ADR0 output from the horizontal address counter 200 shown in FIG.
DRH1,..., ADRHk or the address signals ADRV0, ADR output from the vertical address counter 202
V1,..., ADRVi. Such address signals ADR0, ADR1,..., ADRn are supplied to the input A of the accumulator 216.

The output of the accumulator 216 is connected to the input of the register 217, and the output of the register 217 is input to the input B of the accumulator 216 and the input A of the divider 218. Further, the output of the accumulator 219 is connected to the input of the register 220, and the output of the register 220 is connected to the input B of the divider 218 and the accumulator 219.
To the input B. Note that “1” is always supplied to the input A of the accumulator 219.

The different value signals output from the output terminal VO are supplied to the enable terminals EN of the accumulators 216 and 219. Further, the enable terminal EN of the divider 218 is supplied with the EOS signal output from the vertical scanning circuit 6 shown in FIG.
The reset signal input terminal RESET has a delay circuit 22
1, the EOS signal is supplied.

In the present embodiment, the magnitude of the difference between the analog signals (electric signals representing luminance) corresponding to the incident light obtained between two consecutive frames (the (N-1) th frame and the Nth frame) is different. When the value is equal to or more than a certain value (when a different value is detected), the different value signal output from the output terminal VO indicates a high level. Hereinafter, the operation of the third embodiment will be described with reference to FIG.

When the EOS signal is inverted to a high level,
Registers 217 and 220 are loaded with “0” as an initial value. The input A of the accumulator 216 includes address signals ADR0, ADR1,.
n is supplied to the input B, and the address signal (initial value: 0) stored in the register 217 is supplied to the input B.

Here, each time the different value signal output from the output terminal VO becomes high level (a different value signal is detected), the accumulator 216 becomes valid and adds the values of the input A and the input B. Then, the data is supplied to the register 217. That is, the accumulator 216 calculates the sum of the addresses where the different values are detected, and the register 217 stores the sum.

Further, the accumulator 219 adds “1” to the value (initial value: 0) stored in the register 220 and supplies it to the register 220 every time the different value signal becomes high level. That is, the value of the register 220 is counted up (incremented) by one each time the outlier signal becomes a high level, and indicates the total sum of pixels in which outliers are detected.

By the way, the divider 218 always stores the “sum of addresses at which outliers are detected” stored in the register 217 and the “sum of pixels at which outliers are detected” stored in the register 220. Supplied. Divider 218
Becomes effective when the EOS signal is inverted to the high level, and divides "the sum of the addresses where the different values are detected" by the "sum of the pixels where the different values are detected". Note that the divider 218
Becomes valid immediately before the registers 217 and 220 are reset.

Therefore, according to the present embodiment, the horizontal address and the vertical address of the center of gravity of the area in which an outlier is detected can be reliably obtained. As described above, according to the second embodiment and the third embodiment, a region where an outlier is detected can be easily identified.
The application field of the image processing system using the solid-state imaging device 10 for change detection to which these embodiments are applied is significantly expanded.

In the second embodiment and the third embodiment, the addresses of the center and the center of gravity of the area where the outlier is detected are obtained, but only the invention of claim 2 is applied.
When the different value signal becomes high level, the address signal A
DR0, ADR1,..., ADRn may be output. For example, if a change detection solid-state imaging device having such a configuration is used in a system for monitoring a position where a change is detected in a remote place, only the address of the center or the center of gravity of a region where an outlier is detected is directly transferred. be able to. This eliminates the need to transfer video signals as in the past,
The equipment cost and communication cost for communication can be reduced, and a system that is totally inexpensive can be provided.

(Fourth Embodiment) FIG. 10 is a circuit diagram showing an internal configuration of an outlier detection circuit 50 according to a fourth embodiment. FIG. 11 is a timing chart illustrating an operation of generating an outlier signal according to the fourth embodiment.

A feature of the configuration of the fourth embodiment is that an outlier detection circuit 50 shown in FIG. 10 is provided in place of the outlier detection circuit 20 in FIG. 1. 1, FIG. 2 and FIG. 4, and a description thereof is omitted here. In FIG. 10, the different value detection circuit 50 includes two capacitors CCA and CCB and five inverters IN.
V1 to INV5, four switching MOS transistors QB1 to QB4, and a NAND circuit NA.

Here, the capacitor CCA and the switch M
The OS transistor QB1 forms a first sample and hold circuit 51A, and the capacitor CCB and the switching MOS transistor QB2 form a second sample and hold circuit 51B. Capacitor CC
One electrode of A, CCB is connected to the vertical read line 2, and the other electrode of capacitors CCA, CCB is
The switching MOS transistors QB1 and QB2 are connected to the input terminals of the inverters INV1 and INV2.
Connected to the drain of

The switching MOS transistor QB
1 and QB2 are connected to a constant voltage power supply VR (not shown).
1 and VR2 are connected to each other, and the gates of the switching MOS transistors QB1 and QB2 are connected to the clock line 8a.
Are supplied with a drive pulse φSA. Further, the output terminals of the inverter INV1 are connected to the inverters INV3 and INV3, respectively.
One input terminal of the NAND circuit NA is connected via the INV5, and the other input terminal of the NAND circuit NA is connected to the output terminal of the inverter INV2 via the inverter INV4.

The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV1 to form a closed loop, and the output terminal of the inverter INV4 is connected to the inverter IV4.
Connected to the input terminal of NV2 to form a closed loop. Further, the output terminal of the inverter INV3 is connected to the inverter INV3.
On the signal line reaching the input terminal of V1, there is a switching MOS
A transistor QB3 is provided, and a switching MOS transistor QB4 is provided on a signal line extending from an output terminal of the inverter INV4 to an input terminal of the inverter INV2.

Further, the switching MOS transistor Q
The driving pulse φSB is supplied to the gate of B3 and the switching MOS transistor QB4 via the clock line 9a. Note that the output of the NAND circuit NA is the same as that of the outlier detection circuit 20 of the first embodiment.
The shift register 13 is connected to the data input terminals Q1 to Qn of the corresponding bit register.

That is, an output signal of the outlier detection circuit 50 (an outlier signal indicating a difference in luminance between two consecutive frames).
Are stored in a corresponding register of the shift register 13 at a predetermined timing, and are sequentially output from an output terminal of the shift register 13 in accordance with a clock pulse φCK input to the shift register 13. Hereinafter, a specific operation of the outlier detection circuit 50 (an operation of generating an outlier signal) will be described as an operation of the fourth embodiment with reference to FIGS.

As shown in FIG. 11, the period t of the N-th frame
10 (the end of the period t26 of the (N-1) th frame), the driving pulse φTG1 and the driving pulse φPX
1. The drive pulse φRG1 and the drive pulse φSA are held at a low level, and the drive pulse φSB is held at a high level.

Here, since the drive pulse φTG1 is at a low level, the charge transfer MOS switch QT shown in FIG. 2 is turned off, and the drive pulse φRG1 is at a low level, so that the reset MOS switch QR1 is also turned off. Therefore, although the gate of the amplifying MOS transistor QA is in a floating state, the charges (to the gates of the amplifying MOS transistors QA already transferred to the gates of the respective amplifying MOS transistors QA via the charge transfer MOS switches QT during the period t14 of the (N-1) th frame). The first signal charge) is held at the gate of the amplification MOS transistor QA even after the charge transfer MOS switch QT is turned off due to the effect of the parasitic capacitance (CS1).

The charge transfer MO in the (N-1) th frame
After the S switch QT is turned off, a charge (second signal charge) according to the incident light is newly generated and accumulated in each photodiode PD. In such a state, when the period t10 is reached, the drive pulse φSB which has been held at the high level until then is inverted to the low level.

In the next period t11, the drive pulse φPX1 is inverted from low level to high level, and the drive pulse φSA is inverted from low level to high level.
Here, since the drive pulse φPX1 becomes high level,
An electric signal (first output signal) corresponding to the first signal charge already held at the gate of the amplification MOS transistor QA is supplied to the capacitor CC by the source follower operation.
A and CCB are supplied to one of the electrodes CCA1 and CCB1.

Since drive pulse φSA attains a high level, switching MOS transistors QB1, QB2
Is turned on, and the other electrodes CCA2 and CCB2 of the capacitors CCA and CCB are supplied with a constant voltage VR1 (= VT−V
th) and VR2 (= VT + Vth).
Note that VT is the inverter INV1 and the inverter INV2.
, And Vth is a predetermined value.

At this time, since the drive pulse φSB remains at the low level, the path from the output terminal of the inverter INV3 to the input terminal of the inverter INV1 and the path from the output terminal of the inverter INV4 to the input terminal of the inverter INV2 are , Will be shut off. Therefore, the potential difference between both ends of the capacitor CCA is equal to the difference between the electric signal corresponding to the incident light in the (N−1) th frame (hereinafter, referred to as “electric signal VA”) and the constant voltage VR1 (= VT−Vth). become. The potential difference between both ends of the capacitor CCB is
The electric signal VA in the (N-1) th frame and the constant voltage V
R2 (= VT + Vth).

Then, during the period t12, the drive pulse φSA is inverted to a low level, and the drive pulse φRG1 is inverted to a high level. Here, since the driving pulse φSA is inverted to a low level, both ends of the capacitor CCA
Electric signal VA and constant voltage VR in the (N-1) th frame
1 (= VT−Vth) is stored as it is, and the difference between the electric signal VA and the constant voltage VR2 (= VT + Vth) in the (N−1) th frame is stored directly at both ends of the capacitor CCB.

Since the drive pulse φRG1 is inverted to the high level, the reset MOS switch QR1 is turned on, and the operation of resetting the charge stored in the gate of the amplification MOS transistor QA is performed. Period t13
, The drive pulse φRG1 is inverted to a low level, so that the reset MOS switch QR1 is turned off,
The reset operation is released.

In the period t14, the driving pulse φTG1
Is inverted to a low level, the charge transfer MOS switch QT is turned on, and a charge (second signal charge) newly generated and accumulated in the photodiode PD according to the incident light up to this point is transferred. MOS switch Q
The signal is directly transferred to the gate of the amplification MOS transistor QA via T.

At this time, the amplification MOS transistor QA performs a source follower operation, and an electric signal (second output signal) corresponding to the second signal charge is transferred to the vertical read line 2. In the period t15, the driving pulse φTG1 is inverted to a low level, and the driving pulse φLD is inverted to a high level. Here, since the drive pulse φTG1 is inverted to a low level, the charge transfer MOS switch QT is turned off,
The transfer of the charge (second signal charge) corresponding to the incident light generated and stored in the photodiode PD to the gate of the amplification MOS transistor QA ends.

At this time, the gate of the amplifying MOS transistor QA is again brought into a floating state, but the potential of the gate is reduced by the transferred charge (second signal charge) due to the effect of the parasitic capacitance (CS1). Changes and that state is maintained. Therefore, the amplification MOS transistor Q
From A, an electric signal (hereinafter, referred to as an electric signal) corresponding to the electric charge (second signal electric charge) accumulated in the gate by the source follower operation.
It is described as “electric signal VB”. ) Is the capacitor CC
A and CCB are supplied to one of the electrodes CCA1 and CCB1.

By the way, at the time when the electric signal VB corresponding to the electric charge (second signal electric charge) obtained in the N-th frame is supplied to one of the electrodes CCA1 and CCB1 of the capacitors CCA and CCB, both ends of the capacitor CCA Is the N-th
The electric signal VA and the constant voltage VR1 (=
VT−Vth), and the electric signal VA and the constant voltage VR2 (= VT + V) are provided at both ends of the capacitor CCB.
th) is stored.

That is, when the electric signal VB in the Nth frame is supplied to one electrode CCA1 of the capacitor CCA, the potential of the other electrode CCA2 of the capacitor CCA becomes "VB + VR1-VA". On the other hand, the electric signal V
When B is supplied to one electrode CCB1 of the capacitor CCB, the potential of the other electrode CCB2 of the capacitor CCA becomes “VB + VR2-VA”.

The inverter INV1 operates when the potential on the input side (corresponding to "VB + VR1-VA" in this case) becomes larger than VT (VB + VR1-VA> V).
T) Output a low-level signal. That is, the inverter INV1 outputs a low-level signal when the electric signal VB in the N-th frame (current frame) becomes larger than “VT + VA−VR1”.

Here, as described above, “VR1 = VT−
Vth ", the inverter INV1 outputs a low-level signal when VB becomes larger than" VA + Vth ", and outputs a high-level signal when VB becomes smaller than" VA + Vth ". That is, the inverter INV1 outputs a low-level signal when "VB-VA" exceeds Vth, and outputs a high-level signal when "VB-VA" falls below Vth.

On the other hand, the inverter INV2 sets the input side potential (corresponding to VB + VR2-VA in this case) to VT.
When it becomes larger than (VB + VR2-VA> VT),
Outputs a low-level signal. That is, the inverter I
NV2 outputs a low-level signal when the electric signal VB in the N-th frame (current frame) becomes larger than “VT + VA−VR2”.

Here, as described above, “VR2 = VT +
Vth ", the inverter INV2 outputs a low-level signal when VB becomes larger than" VA-Vth ", and outputs a high-level signal when VB becomes smaller than" VA-Vth ". I do. That is, the inverter INV2 outputs a low-level signal when "VB-VA" exceeds "-Vth", and outputs a high-level signal when "VB-VA" falls below "-Vth".

Note that the output signal of the inverter INV1 is
After being inverted by the inverters INV3 and INV5, the signal is transferred to one input terminal of the NAND circuit NA. The output signal of the inverter INV2 is inverted by the inverter INV4 and then transferred to the other input terminal of the NAND circuit NA. . The signal transferred to the input terminal of the NAND circuit NA in this way is logically operated. As a result, from the output terminal of the NAND circuit NA,
A low-level signal is output when “VB-VA” is within the range of “−Vth to Vth”, and a high-level signal when “VB-VA” is outside the range of “−Vth to Vth”. Is output.

The signal output from the output terminal of the NAND circuit NA is output from the different value detection circuit 50 as a different value signal. In the period t15, the driving pulse φLD is at a high level, so that the different value signal output from the different value detection circuit 50 is stored in the register of the shift register 13. Then, in the next period t16, when the clock pulse φCK is input to the shift register 13, the different value signal held in the register corresponding to each bit is sequentially output from the output terminal VO via the horizontal read line 12. Is done.

In the period t16, the driving pulse φSB
Becomes high level, the output terminal of the inverter INV3 and the input terminal of the inverter INV1 are connected to form a closed loop, and the output terminal of the inverter INV4 and the input terminal of the inverter INV2 are connected to form a closed loop. . When a closed loop is formed between the inverter INV3 and the inverter INV1, the output of the inverter INV1 is fixed, and the output of the inverter INV1 is fixed.
When a closed loop is formed between the inverter INV2 and the inverter INV2, the output of the inverter INV2 is fixed (that is, the logical outputs of the inverters INV1 and INV2 can be stabilized). The output of the inverters INV1 and INV2 is fixed until the drive pulse φSB is inverted to the low level (until the period t20).

As described above, in the present embodiment, the magnitude of the difference between the electric signals (electric signals representing luminance) obtained in two consecutive frames (the (N-1) th frame and the Nth frame) is determined in advance. It is possible to reliably determine whether or not it is within the specified range. Further, the threshold value used for such a determination can be set freely. Therefore, according to the present embodiment, similarly to the first embodiment, it is possible to detect a pixel having a difference in the magnitude of the electric signal difference between two consecutive frames, and the field of application for image processing is remarkable. Expanding.

The invention corresponding to each of the above-described embodiments is not limited to a solid-state imaging device for visible light, but is applicable to a solid-state imaging device for received electromagnetic waves of any wavelength such as X-rays, ultraviolet rays, and infrared rays. it can. (Fifth Embodiment) FIG. 12 is a circuit diagram showing an internal configuration of a pixel 60 according to a fifth embodiment.

FIG. 13 is a timing chart for explaining the operation of the pixel 60. Note that the fifth embodiment corresponds to an embodiment corresponding to the invention described in claims 6 and 7. Further, the feature of the configuration of the fifth embodiment is that FIG.
A pixel 60 shown in FIG. 12 is provided in place of the pixel 1 of FIG. 12, and a clock line 61 for supplying drive pulses φRP1 to φRPm is newly provided for each pixel 60. 3 and FIG.
Here, the description is omitted.

Note that the pixel 60 shown in FIG. 12 is a pixel arranged in the first row and the first column. In FIG. 12, a pixel 60
Has a photodiode PD that generates and accumulates charges according to incident light. In the present embodiment, the photodiode PD is a Schottky junction photodiode formed of platinum silicide and a p-type silicon substrate.

The cathode of the photodiode PD is connected to one end of a charge storage capacitor CS1 and the gate of an amplifying MOS transistor (N-channel type) QA via a charge transfer MOS switch QT.
Via an OS switch (P-channel type) QR2, it is connected to a wiring layer maintained at a constant reset potential VRD. The gate of the amplification MOS transistor QA is connected to a wiring layer maintained at a constant reset potential VRD via a reset MOS switch (P-channel type) QR1. The source of the amplification MOS transistor QA is connected to the vertical read line 2 via a vertical transfer MOS switch (P-channel type) QX.

The drive pulse φTG1 is supplied to the gate of the charge transfer MOS switch QT, and the drive pulse φRG is supplied to the gate of the reset MOS switch QR1.
1 is supplied to the gate of the vertical transfer MOS switch QX, and the drive pulse φPX1 is supplied to the reset MO switch QX.
The drive pulse φRP1 is supplied to the gate of the S switch QR2.

Hereinafter, referring to FIG. 12 and FIG.
The operation of the embodiment will be described. In the present embodiment,
The following description focuses on the operation related to each pixel 1 in the first row in the Nth frame. As shown in FIG. 13, immediately before the period t10 in the Nth frame (the period t10 in the (N-1) th frame).
26, the driving pulses φTG1, TG2,
φPX1, φPX2, φRG1, φRG2, φRP1,
φRP2 is held at a low level.

Here, since the driving pulses φTG1 and φTG2 are at low level, the charge transfer MOS switch QT of the pixel 60 is turned off, and since the driving pulses φRG1 and φRG2 are at low level, the resetting MOS switch QT of the pixel 60 is turned off.
R1 is off. Therefore, although the gate of the amplifying MOS transistor QA is in a floating state, the charges (to the gates of the amplifying MOS transistors QA already transferred to the gates of the respective amplifying MOS transistors QA via the charge transfer MOS switches QT during the period t14 of the (N-1) th frame). The first signal charge) is held at the gate of the amplification MOS transistor QA even after the charge transfer MOS switch QT is turned off due to the effect of the parasitic capacitance (CS1).

The charge transfer MO in the (N-1) th frame
After the S switch QT is turned off, as described later,
The reset MOS switch QR2 is turned on, and the photodiode PD is reset (precharged). Thereafter, the reset MOS switch QR2 is turned off,
In the photodiode PD, a charge (second
Is newly generated and accumulated.

Here, the first signal charge is a charge corresponding to the incident light in the (N-1) th frame, and the second signal charge is a charge corresponding to the incident light in the Nth frame. In the period t11, the driving pulse φPX1 is inverted to the high level, and the vertical transfer MO of each pixel 60 in the first row is changed.
When the S switch QX is turned on, the source of the amplification MOS transistor QA is connected to the vertical read line 2. Since the drive pulse φPX2 is at a low level, the vertical transfer MOS switch QX of each pixel 60 in the second row is used.
Is off, and the amplification M of each pixel 60 in the second row is
The source of the OS transistor QA is not connected to the vertical read line 2.

That is, in the period t11, the amplification MOS transistor QA of each pixel 60 in the first row is selected. At this time, the amplification M of each pixel 60 in the first row is used.
Since the first signal charge is held at the gate of the OS transistor QA as described above, the vertical read line 2
Outputs an electric signal (first output signal) corresponding to the first signal charge.

Then, during the period t12, the drive pulse φRG1 is inverted to the high level, so that the reset MOS switch QR1 of each pixel 60 in the first row is turned on, and the power supply voltage VRD is set as the read level in the first row. It is supplied to the gate of the amplification MOS transistor QA of each pixel 60 of the eye. That is, the reset MOS switch QR
When 1 is turned on, the first signal charge is reset (discharged) from the gate of the amplification MOS transistor QA.
At the same time, the gate of the amplification MOS transistor QA is biased to the read level by the power supply voltage VRD.

At the start of the period t13 (at the end of the period t12), the driving pulse φRG1 is inverted to the low level, so that the reset MOS switch QR1 of each pixel 60 in the first row is turned off again, and the first row is turned off. Each pixel 60 of the eye
The gate of the amplifying MOS transistor QA is in a floating state, but due to the effect of the parasitic capacitance, the gate is kept in a state of being biased to the read level.

Then, during the period t14, the drive pulse φTG1 is inverted to the high level, so that the charge transfer MOS switch QT of each pixel 60 in the first row is turned on,
The charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD of each pixel 60 on the first row is transferred to the gate of the amplification MOS transistor QA of each pixel 60 on the first row. Transferred directly.

As described above, the amplification MOS transistor QA
Is transferred to the gate of the Nth frame (current frame) according to the incident light in the Nth frame (current frame), the gate potential of each amplifying MOS transistor QA becomes
Since the change is made by the transferred charge, the amplification MOS transistor QA of each pixel 60 in the first row performs a source follower operation, and the source potential of the amplification MOS transistor QA changes by the change in the gate potential. .

At this time, the amplifying MOS transistor QA of each pixel 60 in the first row that performs the source follower operation,
An electric signal (second output signal) corresponding to the second signal charge is output to the vertical read line 2 via the vertical transfer MOS switch QX that is already on. At the start of period t15 (at the end of period t14), drive pulse φ
Since TG1 is inverted to the low level, the charge transfer MOS switch QT of each pixel 60 in the first row is turned off, and the charge transfer MOS switch QT is turned on in accordance with the incident light generated and accumulated in the photodiode PD of each pixel 60 in the first row. Charge (second signal charge)
Transfer to the gate of the amplifying MOS transistor QA is completed, and the gate of the amplifying MOS transistor QA is brought into a floating state again. However, the potential of the gate is reduced by the effect of the parasitic capacitance (CS1). (The second signal charge), and the state is maintained.

By the way, the electric charge transferred to the gate of the amplifying MOS transistor QA as the second signal electric charge for the N-th frame is the next (N + 1) -th frame (not shown).
Is held until the gate is reset (until the reset MOS switch QR1 is turned on). That is, the second signal charge in the Nth frame is (N + 1) th.
It will be used as the first signal charge in the frame.

As described above, the charge transfer MOS switch QT
Is turned off, the second signal charge is held at the gate of the MOS transistor for amplification QA.
From the transistor QA, an electric signal (second output signal) corresponding to the charge (second signal charge) accumulated in the gate by the source follower operation until the gate is reset is output.

At the start of period t16, drive pulse φR
Since P1 is inverted to the high level, the reset MOS switch QR2 is turned on, and the photodiode PD is reset (precharged). Then, drive pulse φ
RP1 is inverted to low level. Further, in the period t16 (before reaching the period t20), the driving pulse φPX1 is inverted to the low level, so that the vertical transfer MOS switch QX of each pixel 60 in the first row is turned off, and each pixel in the first row is turned off. 60 is separated from the vertical read line 2.

In the following period t20 to t26, the period t10 to t1 is applied to each pixel 60 in the second row.
6, the same operation as that of each pixel 60 in the first row is performed. As described above, in the present embodiment, the drive pulse φ
Since the reset MOS switch QR2 is turned on by the RP1, the photodiode PD can be reliably reset (precharged), so that the electronic shutter function can be reliably realized.

Further, restrictions on the magnitude of the capacitance of the charge storage capacitor CS1 and the magnitude of the capacitance of the photodiode PD are relaxed. Therefore, for example, when the photoelectric conversion characteristic (sensitivity) of the photodiode PD depends on the bias voltage, the photodiode PD is made larger by making the capacitance of the photodiode PD larger than the capacitance of the charge storage capacitor CS1. In addition, photoelectric conversion can be performed in a state where the bias voltage is large, and the sensitivity is improved.

(Sixth Embodiment) FIG. 14 is a circuit diagram showing an internal configuration of a pixel 70 according to a sixth embodiment.
FIG. 15 is a timing chart illustrating the operation of the pixel 70. Note that the sixth embodiment corresponds to an embodiment corresponding to the invention described in claims 6 and 7. A feature of the configuration of the sixth embodiment is that a pixel 70 shown in FIG. 14 is provided instead of the pixel 1 in FIG. 1, and a clock line 61 for supplying drive pulses φRP1 to φRPm is newly provided for each pixel 70. The other points are as follows.
The description is omitted here because it is the same as FIG. 1, FIG. 3 and FIG.

Note that the pixel 70 shown in FIG. 14 is a pixel arranged in the first row and the first column. In FIG. 14, the pixel 70
Has a photodiode PD that generates and accumulates charges according to incident light. In the present embodiment, the photodiode PD is a Schottky junction photodiode formed of platinum silicide and a p-type silicon substrate.

The cathode of the photodiode PD is connected to one end of a charge storage capacitor CS1 and the gate of an amplification MOS transistor (N-channel type) QA via a charge transfer MOS switch QRT and a charge transfer MOS switch QT. In addition, the charge transfer MOS switch Q
MOS switch for RT and reset (P-channel type)
Via QR3, it is connected to a wiring layer maintained at a constant reset potential VRD. The amplification MOS transistor Q
The source of A is connected to the vertical read line 2 via a vertical transfer MOS switch (P-channel type) QX.

The drive pulse φTG1 is supplied to the gate of the charge transfer MOS switch QT, and the drive pulse φRG is supplied to the gate of the reset MOS switch QR3.
1 is supplied to the gate of the vertical transfer MOS switch QX, and the drive pulse φPX1 is supplied to the charge transfer MO switch QX.
The drive pulse φRP1 is supplied to the gate of the S switch QRT.

Hereinafter, referring to FIG. 14 and FIG.
The operation of the embodiment will be described. In the present embodiment,
The operation related to each pixel 70 in the first row in the Nth frame will be mainly described. As shown in FIG. 15, immediately before the period t10 in the N-th frame (the end of the period t26 in the (N-1) th frame), the drive pulses φTG1, TG
2, φPX1, φPX2, φRG1, φRG2, φRP
1, φRP2 is kept at a low level.

Here, since the drive pulses φTG1 and φTG2 are at low level, the charge transfer MOS switches QT of each pixel 70 are turned off, and since the drive pulses φRG1 and φRG2 are at low level, the reset MOS switch QR3 of each pixel 70 is turned off. It is off. Therefore, the amplification MO
Although the gate of the S transistor QA is in a floating state, the charge (the first signal) already transferred to the gate of each amplification MOS transistor QA via the charge transfer MOS switch QT in the period t14 of the (N-1) th frame. Even after the charge transfer MOS switch QT is turned off due to the effect of the parasitic capacitance (CS1), the charge
It is held at the gate of the transistor QA.

The charge transfer MO in the (N-1) th frame
After the S switch QT is turned off, as described later,
MOS switch QRT for charge transfer and MO for reset
The S switch QR3 is turned on, and the photodiode PD
Is reset (precharged). Thereafter, the charge transfer MOS switch QRT and the reset MOS switch QR3 are turned off, and charges (second signal charges) corresponding to the incident light are newly generated and accumulated in the photodiode PD.

Here, the first signal charge is a charge corresponding to incident light in the (N-1) th frame, and the second signal charge is a charge corresponding to incident light in the Nth frame. In the period t11, the driving pulse φPX1 is inverted to the high level, and the vertical transfer MO of each pixel 70 in the first row is changed.
When the S switch QX is turned on, the source of the amplification MOS transistor QA is connected to the vertical read line 2. Since the driving pulse φPX2 is at a low level, the vertical transfer MOS switch QX of each pixel 70 in the second row is used.
Is off, and the amplification M of each pixel 70 in the second row is
The source of the OS transistor QA is not connected to the vertical read line 2.

That is, in the period t11, the amplification MOS transistor QA of each pixel 70 in the first row is selected. At this time, the amplification M of each pixel 70 in the first row is used.
Since the first signal charge is held at the gate of the OS transistor QA as described above, the vertical read line 2
Outputs an electric signal (first output signal) corresponding to the first signal charge.

Then, during the period t12, the driving pulses φRG1 and φTG1 are inverted to the high level.
The reset MOS switch QR3 and the charge transfer MOS switch QT of each pixel 70 in the row are turned on, and the power supply voltage VRD is set to the read level, and each pixel 7 in the first row is read.
0 is supplied to the gate of the amplifying MOS transistor QA.

That is, the amplification MOS transistor QA
, The first signal charge is reset (discharged), and the gate of the amplifying MOS transistor QA is biased to the read level by the power supply voltage VRD.

At the start of the period t13 (at the end of the period t12), the drive pulses φRG1 and φTG1 are inverted to low level, so that the reset MOS switch QR3 and the charge transfer MOS switch of each pixel 70 in the first row are provided. QT is turned off again, and the gate of the amplifying MOS transistor QA of each pixel 70 in the first row is in a floating state. However, due to the effect of the parasitic capacitance, the state of the gate remains biased to the read level. Is done.

When the period t14 is reached, the driving pulses φTG1 and φRP1 are inverted to the high level.
MOS switch QT, Q for charge transfer of each pixel 70 in the row
When the RT is turned on, the charge (second signal charge) generated and accumulated in the photodiode PD of each pixel 70 in the first row corresponds to the amplification MOS of each pixel 70 in the first row. The data is directly transferred to the gate of the transistor QA.

Thus, the amplification MOS transistor QA
When the charge (second signal charge) corresponding to the incident light in the N-th frame is transferred to the gate of the Nth frame, the gate potential of each amplifying MOS transistor QA changes by the amount of the transferred charge. MOS for amplification of each pixel 70 in the first row
The transistor QA operates as a source follower, and the amplifying MO
The source potential of S transistor QA changes by the change in gate potential.

At this time, the amplifying MOS transistor QA of each pixel 70 in the first row that performs the source follower operation,
An electric signal (second output signal) corresponding to the second signal charge is output to the vertical read line 2 via the vertical transfer MOS switch QX that is already on. At the start of period t15 (at the end of period t14), drive pulse φ
Since TG1 and φRP1 are inverted to low level, the charge transfer MOS switches QT and QR of each pixel 70 in the first row
T turns off, and the transfer of the charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD of each pixel 70 in the first row to the gate of the amplification MOS transistor QA ends. , Amplifying MOS transistor Q
The gate of A is again brought into a floating state, but the potential of the gate changes by the transferred charge (second signal charge) due to the effect of the parasitic capacitance (CS1), and that state is maintained.

By the way, the charge transferred to the gate of the amplifying MOS transistor QA as the second signal charge for the N-th frame (current frame) is the next (N + 1) -th signal charge.
Until the gate is reset in the frame (not shown) (until the reset MOS switch QR1 is turned on)
Will be retained. That is, the second signal charge in the Nth frame is used as the first signal charge in the (N + 1) th frame.

As described above, the charge transfer MOS switch QT
Is turned off, the second signal charge is held at the gate of the MOS transistor for amplification QA.
From the transistor QA, an electric signal (second output signal) corresponding to the charge (second signal charge) accumulated in the gate by the source follower operation until the gate is reset is output.

At the start of period t16, drive pulse φR
Since P1 and RG1 are inverted to the high level, the charge transfer MOS switch QRT and the reset MOS switch QR3 are turned on, and the photodiode PD is reset (precharged). Then, drive pulse φRP
1, RG1 is inverted to low level. In addition, period t16
Before the period t20, the drive pulse φPX1 is inverted to a low level, so that the vertical transfer MOS switches QX of the pixels 70 in the first row are turned off, and the pixels 70 in the first row are read out vertically. Separated from line 2.

In the following period t20 to t26, the period t10 to t1 is applied to each pixel 70 in the second row.
6, the same operation as that of each pixel 70 in the first row is performed. As described above, in the present embodiment, the drive pulse φ
MOS switch QR for charge transfer by RP1 and RG1
Turn on the T and reset MOS switch QR2,
The photodiode PD can be reliably reset (precharged). Therefore, similarly to the fifth embodiment, the electronic shutter function can be reliably realized, and the photodiode PD can perform photoelectric conversion with high sensitivity.

When the solid-state imaging device for detecting a change in infrared light shown in the fifth embodiment and the sixth embodiment is used in a monitoring system, for example, in the daytime, a person (moving body) is used in a place where traffic frequently occurs. Monitoring (for example, playback on a monitor screen), an analog image using a video signal (analog signal) is generated, and monitoring is performed based on this.
In the case of monitoring at night when traffic stops, it is conceivable to generate a binary image using a different value signal (digital signal) and perform monitoring based on this.

As described above, when monitoring with an analog image (video signal) in the daytime and monitoring with a binary image (different value signal) in the nighttime, the solid-state imaging device 10 for change detection is used.
It is not necessary to change the drive timing, and each monitor can be performed easily and appropriately by switching images. That is, optimal monitoring using both or one of the analog image and the binary image can be appropriately performed according to the situation.

The timing of switching between an analog image and a binary image (for example, display on a monitor screen) is as follows.
It may be performed automatically at predetermined time intervals, or the state of change of the different value signal is detected, and an analog image is displayed when the change amount is equal to or more than a predetermined value, and a binary image is displayed when the change amount is equal to or less than a predetermined value. You may. When the change detection infrared solid-state imaging device is applied to an automatic digestion system, it is possible to specify the position where water is to be discharged based on the address where an outlier is detected, and extinguish a fire by discharging water only in a very narrow range. it can. Especially,
By combining with the second embodiment or the third embodiment, it is possible to know the address of the center or the center of gravity of the area where the outlier is detected, and it is possible to easily recognize the position where water is to be discharged. For example, by providing an automatic water discharge gun or the like, an automatic digestion system can be constructed.

Incidentally, in the fifth and sixth embodiments, a Schottky junction type photodiode P formed of platinum silicide and a p-type silicon substrate is used.
D is generally used after cooling to liquid nitrogen temperature. In such a case, since the band gap of the photoelectric conversion unit is low,
Since the excess charges escape to the substrate side, there is no problem even if an overflow drain structure is not provided other than the Schottky junction of the photoelectric conversion unit. That is, bleeding phenomena such as blooming and smear can be suppressed by the Schottky junction of the photoelectric conversion unit.

FIG. 16 is a schematic diagram of a vertical sectional structure of the photoelectric conversion unit. In the figure, a Schottky junction is formed between a platinum silicide 302 and a P-type silicon semiconductor substrate 301. Note that reference numeral 304 denotes a gate electrode of the charge transfer MOS switch QT, reference numeral 303 denotes an aluminum thin film disposed on the photoelectric conversion unit, and reference numeral 305 denotes an aluminum wiring for wiring. In such a configuration, the infrared light enters from the opposite side (that is, the lower side) of the P-type silicon semiconductor substrate 301.

That is, in the fifth and sixth embodiments, a monolithic change detection infrared solid-state imaging device can be easily configured. Since the silicide material is well compatible with the silicon semiconductor process, a change detection solid-state imaging device can be manufactured without specially changing a widely adopted silicon semiconductor process. In addition, when platinum silicide is used, infrared sensitivity is good, a change near normal temperature can be detected, and when nickel silicide is used, it is not necessary to keep the cooling temperature so low, and cooling by electronic cooling is possible, It is possible to provide a change detection solid-state imaging device that can be manufactured at low cost and requires no maintenance.

The solid state imaging device for change detection can exhibit its effects if it can be integrated on a single semiconductor chip.
It is also possible to use a method of manufacturing the semiconductor device by dividing it on a plurality of semiconductor chips. In each of the above-described embodiments, the charge transfer from the photodiode PD to the charge storage capacitor CS1 is performed in units of rows. However, such transfer can be performed for all pixels by changing the signal waveform of the drive pulse. You may go at the same time. That is, in a normal XY scanning type solid-state imaging device, since the inside of the screen is sequentially read out, the synchronization of the imaging time cannot be maintained in the screen, whereas in the solid-state imaging device to which the present invention is applied, the synchronization of the imaging time is not performed. Can easily be maintained.

Therefore, in the change detection solid-state imaging device to which the present invention is applied, when the transfer of the charge from the photodiode PD to the charge storage capacitor CS1 is performed simultaneously for all pixels, an image having a drastic change with time is obtained. Also, since the synchronization of imaging can be maintained, it is possible to detect outliers with faithful position information.

[0210]

As described above, according to the first aspect of the present invention, since a different value signal indicating a change of a subject can be generated by the comparing means without separately providing an AD conversion circuit, the conventional image processing for change detection is performed. The circuit configuration can be significantly simplified as compared with the device.

Therefore, the size and cost of the change detection solid-state imaging device can be reduced. According to the first aspect of the present invention, since the comparing unit is provided not in units of each pixel but in association with the vertical readout line, the structure of each pixel can be simplified, and the aperture of the solid-state imaging device can be simplified. An outlier signal can be generated without reducing the rate or resolution.

Further, in the invention according to the first aspect, in the process of generating the different value signal, the position information indicating the position of the light receiving section is directly output based on the drive timing of the vertical transfer means and the horizontal transfer means. Therefore, it is possible to accurately associate the different value signal with the position of the pixel. The position information may be two-dimensional information in a horizontal direction and a vertical direction, or may be one-dimensional information.

According to the second aspect of the present invention, it is possible to generate change position information indicating the position of the light receiving section where the pixel output has changed between the immediately preceding frame and the current frame. Therefore, in the information processing apparatus to which the change detection solid-state imaging device according to claim 2 is applied, the field of use can be significantly expanded. According to the third aspect of the invention, since the position of the center of the area where the change has occurred can be detected, for example, when the change detection solid-state imaging device of this configuration is used for a fire detector, Location can be estimated.

According to the fourth aspect of the present invention, the position of the center of gravity of the area where the change has occurred can be detected. When estimating the location of the fire using the change detection solid-state imaging device according to claim 3, an error is likely to occur due to the shape of the flame, whereas the change detection solid-state imaging device according to claim 4 In the device, such an error can be reliably reduced.
According to the fifth aspect of the present invention, it is possible to simultaneously generate an outlier signal and an image signal.

According to the present invention, the electronic shutter operation can be easily realized. Therefore, a change detection solid-state imaging device for visible light corresponds to a phenomenon from dark to bright, and a change detection solid-state imaging device for infrared light corresponds to a phenomenon from low to high temperatures. Thus, a change in the subject can be detected. According to the seventh aspect of the present invention, it is possible to easily configure a monolithic type change detection solid-state imaging device for infrared light.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram illustrating a schematic configuration of a change detection solid-state imaging device according to a first embodiment.

FIG. 2 is a circuit diagram illustrating an internal configuration of a pixel according to the first embodiment.

FIG. 3 is a circuit diagram illustrating an internal configuration of an outlier detection circuit according to the first embodiment;

FIG. 4 is a circuit diagram showing an internal configuration of a video signal generation circuit.

FIG. 5 is a timing chart illustrating an operation of generating a different value signal according to the first embodiment.

FIG. 6 is a timing chart illustrating an operation of outputting an address signal according to the first embodiment.

FIG. 7 is a characteristic diagram illustrating an example of input / output characteristics of a voltage comparator.

FIG. 8 is a diagram illustrating the operation of the second embodiment.

FIG. 9 is a diagram illustrating the operation of the third embodiment.

FIG. 10 is a circuit diagram illustrating an internal configuration of an outlier detection circuit according to a fourth embodiment;

FIG. 11 is a timing chart illustrating an operation of generating a different value signal according to a fourth embodiment.

FIG. 12 is a circuit diagram illustrating an internal configuration of a pixel according to a fifth embodiment.

FIG. 13 is a timing chart illustrating the operation of the pixel according to the fifth embodiment.

FIG. 14 is a circuit diagram illustrating an internal configuration of a pixel according to a sixth embodiment.

FIG. 15 is a timing chart illustrating the operation of the pixel according to the sixth embodiment.

FIG. 16 is a schematic diagram of a vertical cross-sectional structure of a photoelectric conversion unit.

FIG. 17 is a diagram illustrating a configuration of a change detection image processing apparatus.

[Explanation of symbols]

1, 60, 70 pixels 2 Vertical readout line 2-1 2-2 Readout line 6 Vertical scanning circuit 8, 9, 11, 15, 16, 32, 36, n1 Node 3, 4, 5, 8a, 9a, 11a , 15a, 16a, 3
2a, 36a, 61 clock lines 10 solid-state imaging device for change detection 12, 34 horizontal readout line 13 shift register 14 selection signal line 17 constant current source 20 outlier detection circuit 30 video signal generation circuit 33 horizontal selection signal line 35 horizontal scanning circuit 37 output buffer amplifier 50 outlier detection circuit 51A, 51B sample hold circuit 100 change detection image processing device 101 solid-state imaging device 102 AD conversion circuit 103 first image memory 104 second image memory 105 image processing circuit 200 horizontal address counter 202 Vertical address counter 210, 211, 217, 220 Register 212, 213 Comparison circuit 214 Adder 215, 218 Divider 216, 219 Accumulator 221 Delay circuit 301 P-type silicon semiconductor substrate 302 White Silicide 303 aluminum thin film 304 gate electrode 305 of aluminum wiring QRSV, QRSH, QR1, QR2 reset MO
S switch Q1 to Qn Data input terminal LD Load signal input terminal CK Clock signal input terminal VO, Ao Output terminal QH Horizontal transfer MOS switch RESET Reset signal input terminal PD Photodiode QT, QRT Charge transfer MOS switch CS1 Charge storage capacitor QA Amplification MOS transistor QX Vertical transfer MOS switch XA Different value detector AP1, AP2 Voltage comparator OR OR operator CL, CS Signal storage capacitor QL, QS, QV Switch MOS transistor CV Hold capacitance EN Enable terminal CCA , CCB capacitors INV1, INV2, INV3, INV4, INV5
Inverter QB1, QB2, QB3, QB4 Switching MOS transistor NA NAND circuit

Claims (7)

[Claims] A plurality of light receiving units arranged in a matrix and generating pixel outputs according to incident light; a plurality of vertical read lines provided in association with respective columns of the plurality of light receiving units; While holding the pixel output generated by each of the plurality of light receiving units, the already held “pixel output for the immediately preceding frame” and the “pixel output for the current frame” newly generated by the light receiving unit are referred to as Vertical transfer means for transferring a row to a vertical readout line in a row unit; provided in association with each of the vertical readout lines; "pixel output for the immediately preceding frame" and "pixel for the current frame" transferred to the vertical readout line. A plurality of comparing means for comparing the "output" with each other and generating an outlier signal indicating a change of a subject between consecutive frames; and an outlier signal generated by each of the plurality of comparing means. Horizontal transfer means for performing horizontal transfer, and position information for generating position information indicating the position of the light receiving unit in association with the different value signal based on a drive timing of at least one of the vertical transfer means and the horizontal transfer means. A change detection solid-state imaging device comprising: a generation unit. 2. The change-detection solid-state imaging device according to claim 1, wherein a light-receiving unit whose pixel output has changed between a previous frame and a current frame is detected based on the outlier signal. A solid state imaging device for change detection, comprising: change position information generation means for generating change position information indicating a position of a light receiving section whose pixel output has changed from position information generated by the position information generation means. 3. The change detection solid-state imaging device according to claim 2, wherein a change has occurred with respect to the immediately preceding frame in the current frame based on the change position information generated by the change position information generating means. A solid state imaging device for change detection, comprising: center position information generating means for generating center position information indicating a position of a center of a region. 4. The change detection solid-state imaging device according to claim 2, wherein a change has occurred from a previous frame in a current frame based on the change position information generated by the change position information generating means. A solid-state imaging device for change detection, comprising: a center-of-gravity position information generating unit that generates center-of-gravity position information indicating a position of a center of gravity of a region. 5. The change detection solid-state imaging device according to claim 1, wherein the “pixel output for the immediately preceding frame” or the “pixel output for the current frame” transferred to the vertical readout line. A change detection solid-state imaging device, comprising: an image generation unit that obtains one of pixel outputs of “pixel output” and horizontally transfers the pixel output to generate an image signal. 6. The change detection solid-state imaging device according to claim 1, wherein the change detection solid-state imaging device is provided corresponding to each row of the plurality of light receiving sections, and the light receiving sections and a predetermined reset voltage are provided. A plurality of switch means intermittently intermittently, and a switch means corresponding to the light receiving unit is set at a predetermined time before a point in time when a pixel output is taken in from the light receiving unit by the vertical transfer means. A change detection solid-state imaging device, comprising: an electronic shutter control unit that conducts only during a period. 7. The change detection solid-state imaging device according to claim 1, wherein the light receiving section is formed of platinum, nickel, chromium, tungsten, or silicide that is generated by reacting with silicon. And a change detection solid-state imaging device formed by Schottky junction with P-type silicon.