JPH11225333A - Decode processing circuit - Google Patents

Abstract

(57) [Summary] [Problem] Reduce the time required for task switching processing,
Provided is a decoding processing circuit that enables more processing to be executed even with the same hardware, and that does not require a high performance to a DSP. The timing for accepting is limited, and M
Considering the features of PEG processing, each processing specified in MPEG
Task switching is performed at the timing of task switching determination processing 102, 104, 106, 108, 110 provided for each of the units 101, 103, 105, 107, 109, and 111. Thereby, the task can be switched in accordance with the timing at which the data amount of the intermediate result of the temporarily generated operation becomes small, so that the overhead time for the saving process and the returning process can be greatly reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast system in which a plurality of streams of video and audio coded by the MPEG system are multiplexed and transmitted. The present invention relates to a decoding processing circuit that can perform decoding processing at the same time.

[0002]

2. Description of the Related Art In general, a system for transmitting moving images and sounds, such as a television broadcast, a video conference system, and a video telephone, and a method for recording signals such as moving images and sounds on a magnetic disk, an optical disk, and a magnetic tape. In a system for reproducing a recorded signal, a method of performing high-efficiency encoding to increase transmission efficiency is used to effectively use a transmission path and a recording medium.

[0003] A typical method of this high efficiency coding is MPE.
G (Moving Picture Expert Group) 2. MPE
G2 stands for ISO (International Organization for Stand)
ardization) and IEC (International Electrotechica)
l Commission) Joint Technical Committe (JTC)
This is an encoding standard that has been standardized as ISO / IEC 13818 in e).

[0004] In MPEG2, not only the coding standard, but also a method for multiplexing a video stream such as video and audio is specified by the standard so that the encoded data stream such as video and audio can be used for a wide range of purposes. Have been. This standard is an MPEG2 system (MPEG2
Systems), depending on the usage of the data stream, a transport stream (TS: Transport Stream) intended for application to broadcasting and communication,
Program stream (PS:
Program Stream).

The transport stream has been considered to transmit a plurality of programs in one stream, and is expected to be used in many broadcasting and communication applications in the future.

On the other hand, DSP (Digital Signal Processo)
By using r), it is also possible to perform decoding of a video signal compressed using the MPEG method. The processing power of the hardware in the DSP has been improved,
Since the operation speed of the IC has also been improved, it is possible to decode a plurality of video signals and a plurality of audio signals included in the MPEG stream.

A DSP generally has at least one arithmetic unit (CPU), and can execute program decoding and data retrieval simultaneously by various register functions.
In addition, parallel operation can be performed.

[0008] In an MPEG decoding processing circuit using a DSP, which is used in a digital broadcast receiving apparatus or the like, an input bit stream inputted is temporarily stored in an input buffer. The instructions stored in the instruction memory are read out in order and given to an instruction decoder for decoding.
The decoded instruction exchanges data with a data memory, a computing unit, a register, an input buffer, and an output buffer according to the contents. The data after the operation is sent to an output buffer and output as a signal from an output terminal or stored in a data memory.

[0009] A signal is periodically supplied from the timer to the instruction decoder to interrupt the execution of the program. When an interrupt is issued, the instruction decoder starts processing a predetermined program.

[0010] When decoding a plurality of videos and a plurality of sounds, programs for executing respective processes executed by the DSP are executed in parallel. Executing a plurality of programs in parallel is generally called multitask processing. When performing such multitask processing, the DSP executes processing for each video and audio while temporally switching one of the plurality of program tasks.

FIG. 11 shows a flowchart of a program processed by the DSP. Here, one task 11 is a decoding process for the first input stream, and another task 13 is a decoding process for the second input stream. These decoding processes are executed while being alternately switched in time by the task switching process 12.

FIG. 12 shows the contents of the decoding process in FIG. In the case of an MPEG2 video stream, a decoding process is performed in accordance with the layers constituting the stream. That is, the decoding process is MPEG
It is performed in units of processing specified by two video layers (MPEG2 VideoLayer). The unit of processing of MPEG2 is
There are a sequence layer process 21, a GOP layer process 22, a picture layer process 23, a slice layer process 24, a macro block layer process 25, and a block layer process 26. In addition,
MPEG2 allows a structure with a GOP layer,
It is possible to create a stream that does not have one.

In MPEG2, 8 × 8 pixels of a luminance image are defined as a block, and four of these collectively form a macroblock. A macro block includes a luminance signal and a chrominance signal. An 8 × 8 pixel block uses DCT (D
iscreate Cosine Transform). Therefore, an inverse DCT operation is performed in MPEG2 decoding processing. The inverse DCT operation returns the image data expressed on the frequency axis to the time axis data. This requires a cumulative addition operation. Data in the middle of the accumulative addition operation is stored not in the data memory but in a register. This is because the register requires a small number of clocks to access the data memory, so that a high-speed operation can be performed.

On the other hand, in the multitask processing, when the tasks of a plurality of input streams, for example, the first and second input streams have the same priority, the task switching processing is performed by an interrupt signal from a timer. Has become. In such a task switching process, M
Each process 21, 22, 23, 24, 2 specified by PEG
There is a possibility that the process may shift to the task switching process from any of the states 5 and 26, and the switching is performed even during each process.

The task switching is performed by a service routine (IS) which is a program executed by an interrupt.
R). The only interrupt condition in the multitask process is the time interrupt by the timer.
This instructs task switching. The task switching process performs a process for shifting execution from a task that has been executed until now to a task that has not been executed.

FIG. 13 is a flowchart showing a conventional task switching process. In FIG. 13, in the task switching process, first, the result of calculation of the task before switching, that is, the contents of the register, is stored in the data memory (step 3
1). Then, control is transferred to the next task that has not been performed. Before that, the task to be switched is first obtained (step 32), and the intermediate result of the operation of the next task to be shifted is restored from the data memory to the register (step 33). Then, control is transferred to the next task that has not been executed (step 3).
4).

As described above, in the conventional task switching process, when shifting from task to task, it is necessary to save the intermediate result of the operation in the previous task from the register to the data memory. It is necessary to return the operation result of the task from the data memory to the register,
The switching process takes time, and as a result, the decoding process takes time. There is a problem that the so-called overhead time is long.

[0018]

As described above, the conventional D
In the MPEG decoding process using the SP, when a plurality of multiplexed streams are simultaneously processed, there is a problem that an overhead time for a save process and a return process is long when a task is switched.

In view of the above problems, the present invention reduces the time required for task switching processing, enables more processing to be performed even with the same hardware, and provides a high performance to a DSP. It is an object of the present invention to provide a decoding circuit which does not require a request.

[0020]

SUMMARY OF THE INVENTION The present invention is a decoding processing circuit for decoding a plurality of video and audio streams encoded by the MPEG system, and switches between a plurality of program tasks for decoding the plurality of streams. The signal processing is performed while the plurality of program tasks are switched at the timing of each processing unit specified by MPEG.

In the present invention, the timing of task switching, that is, the timing of accepting a timer interrupt is defined. Specifically, considering the characteristics of MPEG processing, the timing for each processing unit specified by MPEG is specified. Then, the task is switched. As a result, the task can be switched in accordance with the timing at which the data amount of the intermediate result of the temporarily generated operation becomes small, so that the overhead time for the save processing and the return processing can be greatly reduced. it can.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
This will be described with reference to FIG. FIG. 1 is a flowchart showing an MPEG decoding process using a DSP in the decoding processing circuit according to the present invention. FIG. 2 is a block diagram showing a configuration of an MPEG decoding processing circuit using a DSP, which is used for a digital broadcast receiving device or the like.

First, referring to FIG. 2, M using a DSP
The configuration of the PEG decode processing circuit 400 will be described.
In FIG. 2, two input bit streams are input, and each input stream is connected to an input terminal 40 respectively.
1, 402. The input buffer 403 temporarily stores input data. The instruction to be processed is written in the instruction memory 404. The stored instructions are read out in order and applied to an instruction decoder 405 for decoding. The decoded instruction is sent via the bus 407 to the data memory 408 or the arithmetic unit 40 in accordance with the contents.
9, register 410, input buffer 403, output buffer 41
Exchange data with 1. The data for which the operation has been completed is sent to the output buffer 411 and output as signals from the output terminals 412 and 413, or stored in the data memory 408.

A signal is periodically provided from the timer 406 to the instruction decoder 405 to interrupt the execution of the program in the instruction decoder 405. When an interrupt is issued, the instruction decoder 405 starts processing a predetermined program. The program executed by this interrupt is called an interrupt service routine (ISR). When decoding multiple input streams, D
Programs for processing the respective streams executed by the SP are temporally switched by the interruption by the timer, and are executed in parallel. That is, multitask processing is performed.

FIG. 3 shows a flowchart of a program processed by the DSP. Here, one task
100 is a decoding process for the first input stream,
Another task 300 is a decoding process for the second input stream. These decoding processes are executed while being alternately switched in time by the task switching process 200.

FIG. 1 shows the flow of the decoding process in the circuit of FIG. 2 (that is, the content of the MPEG decoding process in FIG. 3). As described above, the MPEG decoding process is performed in the MPEG2 video layer (MPEG2 Video Layer).
r) (sequence layer processing 101, GO
P layer processing 103, picture layer processing 105, slice layer processing 107, macroblock layer processing 109, and block layer processing 111). The processing 111 of the block layer is performed in the processing 109 of the macroblock layer, the processing 109 of the macroblock layer is performed in the processing 107 of the slice layer, and the processing 107 of the slice layer is performed in the processing 10 of the picture layer.
5, the processing 105 of the picture layer is performed in the processing 103 of the GOP layer. The processing 103 of the GOP layer is performed in the processing 101 of the sequence layer. However, GOP
There may be no layer. In FIG. 1, as compared with the flowchart of FIG. 12, judgment processing 102, 104, 106 for task switching is performed between the processing 101, 103, 105, 107, 109, 111 of each layer defined by the MPEG video layer. , 108,
It is characterized by the point that 110 is provided.

FIG. 4 shows a first embodiment of the task switching determination process in FIG.

FIG. 4 shows that an interrupt is permitted in step 501 and then disabled in step 502. No interrupt is accepted outside this period. timer
The interrupt signal from 406 is processed by the processing 10 defined by MPEG.
1, 103, 105, 107, 109, 111 are not accepted during the processing, and the task switching determination processing 102, 104, 106,
Accepted only during the execution period of 108 and 110. A task switching determination process 102 at the break of each of the sequence layer process 101, the GOP layer process 103, the picture layer process 105, the slice layer process 107, the macroblock layer process 109, and the block layer process 111; 104, 106, 108, 11
0 can be entered, and when there is an interrupt from the timer 406, the processing shifts to the task switching processing 200.

FIG. 5 shows a second embodiment of the task switching judgment processing. In this embodiment, an interrupt is directly generated as in step 601 without using the interrupt by the timer 406. By doing so, the process is forcibly shifted to the task switching process 200.

In another embodiment, a task switching process is forcibly performed by using a jump instruction.
The process may shift to 0.

Further, a multitask OS (so-called OS)
/ 2, Macintosh OS, Windows, UNIX, etc.), in the task switching judgment process, the process is similarly transferred to the task switching process 200 by calling a task scheduling function such as outputting a message. be able to.

FIG. 6 shows the contents of the task switching processing 200 in FIGS. 1 and 3. Task switching processing 20
In step 0, the task to be switched is determined in step 201, and the process jumps to the next task in step 202. In the embodiment of the present invention, at the time of this task switching, since the processing for each layer specific to the MPEG processing has been completed, there is no information to be saved in the register 410 in the task switching processing. Therefore, there is no need to save the contents of the register 410 in the data memory 408, and
There is no need to restore data from the data memory 408 to the register 410.

FIG. 7 is a view for explaining the flow of processing when task switching occurs in the stage preceding the processing 111 of the block layer in FIG.

When the processing 111-1 of the task 1 is started, the possibility of the task switching is determined here by the task switching determination 11
Judge by 0-1. At this point, the operation has not been started, and the result of the operation is not yet in the register 410. If task switching occurs here, step 201
The task to be switched is determined by using, and in step 202, the process jumps to the next task. The processing 311-1 of the block layer is started from the jump destination.

In step 311-11, the position of the data in the data memory 408 is determined. 8x8 IDCT from there
The coefficients are read (step 311-12). Thereafter, an IDCT operation 311-13 is performed. 8 × 8 IDCT operation is performed and 8 × 8
Is stored in the data memory 408 (step 31).
1-14). Then, the extent to which the processing has been performed, that is, the next processing start position is stored (evacuated) in the data memory 408.

Therefore, the possibility of the task switching is determined again by the task switching determination 310-1. If the task switching occurs, the task to be switched is determined in step 201, and the process jumps to the next task in step 202. The processing 111-1 of the block layer is started from the jump destination. Thereafter, steps 111-11 to 111-15 are executed in the same manner as described above.

In the embodiment shown in FIG. 1, the processing 101, 103, 105, 107, 109, 109 of each layer of the sequence layer, the GOP layer, the picture layer, the slice layer, the macro block layer, and the block layer specified by the MPEG2 video layer is performed. During 111, judgment processing 102, 104, 106, 108 for task switching
, 110, the task switching timing can be adjusted to the processing unit of each layer. Since the processing in each layer unit is completed at the time of task switching,
The necessity of saving the register can be almost eliminated.

By the way, the MPEG2 system layer (MP
EG2 System Layer) defines a method of packetizing a plurality of video streams and multiplexing them into one transport stream. Here, the packet of each video stream multiplexed into one transport stream is
It is called a transport packet (TS packet for short).

FIG. 8 shows the data structure of an MPEG2 transport packet. The TS packet has a 4-byte header part, in which the PID (packet ID)
Indicates what the packet is. In the decoding of the system layer in the MPEG decoding processing circuit, a PID is taken out, a value is determined to determine what packet it is, and if the packet is video data to be decoded, the packet is extracted. Transfer to 1
As for the number of video streams that can be multiplexed into one transport stream, for example, if the bit rate of the transport stream is 40 Mb / s and the bit rate of the video bit stream is 6 Mb / s, six video streams can be transmitted.
Furthermore, if you want to transmit many video streams,
It is necessary to use multiple transport streams.
In order to decode a plurality of video streams in different transport streams, it is necessary to be able to receive a plurality of transport streams.

FIG. 9 shows a flowchart in the case where a plurality of transport streams are processed by the DSP.
Here, one task 700 is a decoding process for the first transport stream, and another task 90 is a decoding process for the first transport stream.
0 is a decoding process for the second transport stream. These decoding processes are executed while being alternately temporally switched by the task switching process 800.

FIG. 10 is a view for explaining the flow of processing when task switching occurs in the preceding stage of the processing of the TS packet of the transport stream in FIG. In the present embodiment, the processing unit defined by MPEG2 is MPEG
This is a TS packet defined by two system layers.

In the process 711-1 of the task 1, the process of the transport stream 1 is performed. In the process 111-1 of the task 2, the transport stream 2 is processed. First, when the process 711-1 of the task 1 is started, the possibility of the task being switched is determined by the task switching determination 710-1. At this time, the operation has not been started, and the result of the operation is not yet in the register. If the task switching occurs, the task to be switched is determined in step 801 and the process jumps to the next task in step 802. Processing 91-1 of the TS packet of the transport stream 2 is started from the jump destination. When the processing of the packet is started, the PID is extracted from the header of the bucket (step 911-11). Then, the value of the PID is determined (step 911-12). If it is determined that the video data to be acquired is included, the data is transferred to the video decoder (step 911-13), and the packet processing is performed. Is completed, and the flow returns to step 910-1 to determine whether to switch tasks.

If task switching occurs again,
In step 801, a task to be switched is requested.
To jump to the next task. Processing of TS packet of transport stream 1 from the jump destination
Is started. Thereafter, in the same manner as described above, step 711-
11 to Step 711-13 are executed.

If the task switching timing is not matched to the processing unit of each TS packet as in the embodiment of the invention shown in FIG. 10, the task may be switched during packet processing as in the conventional example. In such a case, the acquired PID, the PID determination result, and the like are present in the register, and these need to be saved and restored at the time of task switching, which increases the overhead time associated with task switching.

According to the embodiment of the present invention described above,
Switching of a plurality of program tasks is performed at the timing of a processing unit defined by MPEG, so that task switching does not occur while valid data exists in the register.
Therefore, the time required for saving and restoring the register data can be almost eliminated. There is no dead time in task switching, the load on the DSP is reduced, and a faster program operation is possible. Further, there is an advantage that it is not necessary to request high performance from the DSP.

The present invention is not limited to a digital broadcast receiving apparatus, but can be applied to various video equipment, broadcast equipment, communication equipment, and recording / reproducing equipment using the MPEG system.

[0047]

As described above, according to the present invention, it is possible to reduce the time required for task switching processing. Even with the same hardware, more processing can be executed, and the load on the DSP is reduced.
It is no longer necessary to request high performance.

[Brief description of the drawings]

FIG. 1 is a flowchart showing MPEG decoding processing according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an MPEG decoding processing circuit using a DSP in the digital broadcast receiving apparatus.

FIG. 3 is a flowchart of a program processed by the DSP in FIGS. 1 and 2;

FIG. 4 is a flowchart showing a first embodiment of a task switching determination process in FIG. 1;

FIG. 5 is a flowchart showing a second embodiment of the task switching determination process in FIG. 1;

FIG. 6 is a flowchart showing the contents of a task switching process in FIG. 1;

FIG. 7 is a view for explaining the flow of processing when task switching occurs in a stage prior to the processing of the block layer in FIG. 1;

FIG. 8 is a diagram showing a data structure of an MPEG2 transport packet.

FIG. 9 is a flowchart for processing a plurality of transport streams by a DSP according to another embodiment of the present invention.

10 is an exemplary view for explaining the flow of processing when task switching has occurred in the first stage of processing of TS packets of the transport stream in FIG. 9;

FIG. 11 is a flowchart of a program processed by a conventional DSP.

FIG. 12 is a flowchart showing the contents of a decoding process in FIG. 11;

FIG. 13 is a flowchart showing a conventional task switching process.

[Explanation of symbols]

101: processing of sequence layer, 103: processing of GOP layer, 105: processing of picture layer, 107: processing of slice layer, 109: processing of macroblock layer, 111: processing of block layer, 102, 104, 106, 108 , 11
0: task switching determination processing, 200: task switching processing, 400: MPEG decoding processing circuit.

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[Procedure amendment]

[Submission date] February 12, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 11

FIG. 13

FIG. 10

FIG.

Claims (2)

[Claims] 1. A decoding processing circuit for decoding a plurality of video and audio streams encoded by the MPEG system, wherein the signal processing is executed while switching a plurality of program tasks for decoding the plurality of streams, respectively. In this case, the switching of the plurality of program tasks is performed at a timing for each processing unit specified by MPEG. 2. The decoding circuit according to claim 1, wherein the processing unit defined by the MPEG is MPEG2.
Blocks, macroblocks,
A decoding processing circuit, which is a slice, a picture, a GOP, a sequence, or a transport packet defined by an MPEG2 system layer.