JPH11259040A - Driving method of plasma display panel - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent deterioration of image quality due to all resets for simultaneously resetting all cells of a plasma display panel. SOLUTION: A field is divided into a plurality of subfields, and the subfield is composed of a reset period, an address period and a sustain discharge period, and a reset period in at least one subfield in one field is set to all cells. The entire reset period is set to reset simultaneously, and the other reset periods are set to reset only cells sustained and discharged in the immediately preceding sustain discharge period. In such whole reset period, the high voltage, all the reset pulse P _R of the wide pulse width reset of all cells are simultaneously applied to all the X electrodes is carried out, just before the full reset pulse P _R, sustain discharge pulses P simultaneously applying a fine line erasing pulse P _E of approximately equal amplitude a and 1μsec about pulse width _S to all X electrodes,
The wall charges of the sustained cells are erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device such as a personal computer or a workstation,
The present invention relates to a driving method of a plasma display panel used for a flat wall-mounted television, a display device for advertising, information, and the like.

[0002]

2. Description of the Related Art FIG. 2 is an exploded perspective view showing a part of the structure of an AC type plasma display panel.

In FIG. 1, on a lower surface of a front glass substrate 2 of a plasma display panel 1, X transparent electrodes 3a and Y transparent electrodes 4a are provided in parallel and alternately arranged. Also, X is applied to each of the electrodes 3a and 4a.
The bus electrode 3b and the Y bus electrode 4b are stacked. The X transparent electrode 3a and the X bus electrode 3b constitute the X electrode 3, and the Y transparent electrode 4a and the Y bus electrode 4b constitute the Y electrode 4. Further, on the lower surface, these electrodes 3, 4
To cover the dielectric layer 5 and the protective layer 6 such as MgO.
Are provided.

On the other hand, on the upper surface of the rear glass substrate 7 of the plasma display panel 1, address electrodes 8 extending in a direction perpendicular to the X electrodes 3 and the Y electrodes 4 of the front glass substrate 2 are provided. This address electrode 8 serves as a dielectric layer 9
And a partition wall 1 is provided for each space between the address electrodes 8 thereon.
0 is provided in parallel with the address electrode 8. further,
On the surface of the dielectric layer 9 on the partition 10 and the address electrode 8,
The phosphor 11 is applied.

FIG. 3 is a sectional view showing one cell portion of the plasma display panel 1 as seen from the direction of arrow A in FIG. In the figure, the address electrode 8 is located in the middle of two adjacent partitions 10. Further, Ne, Ne is provided in the space 12 between the front glass substrate 2 and the rear glass substrate 7.
It is filled with a discharge gas such as Xe.

FIG. 4 is a sectional view showing three cell portions of the plasma display panel 1 as viewed from the direction of arrow B in FIG. In the figure, the boundary of one cell is a position indicated by a substantially dotted line, and X electrodes 3 and Y electrodes 4 are alternately arranged. In the AC type plasma display panel 1, the dielectric layer 5 (the protective layer 6) near the X electrode 3 and the Y electrode 4 is provided.
And positive and negative charges are collected separately, and an electric field for discharging is formed using the charges. Such charges are called wall charges.

FIG. 5 is a schematic diagram showing the wiring and circuit configuration of the X electrode 3, Y electrode 4 and address electrode 8 described above.

In FIG. 1, an X drive circuit 13 is connected to each of the X electrodes 3 or a plurality of X electrodes, and generates a drive pulse to be applied. The Y drive circuit 14
Each of the electrodes 4 is connected to generate a drive pulse to be applied to each of the Y electrodes 4. The A drive circuits 15 and 16 are connected to each of the address electrodes 8 and generate drive pulses to be applied to each of the address electrodes 8.

In a plasma display device having such a plasma display panel, one field (one screen) is divided into a plurality of subfields on a time axis for each luminance, and each pixel (cell) is divided into the subfields. Light is emitted by generating ultraviolet light by discharge within the period to excite the phosphor. This discharge is called a sustain discharge.For example, as disclosed in Japanese Patent Application Laid-Open No. 4-195188, by changing the number of discharges for each subfield, halftones corresponding to the number of discharges in the field period are generated. The display is performed. In addition, at the beginning of each subfield, write discharge and erasure are performed only in the cells having the stored charged particles in order to erase the stored charged particles in the discharge region (cell) due to the sustain discharge performed in the immediately preceding subfield. Selective reset for performing discharge, or write discharge and self-erase discharge are performed for all cells in the plasma display panel regardless of the presence or absence of accumulated charged particles (this is referred to as "all reset").

[0010] Figure 6 is a diagram showing the structure of a subfield, as shown, each subfield SF is the above l reset period T _R (total reset period T _RA or selective reset period T _RS), It comprises an address period T _A for selecting a cell for sustain discharge (light emission) and a sustain discharge period T _S.

By the way, if the subfield SF is configured as shown in FIG. 6, all resets are performed for each subfield, and the cell emits light with the writing discharge and the self-erasing discharge in the full reset. Become. Since this light emission occurs in all the cells regardless of the presence or absence of the video signal, the brightness of the black level is increased and the contrast is deteriorated.

On the other hand, for example, as described in Japanese Patent Application Laid-Open No. 8-278766, a reset period is provided for each subfield, but in a reset period of one of the subfields constituting one field, Perform a full reset for writing discharge and self-erasing discharge of all cells, and in the reset period of other subfields, lower the voltage value of the reset pulse or narrow the pulse width to maintain it in the immediately preceding subfield. There is known a driving method in which a writing discharge and a self-erasing discharge are performed only on a discharged cell.

According to this, in each cell, after the subfield in which the sustain discharge is not performed, the write discharge and the self-erasing discharge are not performed, so that it is possible to reduce the invalid light emission which does not contribute to the luminance of the image. It is said that contrast and color reproducibility can be improved. This is called a selective reset.

[0014]

As described above, according to the driving method in which all resets are performed only once in one field, the number of times of invalid light emission is reduced and the contrast and the like can be improved. However, there is the following problem in the case of this full reset.

That is, when the sustain discharge period ends,
Since there is a difference in the amount of wall charges formed between the cell in which the sustain discharge has been performed in the period and the cell in which the sustain discharge has not been performed, the sustain discharge period ends and the head of the next subfield starts. When all resets are performed in step (1), it means that a difference in the amount of wall charges has occurred between cells.

When a full reset is performed in such a state, in a cell in which a sustain discharge is performed in the immediately preceding sustain discharge period and a large amount of wall charge is formed, a voltage corresponding to this wall charge amount is included in the total reset pulse. In a cell in which a strong write discharge is performed at a high voltage to which the voltage is applied and a wall discharge amount is small because the sustain discharge is not performed in the immediately preceding sustain discharge period, a voltage corresponding to the small wall charge amount is applied to all reset pulses. A weak write discharge is performed at a low voltage. In addition, a difference occurs in the amount of wall charges formed by writing discharge in these cells, so that uniform resetting over all cells cannot be performed.
The strength of the self-erasing discharge also differs depending on the amount of the formed wall charges.

As described above, when the intensity of the total reset discharge differs for each cell, the intensity of the invalid light emission generated for each cell also varies accordingly, and this appears as noise on the display screen and the image quality becomes poor. It will cause deterioration.

An object of the present invention is to solve such a problem, to make the reset state during all reset periods uniform for all cells, and to suppress the deterioration of image quality due to all reset. It is to provide a driving method.

[0019]

In order to achieve the above object, the present invention provides an erasing pulse having a pulse width and amplitude that does not cause wall charges only immediately before all reset pulses.

In the cell in which the sustain discharge has been performed in the discharge sustain period immediately before the reset period in which all resets are performed, wall charges are formed by the sustain discharge. Is done. Further, in the cell in which the sustain discharge was not performed in the immediately preceding sustain discharge period, almost no wall charge is formed, so that the discharge by the erase pulse is not performed, and no wall charge is generated. Therefore, when reset is performed by all reset pulses, discharge is performed with almost the same intensity in all cells.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing a main part of an embodiment of a driving method of a plasma display panel according to the present invention.

As in the prior art described above, also in this embodiment, one field is divided into a plurality of (for example, eight) subfields, and each subfield SF is
As shown in FIG. 6, and a reset period T _R and the address period T _A and the sustain discharge period T _S. And, in each field, the reset period T _R of at least one sub-field is assumed to reset all of the cells on the plasma display panel at the same time (hereinafter referred to as the total reset period T _RA). In the reset period of the other sub-fields, only the cells that have undergone the sustain discharge in the immediately preceding sustain discharge period are reset, as in the driving method described in JP-A-8-278766 (hereinafter, referred to as
This is called a selective reset period _TRS ). In this entire reset period T _RA , a high voltage, wide pulse width reset pulse (hereinafter, referred to as a high voltage) having a pulse width of about 6 to 10 μsec at about 350 V
All reset pulses) are applied to all the X electrodes at the same time, whereby a write discharge and a self-erase discharge are performed in all the cells.

In this embodiment, as shown in FIG.
A sustain discharge period T _S in which a discharge sustain pulse R _S is alternately applied to the electrode 3 and the Y electrode 4 to discharge and emit light from the selected cell.
There ends and the next reset period T _R is assumed to be the total reset period, before the entire reset pulse P _R is simultaneously applied to all the X electrodes, fine line erasing pulse P _E is applied to all the X electrodes at the same time You.

The thin line erase pulse P _E is a pulse that does not cause wall charge in the cell and discharges the charge formed in the cell. The amplitude of the pulse is equal to the amplitude of the total reset pulse P _R. sufficiently lower than about 350 V), for example, a substantially equal amplitude (160~180V) of the sustain discharge pulses P _S, also the pulse width, the total reset pulse P _R of the pulse width (6~10μsec) It is much narrower than that, for example, about 1 μsec.

In the cell in which the wall discharge is formed by the sustain discharge (light emission) in the immediately preceding sustain discharge period T _S by the thin line erase pulse P _E , discharge is performed by the wall charge and the discharge current i _D Flows, and this wall charge is erased.
In the cells in which the sustain discharge has not been performed during the sustain discharge period T _S , the wall charges are hardly formed, so that the discharge is not performed, and the state without the wall charges is maintained. In this way, all cells have a uniform wall charge.

In such a state, all the reset pulses P _R
When the write discharge is performed simultaneously for all the cells, the discharge intensity becomes almost uniform over all the cells, and thus the invalid light emission becomes almost uniform over all the cells, so that no noise is generated on the display screen. In addition, since the amount of wall charges formed by the writing discharge becomes almost uniform over all cells, the invalid light emission due to the self-erasing discharge also becomes uniform over all cells, and no noise is generated on the display screen. Further, since the state of the wall charges after the self-erasing discharge is also substantially uniform in all the cells, malfunctions in the subsequent address period and discharge sustaining period are reduced. In this way, it is possible to prevent the image quality from deteriorating due to the full reset.

It should be noted that, in the present invention, the above-mentioned Japanese Unexamined Patent Publication No.
In the case where the reset period in the first subfield of the field is defined as the entire reset period as described in Japanese Patent No. 78766, the above-described fine line erase pulse _PE is added immediately before the entire reset pulse in the entire reset period. Although
The present invention is not limited to this, and the thin line erase pulse is added to the entire reset period, as described above, even if the entire reset period is set in any subfield in the field.

The numerical values shown in the above embodiment are merely examples, and the present invention is not limited to such numerical values.

[0029]

As described above, according to the present invention,
Regardless of whether or not the sustain discharge was performed during the sustain discharge period, the wall charge amount can be made uniform in all cells immediately before all the reset pulses, so that the discharge intensity by all the reset pulses is almost uniform over all the cells. Thus, the deterioration of the image quality due to the full reset can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of a driving method of a plasma display panel according to the present invention.

FIG. 2 is an exploded perspective view showing a part of the structure of the AC type plasma display panel.

FIG. 3 is a cross-sectional view showing one cell portion of the plasma display panel viewed from the direction of arrow A in FIG.

FIG. 4 is a cross-sectional view showing three cell portions of the plasma display panel viewed from the direction of arrow B in FIG.

FIG. 5 is a diagram schematically showing an arrangement relationship of respective electrodes in an AC type plasma display panel.

FIG. 6 is a diagram showing a configuration of a subfield in a field for driving an AC plasma display panel.

[Explanation of symbols]

1 a plasma display panel 2 front glass substrate 3 X electrode 4 Y electrodes 9 rear glass substrate 10 address electrode 12 barrier rib 13 fluorescers P _S sustain discharge pulse P _E fine line erasing pulse P _R total reset pulse

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Takeo Masuda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Hitachi, Ltd. Information Media Business Unit

Claims (2)

[Claims] 1. One field is divided into a plurality of subfields, each subfield is composed of a reset period, an address period, and a sustain discharge period, and the reset period in at least one subfield of one field In a driving method of a plasma display panel in which all cells are simultaneously reset by all reset pulses, wherein the pulse width and amplitude are such that wall charges are not generated immediately before the all reset pulses in the all reset period. A driving method for a plasma display panel, comprising the steps of: 2. The plasma according to claim 1, wherein the erase pulse is a thin line pulse having an amplitude substantially equal to the sustain discharge pulse in the sustain discharge period and having a pulse width narrower than the sustain discharge pulse. Display panel driving method.