JPH11266239A - Clock synchronization delay control circuit - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To extend the operating frequency range. A pulse start from a delay monitor is provided.
Propagates through the forward pulse delay line 6. Pulse START
A pulse is output from the backward pulse delay line 7 after the same time as the signal has propagated through the forward pulse delay line 6, and is output as the internal clock INTCLK via the pulse width restoration circuit 8 and the clock delivery 9. Pulse detection circuit 13
Detects whether the pulse START has propagated to the Nth stage. When the pulse START propagates to the N-th stage, the pulse detection circuit 13 generates a detection signal for setting the delay time of the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9 for low frequency. Output Dctl. Thereby, the frequency band can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization delay control circuit suitable for controlling synchronization using a high-speed clock.

[0002]

2. Description of the Related Art In recent years, in a computer system, a clock synchronous type memory such as a synchronous DRAM has been sometimes employed due to a demand for high-speed processing. The synchronous memory uses a clock synchronized with a clock for controlling the memory circuit in the memory.

When a delay occurs between a clock used in the memory (hereinafter referred to as an internal clock) and an external clock such as a clock for controlling a memory circuit, the delay amount becomes small especially when the operation speed is high. However, the malfunction of the circuit is likely to occur.

Therefore, a clock synchronization delay control circuit for synchronizing an internal clock with an external clock is provided in a semiconductor integrated circuit.

FIG. 23 is a block diagram showing a conventional clock synchronization delay control circuit proposed in Japanese Patent Application No. 9-182634 previously filed by the present applicant.

The input terminal 1 has an external clock EXTCLK
Is entered. This external clock EXTCLK is taken in via the receiver 162. A delay is caused by the receiver 162 during this capture. Further, the receiver 1
The output of 62 is the pulse generation circuit 163 and the delay monitor 1
65, forward pulse delay line 6, backward pulse delay line 7,
It is output as an internal clock INTCLK via a pulse width restoration circuit 168 and a clock delivery 169. These circuits also cause a delay.

The circuit shown in FIG. 23 has an external clock EXTCLK.
Is set to τ, and the total of the delay times of the respective circuits is made an integral multiple of τ, thereby obtaining the internal clock INTCLK synchronized with the external clock EXTCLK.

Now, the delay time of the receiver 162 is set to Δtrec
And the delay time of the clock deliver 169 is Δtdeli. Further, the delay time of the pulse generation circuit 163 and the pulse width restoration circuit 168 is represented by τd. These delay times are known, and if the delay time Δtmon of the delay monitor 165 is set to Δtmon = Δtrec + Δtdeli, the delay amount excluding the forward pulse delay line 6 and the backward pulse delay line 7 becomes Δtrec
+ 2τd + Δtmon + Δtdeli = 2 (Δtmon + τd).

Therefore, the delay amount of the sum of the forward pulse delay line 6 and the backward pulse delay line 7 is 2 ｛τ− (Δtmon + τ
d) By setting ＩＮ, the internal clock INTCLK synchronized with a delay of 2τ with respect to the external clock EXTCLK
Can be generated.

FIG. 24 is a waveform chart for explaining the operation of such a conventional clock synchronous delay control circuit.

The input terminal 1 has a period of τ and a duty of 5
A 0% external clock EXTCLK (FIG. 24A) is input. This external clock EXTCLK is supplied to the receiver 1
24, and is delayed as Δtrec and output as a clock CLK, as shown in FIG. This clock CLK is supplied to the pulse generation circuit 163 and the control signal generation circuit 4. The control signal generation circuit 4
As shown in (c), a control signal STOP obtained by inverting the input clock CLK is output.

FIG. 25 shows a pulse generation circuit 163 in FIG.
FIG. 2 is a circuit diagram showing a specific configuration of FIG.

The pulse generation circuit 163 includes a pulse width adjustment delay circuit 52 and an AND circuit 53. The pulse width adjusting delay circuit 52 delays the clock CLK input via the terminal 51 by τd and supplies the clock CLK to the AND circuit 53. This causes the AND circuit 53 to generate a pulse A that rises with a delay of τd from the rise of the clock CLK and falls at the fall of the clock CLK.
(FIG. 24D) is obtained. That is, the pulse width α of the pulse A is smaller than the pulse width of the external clock EXTCLK, and is τ−2−τd.

The pulse A is supplied to the delay monitor 165 and is delayed by Δtmon, and thereafter, the pulse START (FIG. 2)
4 (e)) is supplied to the forward pulse delay line 6.

FIG. 26 shows a delay line 6 for a forward pulse shown in FIG.
3 is a circuit diagram showing a specific configuration of a backward pulse delay line 7. FIG. The forward-pulse delay line 6 and the backward-pulse delay line 7 include 1 to L-stage unit delay elements 11-1 to 11-L, 1
It is composed of 2-1 to 12-L. Each unit delay element is connected to a clocked inverter 31 as shown in FIG.
It is constituted by. By cascading the unit delay elements by the clocked inverter 31, the forward pulse delay line 6 and the backward pulse delay line 7 are configured.

The output terminal of the unit delay element 11 at each stage of the forward pulse unit delay line 6 is connected to the input terminal of the unit delay element 12 at each stage of the backward pulse unit delay line 7. The clocked inverter 31 of the forward pulse unit delay line 6 is controlled by the control signal STOP, and the clocked inverter 31 of the backward pulse unit delay line 7 is controlled by the clock CLK.

When the control signal STOP is at a high level (hereinafter, referred to as
"H"), the forward pulse unit delay line 6
Are in a conductive state, and the pulse START input to the first-stage inverter 31 sequentially propagates through the second-stage inverter 31. During the “H” period of the control signal STOP, since the clock CLK is at a low level (hereinafter, referred to as “L”), each clocked inverter 31 of the backward pulse delay line 7 does not propagate a signal. Pulse START
Is narrow and the clock CLK is input during the period of "L", so that the pulse START rises and the delay line 6 for the forward pulse continues until the next clock CLK becomes "H".
To propagate.

During the period when the control signal STOP is "H", at the stage where the pulse START is not propagated, that is, at the stage where the rising edge of the pulse START has not reached, the output becomes "H" or "L". Fixed. Since the unit delay element is constituted by an inverter, the outputs of adjacent stages have different logic levels. When the edge portion of the pulse START propagates, the stage converts the output to a different logic level and maintains that level for a period corresponding to the pulse width of the pulse START. When the falling edge of the pulse START passes, the output of the stage returns to the original logic level.

When the control signal STOP becomes "L" and the clock CLK becomes "H", the propagation of the pulse START is stopped, and each clocked inverter 31 of the backward pulse delay line 7 starts to propagate.

Each inverter 31 of the forward pulse delay line 6
Is supplied as an input to each inverter of the backward pulse delay line 7, and if the rising edge of the pulse START has propagated to the Nth stage, the output corresponding to this edge is the output of the backward pulse delay line 7. It appears at the input terminal of N stages. The output corresponding to the rising edge portion is transmitted through the backward pulse delay line 7 to the first stage by N stages and output.

Accordingly, the time when the rise of the pulse START propagates through the forward pulse delay line 6 is equal to the time when the pulse input to the backward pulse delay line 7 propagates through the backward pulse delay line 7. As shown in FIG.
TART is from the output of the delay monitor 165 to the time when the control signal becomes “L”, that is, τ− (τd + Δtmon)
And then propagates through the backward pulse delay line 7 for the same amount of time. Thus, from the backward pulse delay line 7, FIG.
The pulse OUT shown in FIG. 4 (f) is output.

The pulse OUT is supplied to a pulse width restoration circuit 168. FIG. 27 shows the pulse width restoration circuit 16 in FIG.
8 is a circuit diagram showing a specific configuration of FIG.

The pulse width restoring circuit 168 comprises a delay circuit 72, NOR circuits 73 and 78, inverters 74 and 76, and nMOS transistors 57 and 77, as shown in FIG. The delay time of the delay circuit 72 is τd. The terminal 71 receives a pulse OUT having a pulse width α. The delay circuit 72 delays the pulse OUT input via the terminal 71 by τd and outputs the delayed pulse OUT.

When the pulse OUT from the terminal 71 becomes "H", the OR circuit 73, 78 causes the terminal 79 to become "H". Before the pulse OUT becomes “L” after the time α, the transistor 77 is turned on by the “H” of the pulse OUT, and the output of the inverter 76 becomes “H”. As a result, even if the pulse OUT becomes “L” after the time α, the terminal 79 maintains “H”.

After a time τd from the rise of the pulse OUT, the output of the delay circuit 72 becomes “H”. This allows
The transistor 75 conducts, and the output of the inverter 76 becomes "L". However, during the time α after the output of the delay circuit 72 rises, the output of the delay circuit 72 is “H”, and the terminal 79 maintains “H” during this time. After all, terminal 7
9 rises at the rise of the pulse OUT, and the pulse width is τd + α = pulse C having the pulse width of the clock CLK.
(FIG. 24 (g)) is obtained.

The delay circuits 52, 52 in FIGS.
For example, the circuit shown in FIGS. 31A and 31B is used as 72. The circuit shown in FIG.
2 are cascaded, and the circuit shown in FIG. 31B is configured by cascade-connecting a circuit including a resistor 66 and a capacitor 65.

Pulse C from pulse width restoration circuit 168
Is the clock delivery 16 as shown in FIG.
9, the internal clock INT is delayed by Δtdeli.
CLK (FIG. 24 (i)).

Since the delay time Δtmon of the delay monitor 165 is designed to be equal to the sum Δtrec + Δtdeli of the delay times of the receiver 162 and the clock delivery 169, the total delay Δtotal of the internal clock INTCLK with respect to the external clock EXTCLK is , Represented by the following equation (1).

Δtotal = Δtrec + τd + Δtmon + 2 ｛τ− (τd + Δtmon)｝ + τd + Δtdeli = 2τ (1) As shown in the equation (1), the internal clock INTCLK is synchronized with the external clock EXTCLK with a delay of two cycles.

Next, the pulse propagation operation of the forward pulse delay line 6 and the backward pulse delay line 7 will be described in more detail with reference to the operation waveform diagram of FIG.

The output signal CLK of the receiver 162 is pulsed by the pulse generation circuit 163, and the pulse STAR
T is supplied to the forward pulse delay line 6 as T. Pulse S
When TART propagates to the L-stage unit delay element 11-L, the operation waveforms of the (N-1) -th, N-th and L-th stages are shown in FIG.
(E), (f), and (g).

The unit delay element is a clocked inverter 31
, The output D (N
-1) and D (N) are mutually inverted as shown in FIGS. 28 (e) and (f). When the pulse propagates, the unit delay element of the (N-1) th stage outputs a positive pulse, and the unit delay element of the Nth stage outputs a negative pulse. Also, the clock CL
When K is "H", the pulse propagates through the forward pulse delay line 6, and in the backward pulse delay line 7, the pulse propagates when the control signal STOP is "H" (CLK is "L").
Output terminal of unit delay element 11 forming forward pulse delay line 6 and unit delay element 1 forming backward pulse delay line 7
28 (f), the pulse 1 of the output D (N) is a pulse that propagates through the forward pulse delay line 6, and the pulse 2 is the reverse pulse delay line 7 It is a propagating pulse.

In the circuit shown in FIG. 23, the pulse START is set to τd + Δtm at the rise of the clock CLK.
The forward-pulse delay line 6 is propagated only during the period from the ON state to the next rise of the clock CLK, and the pulse OUT is output from the backward-pulse delay line 7 at the same time after the end of the propagation, thereby achieving synchronization. Therefore, there is a disadvantage that the operating frequency band is limited.

Now, the period of the external clock EXTCLK is τ and the duty is 50%, and the period and the duty of the output signal CLK of the receiver 162 are the external clock EXT.
It is assumed that they are equal to the cycle and duty of CLK.

To establish synchronization, the pulse STA
The rising edge and the falling edge of RT need to propagate through the forward pulse delay line 6. As for the falling edge, the edge portion may be input to the forward pulse delay line 6 during the period of “L” of the clock CLK (“H” of the control signal STOP). FIG. 29 is a waveform chart showing the limit in this case.

As shown in FIG. 29C, the pulse STA
RT has a falling edge coincident with the rising edge of the clock CLK. That is, the limit is represented by the following equation (2).

[0037] That is, the above equation (2) indicates the upper limit of the frequency of the external clock EXTCLK.

As for the rising edge, the edge portion may be input to the forward pulse delay line 6 during the "L" period of the clock CLK ("H" of the control signal STOP). FIG. 30 is a waveform chart showing the limit in this case.

As shown in FIG. 30C, the pulse STA
RT has a rising edge coincident with the falling edge of the clock CLK. That is, the limit in this case is expressed by the following equation (3).

[0040] That is, the above equation (3) indicates the lower limit of the frequency of the external clock EXTCLK.

Since α = τ / 2−τd, the condition for generating the pulse A in the pulse generation circuit 163 is as follows. It is.

If the propagation of the pulse does not stop before the pulse START propagates to the last stage (L stage) of the forward pulse delay line 6, synchronization cannot be established, so that the unit delay elements 11 and 12 cannot be established. Let Δdu be the delay amount of
The following condition (5) is required.

Τ− (τd + Δtmon) ≦ LΔdu τ ≦ LΔdu + τd + Δtmon 1 / τ ≧ 1 / (LΔdu + τd + Δtmon) (5) Therefore, the frequency band f in the circuit of FIG. Can be expressed by the following equation (6).

Note that max {a, b} indicates the larger of a and b, and min {a, b} indicates the smaller of a and b.

Max {1/2 (τd + Δtmon), 1 / (LΔdu + τd + Δtmon) <f <min {1 / 2Δtmon, 1 / 2τd} (6) In the clock synchronous delay control circuit, the STBD (Synchron
ous Traced Backwards Delay), generally, the lower limit of the operating frequency band can be extended to the lower frequency side independently of the upper limit by increasing the number L of unit delay elements constituting the delay line. it can.

However, in the circuit shown in FIG. 23, as shown in the above equation (6), the lower limit of the operating frequency band is not equal to the delay line forming pulse generator 163 and the delay line forming pulse width restoring circuit 168. Since it depends on the delay time τd and the delay time Δtmon of the delay monitor 165, there is a disadvantage that the operating frequency band is narrower than other clock synchronous delay control circuits.

[0047]

As described above, in the above-described conventional clock synchronization delay control circuit, since the lower limit and the upper limit of the operating frequency band cannot be set independently, the operating frequency band is narrow. There was a problem.

It is an object of the present invention to provide a clock synchronous delay control circuit capable of expanding an operating frequency band by making it possible to switch a delay amount of a delay line in each section of the circuit.

[0049]

A clock synchronization delay control circuit according to the present invention comprises: input means for receiving and outputting an external clock; and a pulse signal having a width smaller than a half cycle of the external clock. Pulse generating means for generating a first pulse signal delayed by a first delay time with respect to an external clock from the input means; delay means for delaying and outputting the first pulse signal; The delay means is constituted by a plurality of unit delay elements.
Pulse signal is supplied to the first-stage unit delay element and propagates to the second-stage unit delay element, and propagation is stopped at a timing synchronized with the external clock from the input means to obtain an output indicating the number of propagated stages. And a plurality of cascade-connected unit delay elements, and the first pulse signal corresponds to the number of stages in which the first pulse signal has propagated through the forward-pulse delay line based on the output of the forward-pulse delay line. Propagating and outputting the pulse signal by the number of stages to be performed, the pulse signal is transmitted after the same time as the time when the first pulse signal has propagated through the forward pulse delay line from the stop of the propagation of the first pulse signal. A delay line for a backward pulse to be output and an edge of a pulse signal from the delay line for a backward pulse are delayed by the first delay time, thereby providing an external signal from the input means. A pulse width restoring means for restoring and outputting the same pulse width as the lock pulse width, and a delay time obtained by subtracting the delay time by the input means from the delay time by the delay means; Output means for delaying the output and outputting as an internal clock;
Pulse detection means for detecting the number of stages of unit delay elements of the forward pulse delay line through which the first pulse signal has propagated;
A delay time control means for controlling at least one of the first delay time and the delay time by the input means, the delay means and the output means based on the detection result of the pulse detection means.

In the present invention, the external clock is input through the input means, and the first pulse signal is generated from the output of the input means. After being delayed by the delay means, the first pulse signal is supplied to the forward pulse delay line and propagated. When the propagation stops, a pulse is output from the backward pulse delay line after the same time as the propagation time of the forward pulse delay line. This pulse is restored to the original pulse width by the pulse width restoring circuit and then output as an internal clock by the output means. The number of stages in which the first pulse signal has propagated through the forward-pulse delay line is detected by the pulse detection means. Based on the detection result, the first delay time and the delay time by the input means, the delay means, and the output means are determined. At least one is controlled. As a result, these circuits are set in accordance with the frequency of the external clock, and the operating frequency range is widened.

[0051]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a clock synchronization delay control circuit according to the present invention. In FIG. 1, the same components as those in FIG. 23 are denoted by the same reference numerals.

In this embodiment, the operating frequency band is expanded by making the delay time of each circuit variable.

The input terminal 1 has an external clock EXTCLK
Is entered. It is assumed that the period of the external clock is τ. The external clock EXTCLK is supplied to the receiver 2, and the receiver 2 outputs a clock CLK obtained by shaping the waveform of the external clock and amplifying it. In the present embodiment, the receiver 2 is controlled by a detection signal Dctl from a pulse detection circuit 13 described later, so that the delay amount changes.

FIG. 2 is a block diagram showing a specific configuration of the receiver 2 in FIG.

The input terminal 101 receives an external clock EXTCLK from the input terminal 1. Receive section 100
Has the same configuration as the receiver 162 in the conventional example, and forms and amplifies an external clock to output. The output of the receiving unit 100 is supplied to the delay circuit 102 and also to the multiplexer 103. The delay circuit 102 delays the input clock by a predetermined delay amount and outputs the delayed clock to the multiplexer 103. The multiplexer 103 selects one of the two inputs based on the detection signal Dctl and outputs it to the terminal 104 as a clock CLK. Assuming that the delay amount due to the receiving unit 100 is Δtrec and the delay amount due to the delay circuit 102 is Δtrec2, the delay amount from the terminal 104 with respect to the external clock EXTCLK is Δtrec or Δtrec + Δtrec2.
K is output.

The clock CLK from the receiver 2 is supplied to the pulse generation circuit 3, the control signal generation circuit 4, and the backward pulse delay line 7. The control signal generation circuit 4 generates a control signal STOP obtained by inverting the clock CLK and outputs the control signal STOP to the forward pulse delay line 6. The pulse generation circuit 3 delays the clock CLK by a predetermined delay amount and generates a pulse A that falls at the falling edge of the clock CLK. In the present embodiment, the pulse generation circuit 3 is controlled by the detection signal Dctl from the pulse detection circuit 13 so that the delay amount changes.

FIG. 3 is a block diagram showing a specific configuration of the pulse generation circuit 3 in FIG.

The input terminal 111 receives a clock CLK from the receiver 2. This clock CLK is supplied to the delay circuits 112 and 113 and the AND circuit 116.
The delay circuits 112 and 113 output the clock C
LK is delayed by τd-h or τd-l and output to the multiplexer 114. The multiplexer 114 has a terminal 115
And selects one of the two inputs based on the detection signal Dctl input through the AND circuit 116 and outputs it to the AND circuit 116. An AND circuit 116 performs an AND operation of two inputs and outputs an output terminal 117.
As a pulse A.

Therefore, the terminal 117 receives the clock CLK
Τd-h or τd-1 after the rise of the clock CLK, and a pulse appears at the fall of the clock CLK.

The pulse A from the pulse generation circuit 3 is supplied to the delay monitor 5. FIG. 4 is a block diagram showing a specific configuration of the delay monitor 5 in FIG.

The input terminal 121 receives a pulse A from the pulse generation circuit 3. This pulse A is applied to the delay unit 1
20. The delay unit 120 has the same configuration as the delay monitor 165 in the conventional example, and delays the input pulse A by Δtmon to form a multiplexer 123.
And to the delay circuit 122. The delay circuit 122 delays the input pulse A by Δtmon2 and outputs the same to the multiplexer 123. The multiplexer 123 selects one of the two inputs based on the detection signal Dctl from the pulse detection circuit 13 and outputs it to the terminal 125 as a pulse START. As a result, the pulse A appears at the terminal 125 with a delay of Δtmon or Δtmon + Δtmon2.

The output of the delay monitor 5 is supplied to a forward pulse delay line 6. The forward pulse delay line 6 is configured by cascading L unit delay elements 11 (unit delay elements 11-1 to 11-L) that operate with a predetermined delay time. Control signal S
By the “H” of the TOP, the output of the unit delay element 11 in the previous stage is propagated to the next stage. Control signal STO
When P is “L”, the pulse START is not propagated.

The backward pulse delay line 7 is provided with L unit delay elements 12 (unit delay elements 12) operating with a predetermined delay time.
-1 to 12-L) are connected in cascade, and each unit delay element 12 propagates the output of the subsequent unit delay element 12 to the previous stage by the "H" of the clock CLK. When the clock CLK is “L”, the pulse is not propagated in the backward pulse delay line 7.

The output terminals of the unit delay elements 11-1 to 11-L at each stage of the forward pulse delay line 6 are input to the unit delay elements 12-1 to 12-L of each stage of the backward pulse delay line 7, respectively. Connected to the end. As the forward pulse delay line 6 and the backward pulse delay line 7, a circuit using a clocked inverter can be used as in FIG.

The pulse START from the delay monitor 5
Propagates through each unit delay element 11 of the forward pulse delay line 6 during the “H” period of the control signal STOP. Control signal STO
P and the clock CLK are mutually inverted. When the control signal STOP becomes “L”, the propagation of the pulse in the forward pulse delay line 6 stops, and when the clock CLK becomes “H”, the forward pulse The pulse propagated to the delay line 6 for use appears on the delay line 7 for backward pulse and propagates to the preceding stage. The edge portion of the pulse propagates through the backward pulse delay line 7 for the same time as the propagation time through the forward pulse delay line 6 and is output as a pulse OUT from the unit delay element 12 at the first stage.

The output of the backward pulse delay line 7 is a pulse OU
T is supplied to the pulse width restoration circuit 8. FIG. 5 is a block diagram showing a specific configuration of the pulse width restoration circuit 8 in FIG.

The input terminal 131 receives a pulse OUT. The pulse OUT is supplied to the delay circuits 133 and 134, the OR circuit 137, and the gate of the nMOS transistor 132. Delay circuits 133, 13
Reference numeral 4 designates the input pulse OUT as τd-h or τd-l, respectively.
And outputs the result to the multiplexer 135. The multiplexer 135 selects one of the two inputs based on the detection signal Dctl input via the terminal 136, and outputs it to the OR circuit 137 and the gate of the nMOS transistor 138. The OR circuit 137 performs a two-input OR operation and outputs the operation result to the OR circuit 1311.

Source / gate paths of the transistors 138 and 132 are connected in series between the power supply terminal and the reference potential. The connection point of the transistors 138 and 132 is connected to the output terminal of the inverter 139 and the input terminal of the inverter 1310. Connected. The output terminal of the inverter 1310 is connected to the input terminal of the inverter 139 and the OR circuit 131
1 input terminal. The OR circuit 1311 performs a two-input OR operation, and outputs the operation result to the output terminal 1312 as a pulse C.

The pulse width restoring circuit 8 constructed as described above
In, a pulse OUT having a predetermined pulse width is input to the input terminal 131. In response to the detection signal Dctl input to the terminal 136, the multiplexer 135 causes the delay circuit 1
The output of the delay circuit that operates with the same delay amount as the delay amount τd-h or τd-l used in the pulse generation circuit 3 is selected from 33 and 134.

When the pulse OUT from the terminal 131 becomes “H”, the OR circuits 137 and 1311 cause the terminal 131
2 becomes "H". The pulse OUT becomes “L” after a predetermined time.
Before the pulse becomes “H”, the transistor 132 is turned on by the “H” of the pulse OUT, and the output of the inverter 1310 becomes “H”
Becomes Thus, even if the pulse OUT becomes “L” after a predetermined time, the terminal 1312 maintains “H”.

Time τd-h from the rise of pulse OUT
Or, after τd−1, the output of the multiplexer 135 becomes “H”.
Becomes As a result, the transistor 138 is turned on, and the output of the inverter 1310 becomes “L”. However, after the output of the multiplexer 135 rises, the pulse OU
The output of the multiplexer 135 is “H” during the time corresponding to the pulse width of T, and the terminal 1312 maintains “H” during this time. As a result, a pulse C having the same pulse width as the clock CLK is obtained from the terminal 1312 at the rising of the pulse OUT.

The pulse C from the pulse width restoration circuit 8 is given to the clock delivery 9. FIG. 6 is a block diagram showing a specific configuration of the clock deliver 9 in FIG.

The pulse C from the pulse width restoration circuit 8 is input to the input terminal 141. This pulse C is given to the output buffer 140. The output buffer 140 has the same configuration as the clock delivery in the conventional example. The output buffer 140 delays the input pulse C by Δtdeli,
2 and the multiplexer 143. Delay circuit 14
2 delays the output of the output buffer 140 by Δtdeli2 and outputs it to the multiplexer 143. One of the two inputs is selected based on the detection signal Dctl input via the multiplexer terminal 144 and is output to the output terminal 10 as the internal clock INTCLK. Therefore, the internal clock INTCLK outputs the pulse C by Δtdeli
Or it is delayed by Δtdeli + Δtdeli2. Δtmon = Δtrec + Δtdeli, Δtmon2 = Δtrec2 +
It is set to Δtdeli2.

The delay time of the delay monitor 5 is
The delay time is set to the sum of the delay time of the receiver 2 and the delay time of the clock delivery 9.

In this embodiment, the pulse detection circuit 13 detects whether the pulse START has propagated to a predetermined stage of the forward pulse delay line 6 and outputs a detection signal Dctl. I have.

FIG. 7 is a block diagram showing a specific configuration of the pulse detection circuit 13 in FIG.

The number of stages through which the pulse START propagates through the forward pulse delay line 6 and the backward pulse delay line 7 varies depending on the frequency of the external clock EXTCLK. When the frequency of the external clock EXTCLK is high (τ is small), the number of stages through which the pulse START propagates is small. When the frequency of the external clock EXTCLK is low (τ is large), the number of stages through which the pulse START propagates is large. In order to extend the operating frequency band to a lower band, it is necessary to increase the number of stages of the forward pulse delay line 6 and the backward pulse delay line 7.
However, when used in a high frequency band, the number of stages through which the pulse START propagates is small regardless of the number of stages of the forward pulse delay line 6 and the backward pulse delay line 7. Since the number of stages to be propagated depends on the operating frequency band, the pulse STA
The current operating frequency band can be ascertained by checking the number of stages through which the RT has propagated.

The pulse detection circuit 13 detects whether or not the pulse START has propagated to the N-th stage unit delay element 11-N. 7, the output pulse D (N) of the unit delay element 11-N of the Nth stage is input to the input terminal 41. This pulse D (N) is applied to flop flop 4
7 is supplied to one input terminal of a NAND circuit 42.

On the other hand, to the terminal 46, for example, a pulse signal generated only once when the power is turned on is input. The multiplexer 45 supplies "L" to one input terminal of the NAND circuit 44 only when a pulse is input from the terminal 46, and supplies "H" to one input terminal of the NAND circuit 44 in other cases. ing.

The flip-flop 47 is connected to the NAND circuit 42,
44, and the "L" level is applied to the NAND circuit 44.
Is applied, the output is reset to "L".
After "H" is input to the NAND circuit 44, the output of "H" is output after the pulse D (N) first becomes "L". Flip-flop 4
The output of the NAND circuit 42 is output from a terminal 43 as a detection signal Dctl.

The pulse detection circuit 13 configured as described above
In the case, when the pulse START propagates to N stages,
The pulse D (N) falls, and the detection signal Dctl becomes "H". Thereafter, the detection signal Dctl keeps "H" regardless of the change of the pulse D (N).

In the present embodiment, the detection signal D
Based on ctl, the delay times of the pulse generation circuit 3 and the pulse width restoration circuit 8 are commonly controlled, and the receiver 2,
The clock delivery 9 and the delay time of the delay monitor 5 are controlled in association with each other.

In FIG. 1, the detection signal Dctl is obtained by using the output pulse D (N) of the unit delay element 11 of the N-th stage.
Has been described above, the detection signal Dctl may be generated using a plurality of outputs of the unit delay elements in a plurality of stages.

Next, the operation of the embodiment thus configured will be described with reference to the operation waveform diagram of FIG. FIG. 8A shows the output pulse D of the unit delay element 11 at the Nth stage.
(N), and FIG. 8B shows the detection signal Dctl.

In the initial state, for example, settings are made for operation at high frequencies. That is, τd−h <τd
-l, the pulse generation circuit 3 and the pulse width restoration circuit 8
Is a delay circuit 11 that operates with a delay time τd-h.
2. It is assumed that the delay circuit 133 has been selected. In the initial state, the delay times of the receiver 2, the clock delivery 9, and the delay monitor 5 are set to be short. That is, the delay times of the receiver 2, the clock delivery 9, and the delay monitor 5 are Δtrec and Δtdeli, respectively.
, Δtmon, and Δtmon = Δtrec + Δtdeli.

Now, it is assumed that a clock having a relatively high frequency (τ is relatively short) is input as the external clock EXTCLK. The external clock EXTCLK is delayed by Δtrec by the receiver 2 and supplied to the pulse generation circuit 3, the control signal generation circuit 4, and the backward pulse delay line 7 as the clock CLK.

The pulse generation circuit 3 sets the clock CLK to τd
A pulse A that is delayed by -h and falls at the falling edge of the clock CLK is generated and output to the delay monitor 5. The pulse width of the pulse A is (τ / 2) −τd-h. The delay monitor 5 delays the pulse A by Δtmon and supplies it to the forward pulse delay line 6 as a pulse START.

The clock CLK is inverted by the control signal generation circuit 4 and applied to the forward pulse delay line 6 as a control signal STOP. Each unit delay element 11 of the forward pulse delay line 6 propagates the pulse START during the “H” period of the control signal STOP. In this case, since τ is relatively small, the number of stages through which the pulse START propagates is small.

The pulse START propagates through the forward pulse delay line 6 for a time τ− (τd−h + Δtmon), as in FIG. At this time, the pulse START does not propagate to the unit delay element 11 of the Nth stage. Control signal S
When TOP becomes "L", the propagation of the forward pulse delay line 6 stops, and the pulse corresponding to the pulse START appears at the corresponding stage of the backward pulse delay line 7 and sequentially propagates to the preceding stage. The number of stages in which this pulse propagates through the backward pulse delay line 7 is the same as the number of stages in which the pulse START propagates through the forward pulse delay line 6, and the time τ- (τ
d−h + Δtmon), the output is output as a pulse OUT from the first-stage unit delay element 12.

The pulse width restoring circuit 8 extends the pulse width of the input pulse OUT to the original pulse width and outputs it to the clock delivery 9 as the pulse C. The clock delivery 9 delays the pulse C by Δtdeli and outputs it as an internal clock INTCLK.

In this case, external clock EXTCLK
Delay amount Δtotal of the internal clock INTCLK with respect to
Can be expressed by the following equation (7).

Δtotal = Δtrec + τd−h + Δtmon + 2 ｛τ− (τd−h + Δtmon)｝ + τd−h + Δtdeli (7) Since Δtmon = Δtrec + Δtdeli, the total delay amount Δtotal is Δtotal = 2τ. Thus, an internal clock INTCLK synchronized with the external clock EXTCLK is obtained.

Next, the external clock E having a relatively low frequency
It is assumed that XTCLK is input and the pulse START propagates to the unit delay element 11 at the Nth stage. The pulse detection circuit 13 is reset by, for example, a pulse generated when the power is turned on, and the detection signal Dctl is “L”. After the reset process, the output of the multiplexer 45 in FIG. 7 is "H".

At the timing before the pulse START propagates to the Nth stage, for example, at the timing t0 in FIG. 8, the output pulse D (N) of the unit delay element 11-N at the Nth stage
Is "H". Therefore, at this timing, the level of the detection signal Dctl does not change. At the timing t1, when the pulse START propagates to the unit delay element 11-N of the Nth stage, the pulse D (N) changes to "L" (FIG. 8).
(A)). Then, the output of the flip-flop 47 becomes "H", and the "H" detection signal Dctl is output from the terminal 43 (FIG. 8B).

The output of the multiplexer 45 is "H".
, And thereafter, as shown at timing t3,
Even if the level of the pulse D (N) changes, the detection signal Dctl
Maintain “H”.

The "H" detection signal from the pulse detection circuit 13 is supplied to the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9. The receiver 2 includes a multiplexer 10 shown in FIG.
3 selects the output of the delay circuit 102. As a result, the delay time of the receiver 2 becomes Δtrec + Δtrec2. Similarly, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the multiplexer 11 of the clock delivery 9
4, 123, 135 and 143, the delay times are respectively τd−1, Δtmon + Δtmon2, τd−1, and Δtdeli +
Set to Δtdeli2.

The other operations are the same as before the change of the delay time.

In this case, external clock EXTCLK
Delay amount Δtotal of the internal clock INTCLK with respect to
Can be expressed by the following equation (8).

Δtotal = (Δtrec + Δtrec2) + τd−l + (Δtmon + Δtmon2) +2 [τ− ｛τd−1 + (Δtmon + Δtmon2)}] + τd−l + (Δtdeli + Δtdeli2)... (8) Δtmon + Δtmon2 = Δtrec + Δtrec
Since it is eli2, the total delay amount Δtotal eventually becomes Δtotal = 2τ. Thus, an internal clock INTCLK synchronized with the external clock EXTCLK is obtained.

In this case, the denominator of each term in the above equation (6) becomes large, and operation corresponding to a lower frequency band becomes possible.

As described above, in the present embodiment, when the frequency of the external clock EXTCLK is high, that is, when the period τ is small, the unit delay element 1 through which the pulse propagates
By utilizing the fact that the number of stages of 1 is reduced, if a pulse does not propagate to a predetermined stage, a pulse generation circuit is set by an output signal Dctl of the pulse detection circuit 13 so that the setting suitable for operation in a high frequency band is obtained. 3 and pulse width restoration circuit 8
And the delay time of the delay monitor 5 is controlled so that the sum of the delay times of the receiver 2 and the clock delivery 9 is equal to the delay time of the delay monitor 5. Conversely, when the frequency of the external clock EXTCLK is low and the period τ is long, the output signal Dctl of the pulse detection circuit 13 is utilized by utilizing the fact that the number of stages of the unit delay element 11 through which the pulse propagates is larger than the predetermined stage. Thus, the delay time of each circuit is controlled so that the setting is suitable for operation in a low frequency band. This makes it possible to widen the operating frequency band.

FIG. 9 is a block diagram showing another embodiment of the present invention. 9, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the embodiment of FIG. 1, once the pulse START propagates to a predetermined stage, the pulse detection circuit 1
No. 3 keeps outputting the detection signal Dctl for setting corresponding to the low operating frequency. Therefore, even if the external clock EXTCLK subsequently changes to a high frequency, it cannot be changed to a setting corresponding to a high operating frequency.

The present embodiment can cope with such a case. When the external clock changes from a low frequency to a high frequency, the pulse generation circuit 3, the pulse width restoration circuit 8, and the delay monitor 5 Is changed to a value suitable for operation in a high-frequency band, and the sum of the delay times of the receiver 2 and the clock delivery 9 is controlled to be equal to the delay time of the delay monitor 5.

In the present embodiment, the control pulse generation circuit 610
Is different from the embodiment of FIG. 1 in that a pulse detection circuit 60 is used instead of the pulse detection circuit 13.

FIG. 10 shows a control pulse generation circuit 61 in FIG.
FIG. 3 is a block diagram showing a specific configuration of a 0.

In FIG. 10, a clock CLK is input to a terminal 613. The clock CLK is supplied to the inverter 6
14 and the NAND circuit 616. Inverter 6
14 inverts the clock CLK and inputs it to the delay circuit 615. The delay circuit 615 delays the inverted signal of the clock CLK by a predetermined time and outputs the delayed signal to the NAND circuit 616.

The NAND circuit 616 performs a two-input NAND operation. That is, the clock CLK is output from the NAND circuit 616.
The control pulse / P which falls at the rising edge of the signal and rises after the delay time of the delay circuit 615 is obtained. Note that / P
Indicates an inverted signal of P. The output of the NAND circuit 616 is inverted by the inverter 617, and the output terminals 618, 61
In FIG. 9, a control pulse P and its inverted signal / P are obtained.

A control pulse generation circuit 627 having an equivalent function may be employed instead of control pulse generation circuit 610. FIG. 11 is a block diagram showing the control pulse generation circuit 627.

In FIG. 11, a clock CLK is input to terminal 620. The clock CLK is supplied to the delay circuit 62
1 and an inverter 622. Delay circuit 621
Delays the clock CLK for the first time and sets the NOR circuit 623
Output to Inverter 622 inverts clock CLK and outputs it to NOR circuit 623.

The NOR circuit 623 performs a two-input NOR operation. That is, a control pulse P that rises at the rising of the clock CLK and falls after the delay time of the delay circuit 621 is obtained from the NOR circuit 623. The output of the NOR circuit 623 is inverted by the inverter 624, and the output terminal 6
25 and 626 include a control pulse / P and a control pulse P, respectively.
Is obtained.

FIG. 12 is a block diagram showing a specific configuration of the pulse detection circuit 60 in FIG.

The input terminal 61 has an N-th stage delay element 1
1-N output pulses D (N) are input. Also, terminal 6
2, a control signal STOP is input. Pulse D (N)
Is supplied to the NAND circuit 63, and the control signal STOP is supplied to the NAND circuit 64. An RS flip-flop 611 is constituted by the NAND circuits 63 and 64.

The RS flip-flop 611 is reset when the control signal STOP goes to “L” and outputs “L”, and the pulse D (N) first becomes “L” during the “H” period of the control signal STOP. After that, the output of "H" is continuously output. Flip-flop 6
The output of 11 is supplied to the delay circuit 65. Delay circuit 65
Is configured to delay the output of the flip-flop 611 by a predetermined delay time and output the delayed output to the clocked inverter 66 constituting the D-type flip-flop 612.

The D-type flip-flop 612 is constituted by clocked inverters 66 and 68 and inverters 67 and 69. The output terminal of the clocked inverter 66 is connected to the input terminals of the inverters 67 and 69 and to the output terminal of the clocked inverter 68.
The output of the inverter 67 is supplied to the clocked inverter 68.

The clocked inverter 66 controls the control pulse P
Conducts during the period of “H”, inverts the input signal and outputs the inverted signal. The control pulse P rises in synchronization with the rise of the receiver output CLK, and the pulse width is
Is shorter than the delay time. The clocked inverter 68 conducts during the period when the control pulse P is “L”, inverts the input signal, and outputs the inverted signal.

When the clocked inverter 66 conducts, the output of the delay circuit 65 is inverted and applied to the inverter 69, and is inverted by the inverter 69 and output to the terminal 610. The output of the clocked inverter 66 is the inverter 67
The output of the inverter 67 is output from the terminal 610 via the clocked inverter 68 and the inverter 69 while the clocked inverter 66 is off.

Therefore, the D-type flip-flop 612 is
During the “H” period of the control pulse P, an output of the same logic level as the output of the delay circuit 65 is output, and this output is maintained during the “L” period of the control pulse P. The output of the D-type flip-flop 612 is used as the detection signal Dctl as the receiver 2,
The signal is output to the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9.

Next, the operation of the embodiment thus configured will be described with reference to the operation waveform diagram of FIG.
FIG. 13A shows the external clock EXTCLK, and FIG.
3 (b) shows the clock CLK, FIG. 13 (c) shows the control signal STOP, FIG. 13 (d) shows the pulse A,
FIG. 13E shows the pulse START, and FIG.
Represents an output pulse D (N) of the N-th unit delay element,
FIG. 13 (g) shows the output R1 of the flip-flop 611, FIG. 13 (h) shows the output R2 of the delay circuit 65, FIG. 13 (i) shows the control pulse P, and FIG. The detection signal Dctl from the flip-flop 612 is shown.

Now, as shown in FIG. 13A, the first clock C1 and the second clock C2 of the external clock EXTCLK have a long period τ1 and the forward pulse delay line 6
START up to the N-th stage of the unit delay element constituting
And the third and subsequent clocks C3 and C4
,... Assume that the period τs is short and the pulse START does not propagate to the Nth stage. In the initial state, the delay times of the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9 are as follows.
Δtrec, τd-h, Δtdeli,
τd-h, Δtmon.

The output pulse D (N) of the unit delay element 11-N of the Nth stage is "H" when no pulse propagates.
The external clock EXTCLK is input to the receiver 2, the output CLK of the receiver 2 is input to the control signal generation circuit 4 and the pulse generation circuit 3, and the control signal generation circuit 4 generates an inverted signal STOP of the clock CLK and generates a pulse. The circuit 3 generates a pulsed signal A.

Before the timing t0, the pulse does not propagate to the N-th stage, and in the range from t0 to t1, the pulse generation circuit 3
The delay circuit of the pulse width restoration circuit 8 and the delay time of the delay monitor are controlled so as to be suitable for operation in a high frequency band. Here, when the low-frequency external clock EXTCLK propagating to the Nth and subsequent stages is input, FIG.
The pulse A and the pulse STA near the timing t1 in FIG.
Like RT, the rise of the pulse START is in a state where the control signal STOP is barely being input to the forward pulse delay line 6 during the period when the control signal STOP is “H”, that is, during the period when the forward pulse delay line 6 operates. If the clock cycle becomes shorter than this, the rise of the pulse START may not be propagated.

For this reason, it is necessary to control the delay circuits of the pulse generation circuit 3 and the pulse width restoration circuit 8 and the delay time of the delay monitor so as to be suitable for operation in a low frequency band. When the pulse propagates to the N-th unit delay element 11-N, the output pulse D (N) of the N-th unit delay element 11-N becomes
As shown at the timing t1 of 3 (f), the signal changes from "H" to "L".

Then, as shown in FIG. 13 (g), the output R1 of the RS flip-flop 611 of the pulse detection circuit 60 becomes "L" during the period from the timing t1 to the next timing t2 when the control signal STOP becomes "L". H ”. When the clock CLK becomes "H" at the timing t2, the control pulse P also becomes "H", and the D-type flip-flop 612 takes in the value of R1 immediately before t2, that is, the output of "H" through the delay circuit 65.

The output of the delay circuit 65 is the clock CL
It is output as a detection signal Dctl until timing t4 when K rises. When the detection signal Dctl becomes “H”, the pulse generation circuit 3, the pulse width restoration circuit 8, and the delay circuit of the delay monitor 5 are controlled to values suitable for operation in a low frequency band, and the receiver 2 and the clock delivery circuit are controlled. 9 is controlled so that the sum of the delay times is equal to the delay time of the delay monitor 5. That is, the delay times of the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9 are each Δ
trec + Δtrec2, τd-l, Δtdeli + Δtdeli2, τd-
l, Δtmon + Δtmon2.

Next, after the timing t4, the external clock EXTCLK has a high frequency, and the period τs is short. As shown in FIG. 13E, the pulse STA
Since RT has not propagated to the Nth stage during the period from timing t5 to t6, D (N) remains at "H" during this period. Therefore, the output R of the flip-flop 611
Since 1 is kept at "L", "L" is taken into the D-type flip-flop 612 when the clock CLK rises at the timing t6. Thus, the detection signal Dctl of "L" is output after the timing t6.

Then, the pulse generation circuit 3, the pulse width restoration circuit 8 and the delay monitor 5 are controlled to have a delay time suitable for high-frequency operation, and the sum of the delay times of the receiver 2 and the clock delivery 9 is determined by the delay monitor 5. It is controlled to be equal to the delay time. That is, the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8
And the delay time of the clock delivery 9 are Δtrec, τd-h, Δtdeli, τd-h, and Δtmon corresponding to the high frequency, respectively.
Becomes

As described above, in the present embodiment, it is possible to cope with the fluctuation of the frequency of the external clock, and when the external clock changes from a high frequency to a low frequency, or when the external clock changes from a low frequency to a high frequency. Even so, a delay time suitable for operation in a frequency band is set. Thus, reliable synchronization control can be performed in a wide frequency band.

FIG. 14 is a block diagram showing another embodiment of the present invention. 14, the same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

In the embodiment of FIG. 9, for example, a pulse STAR is generated by a change in the external clock EXTCLK.
When the state in which T propagates to the Nth stage and the state in which T does not propagate are frequently repeated, the delay time of each circuit frequently changes, and the operation may become unstable.

The present embodiment corresponds to this case, and enables stable control even when the external clock EXTCLK has jitter.

This embodiment differs from the embodiment of FIG. 9 in that a pulse detection circuit 80 is employed in place of the pulse detection circuit 13. The pulse detection circuit 80 includes not only the output pulse D (N) of the unit delay element 11-N of the N-th stage, but also the unit of the (N-M) -th stage M (M is an even number) before the N-th stage. The output pulse D (NM) of the delay element 11- (NM) is also input. When M is an odd number, the pulse D
(N−M) may be inverted and used.

FIG. 15 is a block diagram showing a specific configuration of the pulse detection circuit 80 in FIG.

The pulse detection circuit 80 has detection sections 87 and 88 having the same configuration as in FIG. A pulse D (N−M) and a control signal STOP are input to input terminals 61 and 62 of the detection unit 87, respectively.
2, a pulse D (N) and a control signal STOP are input.

The output CTL (N−M) of the detector 87 is supplied to the NAND circuit 81 and the OR circuit 82, and the output CTL (N) of the detector 88 is also supplied to the NAND circuit 81 and the OR circuit 82. The NAND circuit 81 generates an output N1 by a two-input NAND operation and outputs the output N1 to the NAND circuit 83. The OR circuit 82 outputs an output N2 by a two-input OR operation.
And outputs it to the NAND circuit 84.

That is, the output N1 of the NAND circuit 81 is the output CTL (NM) from the detectors 87 and 88, CTL
It becomes "L" only when (N) is "H". The output N2 of the OR circuit 82 becomes "H" when one of the outputs CTL (NM) and CTL (N) from the detectors 87 and 88 is "H".

An RS flip-flop 86 is constituted by the NAND circuits 83 and 84. The RS flip-flop 86 is reset when the output N2 becomes "L", outputs "L", and outputs "H". After the output N1 first becomes "L" during the "period", the output of "H" is continuously output. RS flip-flop 86
Is output from the terminal 85 as the detection signal Dctl. This detection signal Dctl is used for the receiver 2,
The delay time of each circuit is controlled by being supplied to the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8 and the clock delivery 9, as in the embodiment of FIG.

Next, the operation of the embodiment thus configured will be described with reference to the operation waveform diagram of FIG.
FIG. 16A shows the external clock EXTCLK, and FIG.
6 (b) shows the clock CLK, FIG. 16 (c) shows the control signal STOP, FIG. 16 (d) shows the pulse A,
FIG. 16E shows the pulse START, and FIG.
Is the output pulse D (NM) of the NM-th stage unit delay element
16 (g) shows the output pulse D (N) of the unit delay element in the Nth stage, FIG. 16 (h) shows the output CTL (NM) of the detection unit 87, and FIG. ) Indicates the output CTL (N) of the detection unit 88, and FIG.
16 (k) shows the output N2 of the OR circuit 82, and FIG. 16 (l) shows the RS flip-flop 8
6 shows the detection signal Dctl.

Now, as shown in FIG. 16A, the first clock C1 of the external clock EXTCLK has a period τm.
The pulse START propagates up to the NM-th stage of the unit delay element constituting the forward pulse delay line 6, but does not propagate up to the N-th stage, and the second clock C2 has a period τ1 The pulse START propagates to the Nth stage of the unit delay element constituting the forward pulse delay line 6, the third clock C3 has a period τm, and the fourth and subsequent clocks C4, C5,. Assume that the period .tau.s is short and the pulse START does not propagate to the NM-th stage. In the initial state, the delay times of the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9 are respectively
Δtrec, τd-h, Δtdeli, τd-
h, Δtmon.

The output pulses D (N) and D (NM) of the unit delay elements of the Nth and NM stages are "H" when the pulse START does not propagate. External clock EXTC
LK is input to the receiver 2, and a clock CLK shown in FIG. 16B is generated. The clock CLK is input to the pulse generation circuit 3, and a pulse A having a pulse width of {(τm / 2) -τd-h} rising from the clock CLK with a delay of τd-h is output.

Assuming that the pulse has not propagated to the NM stage before the timing t0, the output pulse D (NM) of the unit delay element 11- (NM) of the NM stage and the unit delay element 11- The N output pulses D (N) remain at "H" (FIGS. 16 (f) and 16 (g)). Therefore, when the clock CLK rises at the timing t0, the output CT of the detection unit 87 to which the pulse D (NM) is supplied is output.
The output CTL (N) of the detection unit 88 to which L (NM) and the pulse D (N) are supplied is both "L" (FIGS. 16 (h) and (i)). Output CTL (N), CTL (N
-M) keeps "L" until the next rise of the clock CLK, that is, until the timing t2.

Since "L" is input to the NAND circuit 81 and the OR circuit 82, the output N1 of the NAND circuit 81 is "H" and the output N2 of the OR circuit 82 is "L" during the period from timing t0 to t2. ". Therefore, the output Dctl of the flip-flop 86 is held at "L" during the period from the timing t0 to the timing t2.

When the detection signal Dctl is "L", the delay time of the pulse generating circuit 3, the pulse width restoring circuit 8 and the delay monitor 5 is controlled so as to enable operation in a high frequency band. Control is performed so that the sum of the delay times of the roses 9 is equal to the delay time of the delay monitor 5.

Next, the operation when the clock CLK rises at the timing t2 will be described. Timing t
Since the forward pulse propagates to the NM stage at 1, NM
The output pulse D (N−M) of the unit delay element at the stage is “L”.
It has become. Since the pulse has never propagated to the Nth stage before the timing t2, the output pulse D (N) of the unit delay element at the Nth stage is maintained at "H" during the period from the timing t0 to t2.

Therefore, at the timing t2, the clock CL
When K rises, “H” is taken into the detection unit 87 to which the pulse D (N−M) is supplied, and the pulse D (N)
Is supplied to the detection unit 88 to which "L" is taken. As shown in FIGS. 16 (h) and (i), after the timing t2, the output CTL (NM) becomes "H" and the output CTL
(N) becomes "L". Therefore, the output N1 of the NAND circuit 81 becomes "H" and the output N2 of the OR circuit 82 becomes "H".
Becomes

Since the RS flip-flop 86 holds the value at the timing t2, the detection signal Dctl is held at "L" during the period from the timing t2 to the timing t4, as shown in FIG. .

As described above, after the N-th stage, the pulse START
Does not propagate once, but propagates to the NM stage, the detection signal Dctl is maintained at "L", so that each circuit maintains the delay time setting suitable for operation in the high frequency band. I do.

Next, the operation when the clock CLK rises at the timing t4 will be described. Timing t
At 3, the pulse START propagates to the N-th stage unit delay element 11-N. Therefore, the pulses D (NM), D
(N) are both "L". Therefore, until the clock CLK becomes "H" at the next timing t6, the output CT
Both L (NM) and CTL (N) are maintained at "H".

Therefore, the output N1 of the NAND circuit 81 becomes "L" and the output N2 of the OR circuit 82 becomes "H", so that the output Dctl of the RS flip-flop 86 becomes "H".
Becomes Since the detection signal Dctl becomes “H”, the delay time of the pulse generation circuit 3, the pulse width restoration circuit 8 and the delay monitor 5 is controlled so as to be able to operate in a low frequency band, and the clock distribution to the receiver 2 is performed. 9 is controlled so that the sum of the delay times is equal to the delay time of the delay monitor 5.

Here, it is assumed that after the pulse START has propagated to the N stages, the number of stages through which the pulse propagates varies from N ± M stages to N stages due to the influence of jitter and the like.

When propagating to N or more stages, N-
Since the pulse START propagates to the M-stage and N-stage unit delay elements 11, the delay time is controlled so that each circuit operates in a low-frequency band.

After propagating once to the N-stage unit delay element 11-N, as shown at timing t5 in FIGS. 16 (f) and 16 (g), it propagates only to the stage between NM and N stages. When no longer occurs, as shown in FIG.
(N) maintains “H”, and the pulse D (NM) changes to “L”.
become. Therefore, as shown in FIGS. 16H and 16I, the output CTL (N−M) of the detection unit 87 becomes “H” and the output CTL (N) of the detection unit 88 becomes “L”.

Since "L" is input to the NAND circuit 81 and "H" is input to the OR circuit 82, each of the outputs N1 and N2 is output.
Becomes "H" as shown at timing t5 in FIGS. 16 (j) and 16 (k). The flip-flop 86
Since the two inputs are "H", the output is not changed. That is, at this timing, the detection signal Dctl is set to “H”.
Is maintained.

As a result, in this case, the setting of the delay time is maintained so that each circuit can operate in the low frequency band.

Further, as shown in the period from timing t6 to t7, when the pulse START does not propagate to the NM stage, the operation becomes the same as that during the period from timing t0 to t2. That is, when the clock CLK rises at the timing t7, the pulses D (NM) and D (N) become "H".
Is maintained at the timing t7.
Becomes “H”, the output CTL (N−M), CTL
(N) becomes "L". Therefore, after the timing t7, the output N1 of the NAND circuit 81 becomes "H" and the output N2 of the OR circuit 82 becomes "L", so that the detection signal Dctl from the flip-flop 86 becomes "L". That is, the delay time of each circuit is set so that it can operate in a high frequency band.

As described above, in the present embodiment, after the pulse START has propagated to N stages, the number of stages through which the pulse propagates between the NM stage and the N stage due to the influence of jitter or the like changes. If the pulse START has propagated to the Nth stage once, each circuit is continuously set to a delay time suitable for operation in the low frequency band, so that the synchronization control operation can be stabilized.

FIG. 17 is a block diagram showing another embodiment of the present invention. 17, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, a receiver 152, a pulse generation circuit 153, a delay monitor 155, and a pulse width recovery circuit are used instead of the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width recovery circuit 8, and the clock delivery 9, respectively. 1 in that a circuit 158 and a clock delivery 159 are employed, and a plurality of pulse detection circuits 90-1 to 90-v are employed.

In the embodiment shown in FIG. 1, the receiver 2, the pulse generating circuit 3, the delay monitor 5, the pulse width restoring circuit 8, and the clock delivery 9 set two kinds of delay times for low frequency and high frequency. Met.

In this embodiment, the receiver 152, the pulse generation circuit 153, the delay monitor 155, the pulse width restoration circuit 158, and the clock delivery 159 can be set to a plurality of delay times and are suitable for a plurality of frequency bands. Settings.

The present embodiment can cope with a wider frequency band by subdividing and controlling the operating frequency band. For this purpose, the pulse START is provided in a plurality of stages of the forward pulse delay line 6 and the backward pulse delay line 7.
Is detected as to whether or not has propagated. FIG.
Then, the forward pulse delay line 6 and the backward pulse delay line 7 are divided into blocks for each of a plurality of stages, and the pulse ST
ART propagation is detected.

That is, output pulses of the unit delay elements are supplied from v blocks to the pulse detection circuits 90-1 to 90-v. It is obvious that any of the pulse detection circuits shown in FIGS. 7, 12, and 15 may be used as the pulse detection circuits 90-1 to 90-v. When the pulse detection circuits of FIGS. 7 and 12 are used, the output pulse of a unit delay element at a predetermined stage of each block is used, and when the pulse detection circuit of FIG. The output pulse of the stage unit delay element is used.

The pulse detection circuits 90-1 to 90-v output a detection signal Dctl indicating that the pulse has been propagated to the receiver 1.
52, a pulse generation circuit 153, a delay monitor 155,
The signal is output to the pulse width restoration circuit 158 and the clock delivery 159.

FIG. 18 is a block diagram showing a specific structure of the receiver 152 in FIG. In FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted.

FIG. 18 differs from FIG. 2 in that a plurality of delay circuits 251-1 to 251-v are employed in place of the delay circuit 102 and a multiplexer 252 is employed in place of the multiplexer 103.

The output of the receiving section 100 is supplied to a plurality of delay circuits 251-1 to 251-v and to a multiplexer 252. Delay circuits 251-1 to 251-v
Delays the input clock by a predetermined amount different from each other and outputs the delayed clock to the multiplexer 252. The multiplexer 252 determines whether the v input is 1 based on the detection signal Dctl.
One is selected and output to terminal 104 as clock CLK. The delay amounts of the delay circuits 251-1 to 251-v are values based on the respective frequency bands corresponding to the stages where the pulse detection circuits 90-1 to 90-v detect the propagation of the pulse. Therefore, the delay amount increases in the order of 251-1, 251-2,....

When the pulse detection circuit 90-1 indicates that the pulse has not propagated to the predetermined stage, the multiplexer 252 selects the output of the receiving unit 100. When the pulse detection circuits 90-1 to 90-v detect that a pulse has propagated to a predetermined stage, the multiplexer 252 selects and outputs the output of the corresponding delay circuit. I have.

FIG. 19 shows a pulse generation circuit 153 in FIG.
FIG. 3 is a block diagram showing a specific configuration of FIG. 19, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 19 employs a plurality of delay circuits 261-1 to 261- (v + 1) in place of the delay circuits 112 and 113, and a multiplexer 2 in place of the multiplexer 114.
FIG. 3 differs from FIG.

The clock CLK input via the input terminal 111 is supplied to the delay circuits 261-1 to 261- (v + 1) and the AND circuit 116. Delay circuits 261-1 to 26-1
1- (v + 1) delays the input clock CLK by a delay amount corresponding to each frequency band, and
Output to The multiplexer 262 selects one of the (v + 1) inputs based on the detection signal Dctl input via the terminal 115 and outputs it to the AND circuit 116. An AND circuit 116 performs an AND operation of two inputs to output the output terminal 11.
7 is output as a pulse A.

Therefore, the terminal 117 receives the clock CLK.
The pulse rises after a delay time based on the detection signal Dctl from the rise of the clock CLK, and falls at the fall of the clock CLK.

FIG. 20 shows the delay monitor 155 in FIG.
FIG. 3 is a block diagram showing a specific configuration of FIG. 20, the same components as those of FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 20 differs from FIG. 4 in that a plurality of delay circuits 271-1 to 271-v are used in place of the delay circuit 122 and a multiplexer 272 is used in place of the multiplexer 123.

The pulse A from the delay unit 120 is supplied to the multiplexer 272 and the delay circuits 271-1 to 271-v. The delay circuits 271-1 to 271-v delay the input pulse A by a delay amount corresponding to each frequency band and output the delayed pulse A to the multiplexer 272. The multiplexer 272 detects the detection signal Dctl input via the terminal 124.
, One of the v inputs is selected and output to the terminal 125. Accordingly, a pulse START that is delayed by a delay time corresponding to each frequency band appears at the terminal 125 based on the detection signal Dctl.

FIG. 21 shows the pulse width restoration circuit 15 in FIG.
8 is a block diagram showing a specific configuration of FIG. 21, the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 21 employs a plurality of delay circuits 261-1 to 261- (v + 1) in place of the delay circuits 133 and 134, and a multiplexer 2 in place of the multiplexer 135.
The difference from FIG. 5 is in that 81 is used.

The pulse OUT input through the input terminal 131 is supplied to the delay circuits 261-1 to 261- (v + 1) and the OR circuit 137. Delay circuits 261-1 to 261-
In (v + 1), the input pulse OUT is delayed by a delay amount corresponding to each frequency band and output to the multiplexer 281. The multiplexer 281 receives the (v + 1) input 1 based on the detection signal Dctl input via the terminal 136.
One is selected and output to the OR circuit 137 and the gate of the nMOS transistor 138.

The pulse width restoring circuit 1 configured as described above
At 58, the detection signal Dct input to the terminal 136 is output.
l allows the multiplexer 281 to operate the delay circuit 261
The output of the delay circuit that operates with the same delay amount as the delay amount used in the pulse generation circuit 153 is selected from −1 to 261 − (v + 1). Thus, a pulse C having the same pulse width as the clock CLK is obtained from the terminal 1312 at the rising of the pulse OUT.

FIG. 22 shows the clock delivery 15 in FIG.
9 is a block diagram showing a specific configuration of No. 9; FIG. In FIG. 22, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 22 differs from FIG. 6 in that a plurality of delay circuits 291-1 to 291-v are used in place of the delay circuit 142 and a multiplexer 292 is used in place of the multiplexer 143.

The pulse C from the output buffer 140 is supplied to the multiplexer 292 and the delay circuits 291-1 to 291-v. The delay circuits 291-1 to 291-v delay the input pulse C by a delay amount corresponding to each frequency band and output the delayed pulse C to the multiplexer 292. The multiplexer 292 receives the detection signal Dct input through the terminal 144.
One of the v inputs is selected based on l and output to terminal 145. Accordingly, at the terminal 145, the internal clock INTCLK that is delayed by a delay time corresponding to each frequency band appears based on the detection signal Dctl.

Next, the operation of the embodiment configured as described above will be described.

Now, for example, the pulse detection circuit 90-w has the same configuration as the pulse detection circuit 13 shown in FIG. 7, and the output of the s-th unit delay element 11-s of the forward pulse delay line 6 is It is assumed that the signal is supplied to the fifth pulse detection circuit 90-5.

Here, an external clock EX having a predetermined frequency
It is assumed that TCLK is input and the pulse START propagates to the s-th stage and does not propagate to the stage of the unit delay element to which the pulse detection circuit 90-6 is connected. Then, the detection signals Dctl-1 from the pulse detection circuits 90-1 to 90-5 are output.
To Dctl-5 become "H", and other detection signals Dctl-6,
Dctl-7,... Remain "L".

[0185] The receiver 15
2 delay circuit 251-5, the delay circuit 261-6 of the pulse generation circuit 153, and the delay circuit 271- of the delay monitor 155.
5. The output of the delay circuit 261-6 of the pulse width restoration circuit 158 and the output of the delay circuit 291-5 of the clock delivery 159 are selected. The sum of the delay amount of the receiver 152 and the delay amount of the clock delivery 159 is set to the delay amount of the delay monitor 155.

These delay amounts are determined by the forward pulse delay line 6
Is suitable for the operating frequency corresponding to the number of stages up to the s-th stage. Thus, the setting can be made suitable for the frequency of the external clock EXTCLK.

As described above, in the present embodiment, the frequency band is subdivided, so that the operating frequency can be controlled with high precision, and the applicable frequency band is set to be smaller than that in the embodiment of FIG. Can be further expanded.

In each of the above embodiments, the pulse detection circuit is connected to only some of the unit delay elements 11, and the unit delay elements 11 to which the pulse detection circuits are connected are connected.
In this case, the load capacitance to be driven is different from other unit delay elements, and the delay time is different from the delay time of other unit delay elements. Therefore, by adding a capacitor having the same capacity as that of the pulse detection circuit to the output of each unit delay element, the delay time of all the unit delay elements can be made equal.

When the operation of the conventional circuit is described with reference to FIG. 24, the delay time of the AND circuit 53 and the delay time of the pulse width restoration circuit 168 (for two OR stages) constituting the pulse generation circuit 163 are set to 0. Explain. The influence of the delay time of the AND circuit 53 and the delay time of the pulse width restoration circuit 168 constituting the pulse generation circuit 163 on the synchronization accuracy by adding a circuit having the same delay time as the delay time to the delay monitor or the like. Can be eliminated. This is the same in each embodiment.

In the embodiments shown in FIGS. 1, 9 and 14, the delay time of the multiplexer constituting the receiver 2, the pulse generation circuit 3, the delay monitor 5, the pulse width restoration circuit 8, and the clock delivery 9 is set to 0. Explain. The delay time of the multiplexer of the delay monitor 5 is configured to be the sum of the delay time of the multiplexer of the receiver 2 and the delay time of the multiplexer of the clock delivery 9, or the delay time of the receiver 100, the delay unit 120, and the output buffer 140 is changed. , Receiver 100, delay unit 120, output buffer 140, and the sum of delay times of multiplexers used in each circuit are Δtrec, Δtmon,
By setting Δtdeli, it is possible to eliminate the influence of the receiver 2, the delay monitor 5, and the clock deliver 9 on the synchronization accuracy of the multiplexer delay time.
The multiplexers of the pulse generation circuit 3 and the pulse width restoration circuit 8 are determined by making the delay times of the multiplexers of the pulse generation circuit 3 and the pulse width restoration circuit 8 the same or by determining the delay time of the delay circuit by considering the delay time of the multiplexer. The influence on the synchronization accuracy can be eliminated.

The same can be said for the embodiment shown in FIG.

In each of the above embodiments, a stress test is performed because all circuits are operable when operating in the high frequency band and when operating in the low frequency band. Even if there is no problem.

Furthermore, in each of the above-described embodiments, an example has been described in which the delay time of the pulse generation circuit and the pulse width restoration circuit is controlled by the detection signal, and the delay time of the receiver, the delay monitor, and the clock delivery are also controlled. However, the delay time of only the pulse generation circuit and the pulse width restoration circuit may be controlled, or only the delay time of the receiver, the delay monitor, and the clock delivery may be controlled.

[0194]

As described above, according to the present invention, there is an effect that the operating frequency band can be widened by making it possible to switch the delay amount of the delay line of each circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock synchronization delay control circuit according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a receiver 2 in FIG.

FIG. 3 is a block diagram showing a specific configuration of a pulse generation circuit 3 in FIG. 1;

FIG. 4 is a block diagram showing a specific configuration of a delay monitor 5 in FIG. 1;

FIG. 5 is a block diagram showing a specific configuration of a pulse width restoration circuit 8 in FIG. 1;

FIG. 6 is a block diagram showing a specific configuration of a clock deliver 9 in FIG. 1;

FIG. 7 is a block diagram showing a specific configuration of a pulse detection circuit 13 in FIG. 1;

FIG. 8 is an operation waveform diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 9 is a block diagram showing another embodiment of the present invention.

FIG. 10 is a block diagram showing a specific configuration of a control pulse generation circuit 610 in FIG. 9;

FIG. 11 is a block diagram showing another example of the control pulse generation circuit.

FIG. 12 is a block diagram showing a specific configuration of a pulse detection circuit 60 in FIG. 9;

FIG. 13 is an operation waveform diagram for explaining the operation of the embodiment in FIG. 9;

FIG. 14 is a block diagram showing another embodiment of the present invention.

FIG. 15 is a block diagram showing a specific configuration of a pulse detection circuit 80 in FIG. 14;

FIG. 16 is an operation waveform diagram for explaining the operation of the embodiment in FIG. 14;

FIG. 17 is a block diagram showing another embodiment of the present invention.

18 is a block diagram showing a specific configuration of a receiver 152 in FIG.

FIG. 19 is a block diagram showing a specific configuration of a pulse generation circuit 153 in FIG. 17;

20 is a block diagram showing a specific configuration of a delay monitor 155 in FIG.

FIG. 21 is a block diagram showing a specific configuration of a pulse width restoration circuit 158 in FIG. 17;

FIG. 22 is a block diagram showing a specific configuration of a clock deliver 159 in FIG. 17;

FIG. 23 is a block diagram showing a conventional clock synchronization delay control circuit.

FIG. 24 is an operation waveform diagram for explaining the operation of the conventional example.

FIG. 25 is a block diagram showing a specific configuration of a pulse generation circuit 163 in FIG. 23;

FIG. 26 is a block diagram showing a specific configuration of a forward pulse delay line 6 and a backward pulse delay line 7 in FIG. 23;

FIG. 27 is a block diagram showing a specific configuration of a pulse width restoration circuit 168 in FIG. 23;

FIG. 28 is an operation waveform diagram for explaining the operation of the conventional example.

FIG. 29 is an operation waveform diagram for explaining a problem of the conventional example.

FIG. 30 is an operation waveform diagram for explaining a problem of the conventional example.

FIG. 31 is a circuit diagram showing a specific configuration of the delay circuit in FIGS. 25 and 27.

[Explanation of symbols]

2 receiver, 3 pulse generating circuit, 4 control signal generating circuit, 5 delay monitor, 6 delay line for forward pulse,
7 ... Delay pulse delay line, 8 ... Pulse width restoration circuit, 9 ...
Clock delivery, 11, 12 ... unit delay element, 13 ...
Pulse detection circuit

Claims (4)

[Claims] An input means for receiving and outputting an external clock; a pulse signal having a width narrower than a half cycle of the external clock, wherein the pulse signal has a first delay time with respect to the external clock from the input means. A pulse generating means for generating a delayed first pulse signal; a delay means for delaying and outputting the first pulse signal; and a plurality of cascade-connected unit delay elements. The first pulse signal is supplied to the first-stage unit delay element, propagates to the second-stage unit delay element, stops at a timing synchronized with the external clock from the input means, and obtains an output indicating the number of propagated stages. A forward pulse delay line, and a plurality of cascade-connected unit delay elements, wherein the first pulse signal is output from the forward pulse based on an output of the forward pulse delay line. The first pulse signal has propagated through the forward pulse delay line from the stop of the propagation of the first pulse signal by propagating and outputting the pulse signal by the number of stages corresponding to the number of stages propagated through the delay line for forward pulse. A backward pulse delay line that outputs a pulse signal after the same time as the time, and an edge of the pulse signal from the backward pulse delay line is delayed by the first delay time, whereby an external clock from the input unit is output. Pulse width restoring means for restoring and outputting the same pulse width as the pulse width, and operating with a delay time obtained by subtracting the delay time by the input means from the delay time by the delay means, and outputting the output of the pulse width restoring means. Output means for delaying and outputting as an internal clock; and a pulse for detecting the number of stages of unit delay elements of the forward pulse delay line through which the first pulse signal has propagated. Delay detecting means, and delay time controlling means for controlling at least one of the first delay time and the delay times by the input means, the delay means and the output means based on the detection result of the pulse detecting means. A clock synchronization delay control circuit characterized in that: 2. The pulse detection means outputs a detection result for controlling the delay time by the delay time control means when the first pulse signal propagates to a designated stage of the forward pulse delay line. 2. The clock synchronization delay control circuit according to claim 1, wherein: 3. The pulse detection means outputs a detection result for coping with low-frequency operation by controlling the delay time by the delay time control means when the first pulse signal propagates to a first stage. 2. The detection result according to claim 1, wherein when the first pulse signal stops propagating to the second stage, a detection result for coping with a high-frequency operation is output by controlling the delay time by the delay time control means. Clock synchronization delay control circuit. 4. The clock synchronization delay control circuit according to claim 3, wherein said pulse detection means is a stage different from said first stage and said second stage.