JPH11274501A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce crystal defects to be caused in a logic element formation region in the manufacturing process when logic circuit transistors are formed in an island-like logic element formation region surrounded by an insulating trench. SOLUTION: There are formed an island-like logic element formation region 16 is a state of being separated mutually by a frame-like insulating trench 15 group and a plurality of power element formation regions 17 in a single crystal silicon layer of a SOI structure. In each of the power element formation regions 17, N-channel type LDMOSs and P-channel type LDMOSs are formed as power semiconductor elements, respectively. In the logic element formation region 16, a frame-like N-well 27 is formed in a state that a circumferential part region coming into contact with the insulating trench 15 is contained, and also a P-well 28 is formed in a state of being surrounded N-well 27. Logic circuit CMOS transistors are formed in these N-well 27 and P-well 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an island-shaped logic element forming region surrounded by an insulating trench on a semiconductor substrate.

[0002]

2. Description of the Related Art For driving an EL display or a plasma display used for a flat panel display for an automobile, a monolithic power IC (a so-called intelligent power IC) in which a control IC and a power semiconductor element are mounted on one chip. The use of is being done. In such a power IC, a plurality of island regions surrounded by insulating trenches are provided on a semiconductor substrate, and a logic circuit element constituting a control IC and a load control Of a power semiconductor element (for example, a power MOSFET).

FIG. 6 shows an outline of a basic example of a planar layout of a logic circuit element portion formed in a power IC as described above. In FIG. 6, a logic element formation region 2 surrounded by a frame-shaped insulating trench 1 is a P well 3
N well 4 is arranged in the
A logic circuit transistor such as a CMOS transistor is formed in the well 3 and the N well 4. FIG.
In the example, the width dimension W of the logic element formation region 2 is 100 μm
It is set before and after.

[0004]

SUMMARY OF THE INVENTION Monolithic power I
In the manufacturing process of C, LOCOS for element isolation is used.
Various heat treatments including a heat treatment for forming an oxide film are performed. In a configuration in which the P well 3 is in contact with the insulating trench 1 as shown in FIG. Due to such heat treatment, stress distortion is generated, and due to such distortion, a maximum of 20 to 20 parts is formed at the boundary between the P well 3 and the insulating trench 1 (the part indicated by the broken line band in FIG. 6). It has been found that a crystal defect reaching a width of about 25 μm may occur, which causes a problem that junction leakage of a transistor for a logic circuit increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a logic circuit transistor in an island-shaped logic element formation region surrounded by an insulating trench. Accordingly, it is an object of the present invention to provide a semiconductor device which can reduce crystal defects generated in a logic element formation region.

[0006]

Means for Solving the Problems In order to achieve the above object, means as described in claim 1 can be employed. This means is characterized in that a frame-shaped N-type impurity diffusion region (27) including a peripheral region in contact with the insulating trench (15) is formed at least on the surface side of the logic element formation region (16). . In this case, in a single crystal semiconductor, it is generally known that a region in which an N-type impurity is diffused has less crystal defects due to stress distortion than a region in which a P-type impurity is diffused. The N-type impurity diffusion region (2)
According to the configuration in which 7) is formed, it is possible to reduce crystal defects generated in the logic element formation region (16) in the manufacturing process of the semiconductor device. For this reason, junction leakage in the logic circuit transistor (26) formed in the P well (28) surrounded by the N-type impurity diffusion region (27) is suppressed, and the characteristics of the logic circuit are reduced. It is possible to prevent the deterioration beforehand. The P well (28) and the N-type impurity diffusion region (2)
If the configuration is such that the logic circuit transistor (26) is formed in both cases 7), the application range can be expanded, for example, the formation of the complementary logic circuit transistor (26) can be performed easily.

According to a third aspect of the present invention, a logic element forming area (16) and a power element forming area (17) are provided on a semiconductor substrate (11), and each element forming area (16, 1) is formed.
7) When forming the logic circuit transistor (26) and the power semiconductor elements (20, 21) in (7), the depth of the N-type impurity diffusion layer (27) on the side of the logic element formation region (16) and the power element formation When the depths of the N wells (22, 25) for the power semiconductor elements (20, 21) formed on the region (17) side are set to be the same, the N type impurity diffusion layer (27) and Since the N wells (22, 25) can be formed in one process using the same mask, the manufacturing process can be simplified.

According to a fourth aspect of the present invention, a logic element forming area (16) and a power element forming area (17) are provided on a semiconductor substrate (11), and each element forming area (16, 1) is provided.
When forming the logic circuit transistor (26) and the power semiconductor elements (20, 21) in (7), the depth of the P well (28) on the side of the logic element formation area (16) and the power element formation area (17) ) -Side power semiconductor device (2
When the depths of the P wells (23, 24) for the P wells (23, 24) are set to be the same,
4, 28) can be formed in one process using the same mask, so that the manufacturing process can be simplified.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a planar layout of a basic structure of a monolithic power IC in which a control IC and a power semiconductor element are mounted on one chip, and FIG. 2 schematically shows a schematic sectional structure of the basic structure. FIG. 3 schematically shows a cross-sectional structure of the monolithic power IC in a completed state.

In FIG. 1 and FIG. 2, the SOI substrate 11
The semiconductor substrate (corresponding to the semiconductor substrate in the present invention) has a structure in which a single crystal silicon layer 14 is provided on a base substrate 12 made of, for example, a P-type silicon substrate via a silicon oxide film 13 for insulation separation (see FIG. 2). In the single-crystal silicon layer 14, an island-shaped logic element formation region 16 and a plurality of power element formation regions 17 are formed which are separated from each other by a group of insulating trenches 15 having a frame shape. Have been.
The insulating trench 15 is back-filled with the insulating silicon oxide film 18 and the polysilicon 19 (see FIG. 1).

Each of the power element forming regions 17 has a structure shown in FIG.
NMOS LDMOS 20 (Lateral Dome)
A double-diffused MOS (horizontal double-diffused MOS transistor) and a P-channel LDMOS 21 are formed as power semiconductor elements according to the present invention, and a well structure is provided for them. Specifically, in the power element forming region 17 for the N-channel LDMOS 20, an N well 22 for a drain is formed, and a ring-shaped P well 23 for forming a source and a channel is formed. . Also, a P-channel type LD
In the power element forming region 17 for the MOS 21, a P-well 24 for a drain is formed, and a ring-shaped N-well 25 for forming a source and a channel is formed.

In the logic element formation region 16, a CMOS transistor 26 (corresponding to a logic circuit transistor in the present invention) as shown in FIG. 3 is formed, and a well structure therefor is provided. I have. Specifically, the logic element formation region 16 includes the insulating trench 1
Frame-shaped N-well 2 including a peripheral region in contact with 5
7 (corresponding to the N-type impurity diffusion region in the present invention) and the P region surrounded by the N well 27 are formed.
A well 28 is formed.

As shown in FIG. 2, a low impurity concentration layer 29 (having an impurity concentration of, for example, 1 × 10 ¹⁴ / cm ³ or less), and this low impurity concentration layer 29 functions as an electric field relaxation layer in the LDMOSs 20 and 21. A portion indicated by reference numeral 34 in FIG. 2 is a LOCOS oxide film described later (not shown in FIG. 1).

Now, in the following, L shown in FIG.
The configurations of the DMOSs 20 and 21 and the CMOS transistor 26 will be schematically described.

The N-channel type LDMOS 20 has a region (a low impurity concentration layer 29) between the N well 22 and the P well 23.
Is a drift layer 30 composed of an N ⁻ diffusion layer.
It has become. The drift layer 30 is provided as a low impurity concentration layer because a relatively high resistance is required, but has a higher impurity concentration than the low impurity concentration layer 29.

The P well 23 has a low impurity concentration layer 29
, And a channel forming region 23b formed at a surface side portion so as to be continuous with the electric field relaxing region 23a. In this case, the impurity concentration of the electric field relaxation region 23a is
The state is lower than the impurity concentration of b. The channel formation region 23b has an N-type source layer 31 made of an N ⁺ diffusion layer.
And a well-known double diffusion technique, whereby an N-channel region is formed on the surface of the channel forming region 23b. still,
On the surface side of the channel forming region 23b, a P ⁺ diffusion layer 32 for taking the potential of the P well 23 is formed.

The N well 22 has a low impurity concentration layer 29
And is formed so as to have a depth substantially equal to the diffusion depth of the P well 23. The surface of the N well 22 has N ⁺
A drain contact layer 33 made of a diffusion layer is formed. The N well 2 for forming the deep drain is used.
The impurity concentration of No. 2 is set to an intermediate level between the impurity concentration of the drift layer 30 and the impurity concentration of the drain contact layer 33.

A LOCOS oxide film 34 is formed between the N well 22 and the P well 23 for relaxing the electric field. A gate electrode 35 made of, for example, a polysilicon wiring film is formed at a portion corresponding to the N channel region via a gate oxide film (silicon oxide film) not shown.

The P-channel LDMOS 21 has a region (low impurity concentration layer 29) between the P well 24 and the N well 25.
Is a drift layer 36 made of a P ⁻ diffusion layer.
It has become. The drift layer 36 is also provided as a low impurity concentration layer because a relatively high resistance is required. However, the drift layer 36 is set to have a higher impurity concentration than the low impurity concentration layer 29.

The N well 25 has a low impurity concentration layer 29
, And a channel forming region 25b formed at a surface side portion so as to be continuous with the electric field relaxing region 25a. Again, in this case,
The impurity concentration of electric field relaxation region 25a is lower than the impurity concentration of channel formation region 25b. The channel formation region 25b is formed by a well-known double diffusion technique together with a P-type source layer 37 composed of a P ⁺ diffusion layer, whereby a P channel region is formed on the surface of the channel formation region 25b. Configuration.
The N well 2 is located on the surface side of the channel formation region 25b.
An N ⁺ diffusion layer 38 for taking a potential of 5 is formed.

The P well 24 has a low impurity concentration layer 29.
And is formed to have a depth substantially equal to the diffusion depth of the N well 25. A drain contact layer 39 made of a P ⁺ diffusion layer is formed on the surface of the P well 24. The P well 24 for forming the deep drain is used.
Is set to an intermediate level between the impurity concentration of the drift layer 36 and the impurity concentration of the drain contact layer 39.

The LOCOS oxide film 34 for reducing the electric field is also formed between the P well 24 and the N well 25. The LOCOS oxide film 34 is also formed on the insulating trench 15. In addition, the P
In a portion corresponding to the channel region, a gate electrode 40 made of, for example, a polysilicon wiring film is formed via a gate oxide film (silicon oxide film) not shown.

The CMOS transistor 26 has an N well 2
A P-channel MOS transistor 41 of known construction which forms the source region 41a and drain region 41b made of ^{P +} diffusion layer in the 7, to form a source region 42a and drain region 42b made of ^{N +} diffusion layer in the P-well 28 The N-channel MOS transistor 42 has a well-known configuration. In the portions corresponding to the respective channel regions in the P-channel MOS transistor 41 and the N-channel MOS transistor 42, for example, gate electrodes 41c and 42c made of a polysilicon wiring film are interposed via a gate oxide film (silicon oxide film) not shown. Is formed.

FIGS. 4 and 5 are schematic cross-sectional views showing a method of manufacturing the monolithic power IC having the above-described structure, which will be described below.

First, as shown in FIG.
Z substrate or a state in which the concentration of impurities such as boron, phosphorus, arsenic, and antimony is extremely low (1 × 10 ¹⁴ / cm
(Approximately ³ or less) CZ substrate with surface orientation of (100)
Is prepared, and a silicon oxide film 13 is formed on the surface thereof by thermal oxidation.

Next, by sequentially performing the bonding step and the polishing step, the SOI as shown in FIG.
The substrate 11 is formed. Specifically, in the bonding step, first, a mirror-finished base substrate 12 is prepared, and the surface of the base substrate 12 and the surface of the single crystal silicon substrate 43 on the silicon oxide film 13 side are subjected to a hydrophilic treatment. Is applied. Specifically, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution (H2 SO4: H
After sequentially performing cleaning with 2 O2 = 4: 1) and pure water cleaning, the amount of water adsorbed on the surfaces of the substrates 12 and 43 is controlled by spin drying. After that, the base substrate 12 and the single-crystal silicon substrate 43 are adhered to each other on the surface subjected to the hydrophilization treatment and bonded, and then integrated by performing a heat treatment.

Next, in the above-mentioned polishing step, a process of grinding and polishing the single-crystal silicon substrate 43 from the surface opposite to the bonding surface is performed until the film thickness becomes about 10 μm, thereby forming the single-crystal silicon layer 14. Then, the SOI substrate 11 is formed.

In this embodiment, the silicon oxide film 13 is formed on the single crystal silicon substrate 43 side.
A configuration in which a silicon oxide film is formed on the base substrate 12 side or on both substrates 12 and 43 may be adopted.

Subsequently, processing is performed to a state as shown in FIG. Specifically, a silicon oxide film (not shown) is formed on the surface of the single crystal silicon layer 24 by, for example, a CVD method, and thereafter, the insulating trench 15 is formed by a photolithography technique and a dry etching technique. Next, a silicon oxide film 18 having a thickness of about 0.5 μm or more is formed on the inner wall of the insulating trench 15 by a thermal oxidation method or the like, and then the insulating trench 15 is back-filled with polysilicon 19. The above-mentioned silicon oxide film (not shown) is removed by polishing or etching back, and the surface is flattened. Thus, the logic element forming region 16 and the plurality of power An element formation region 17 is formed.

Thereafter, processing is performed up to the state shown in FIG. Specifically, a mask having openings at corresponding positions of the electric field relaxation region 23a of the P well 23 for the LDMOS 20, the P well 24 for the LDMOS 21, and the P well 28 for the CMOS transistor 26 is used. In this state, ion implantation of P-type impurities and thermal diffusion are performed to form the electric field relaxation region 23a of the P well 23 and the P wells 24 and 28, and then the mask is removed. As a result of performing such a process, the depth of each of the P wells 23, 24, and 28 is set to be the same.

Next, processing is performed up to the state shown in FIG. More specifically, first, the N-well 22 for the LDMOS 20, the electric field relaxation region 25a of the N-well 25 for the LDMOS 21, and the CMOS transistor 26
N-type impurities are ion-implanted and thermally diffused in a state where masks having openings are provided at positions corresponding to the N-wells 27 and 27, respectively.
Then, an electric field relaxation region 25a of the N well 25 is formed, and then the mask is removed. As a result of performing these steps, the depths of the N wells 22, 25, and 27 are set to be the same.

Further, processing is performed up to the state shown in FIG. Specifically, the drift layer 30 of the LDMOS 20 and the drift layer 36 of the LDMOS 21 are sequentially formed by ion implantation and thermal diffusion of impurities corresponding to the respective conductivity types. The portions of the single crystal silicon layer 14 other than the drift layers 30 and 36 in the power element formation region 17 and the portions of the logic element formation region 16 other than the N well 27 and the P well 28 are low impurity concentration layers. 29.

Then, as shown in FIG. 5 (g), the LOCOS oxide film 34, a silicon oxide film for a gate oxide film (not shown),
After forming 41c and 42c, as shown in FIG. 5 (h), a technique such as a publicly known double diffusion technique is used.
Channel formation region 23b of P well 23, N type source layer 31, channel formation region 25b of N well 25, drain contact layers 33 and 39, P ⁺ diffusion layer 32, P ⁺ source layer 37, N ⁺ diffusion layer 38, source Regions 41a and 4
2a, drain regions 41b and 42b, electrodes (not shown), wiring, a surface protection film, and the like are formed to complete a monolithic power IC as shown in FIG.

The present embodiment is characterized in that a frame-shaped N well 27 including a peripheral region in contact with the insulating trench 15 is formed in the logic element forming region 16. In this case, in general, in a monocrystalline silicon, a region in which an N-type impurity is diffused has less crystal defects due to stress distortion than a region in which a P-type impurity is diffused. In the manufacturing process, in particular, in the heat treatment for forming the LOCOS 34 or other heat treatment, even if a strain due to a thermal stress occurs at the junction of the N-well 27 with the insulating trench 15, a crystal defect caused by the strain is generated. Can be reduced. Therefore, the CMOS formed in the N well 27 and the P well 28 surrounded by the N well 27
Junction leakage at the transistor 26 is suppressed, so that a decrease in characteristics of the logic circuit portion can be prevented.

Further, according to this embodiment, the N-channel LDMOS 2 as a power element is formed on the single crystal silicon layer 14.
In forming the 0- and P-channel LDMOS 21 and the CMOS transistor 26 for the logic circuit, L
The electric field relaxation region 23a and the P well 24 of the P well 23 where the DMOSs 20 and 21 are formed and the P well 28 of the logic element formation region 16 where the CMOS transistor 26 is formed are the same. It can be formed in one process using a mask, and the N well 22 and the electric field relaxation region 25a of the N well 25 on the power element forming region 17 side and the N well 27 on the logic element forming region 16 side Can be formed in a single process using the same mask, so that there is an advantage that the manufacturing process can be simplified.

Note that the present invention is not limited to the above-described embodiment, and the following modifications or extensions are possible.

The N-type impurity diffusion region may be provided at least on the surface side of the logic element formation region in a shape including a peripheral region in contact with the insulating trench. Further, a bipolar transistor may be provided as a logic circuit transistor.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram showing a basic structure of a monolithic power IC according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of the basic structure.

FIG. 3 is a schematic cross-sectional view of a completed monolithic power IC.

FIG. 4 is a schematic sectional view 1 showing a manufacturing process.

FIG. 5 is a schematic sectional view showing a manufacturing process;

FIG. 6 is a basic plan layout diagram of a logic circuit element portion formed in a conventional monolithic power IC.

[Description of References] 11 is an SOI substrate (semiconductor substrate), 12 is a base substrate,
14 is a single crystal silicon layer, 15 is an insulating trench, 16
Is a logic element formation area, 17 is a power element formation area, 20
And 21 are LDMOS (power semiconductor elements), 26 is C
MOS transistor (transistor for logic circuit), 27
Is an N-well (N-type impurity diffusion region), 28 is a P-well,
Reference numeral 34 denotes a LOCOS oxide film.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 622

Claims (4)

[Claims] An island-shaped logic element formation region (1) surrounded by an insulating trench (15) on a semiconductor substrate (11).
6), wherein the logic circuit transistor (26) is formed in the logic element formation region (16). The insulating trench () is provided at least on the surface side of the logic element formation region (16). 15) A frame-shaped N-type impurity diffusion region (27) formed including a peripheral region in contact with the region, and a state surrounded by the N-type impurity diffusion region (27) in the logic element formation region (16). And a P-well (28) formed, wherein the logic circuit transistor (26) is formed at least in the P-well (28). 2. The semiconductor device according to claim 1, wherein said logic circuit transistor is formed in both said P well and said N type impurity diffusion region. 3. An island-shaped power element formation region (17) surrounded by an insulating trench (15) is provided on the semiconductor substrate (11), and an N-type impurity on the side of the logic element formation region (16) is provided. The depth of the diffusion layer (27) and the N for the power semiconductor elements (20, 21) formed on the power element formation region (17) side.
3. The semiconductor device according to claim 1, wherein the wells have the same depth as the wells. 4. An island-shaped power element formation region surrounded by an insulating trench (15) is provided on the semiconductor substrate (11), and a P-well (28) on the side of the logic element formation region (16) is provided. The depth and the P well (2) for the power semiconductor elements (20, 21) formed on the side of the power element formation region (17).
4. The semiconductor device according to claim 1, wherein the depth of the semiconductor device is set to be the same as that of the semiconductor device.