JPH11296155A - Display device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device and its control method in which a very precise resolution is maintained and an animation display is conducted without having picture flaws and unnatural displays. SOLUTION: A digital still camera 10 speedingly conducts a data transfer by controlling the inputting and the outputting of the data supplied to three frame buffers 20a to 20c of a frame memory section 20 by a DMA 18a, a control section 18b and a CPU 18c of an input output control section 18 and avoids the occurrence of a double access to a single frame buffer. Moreover, data are accurately displayed on a liquid crystal display section 24b of a display system 24 by synchronizing the data handled in a line buffer section 22 for every prescribed unit and conducting the inputting and the outputting under the control of the section 18b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a control method for a display device capable of improving a difference between data input / output rates and displaying data normally, and more particularly to a display device having a high number of pixels. It is suitable for use in a digital still camera or the like having a high-definition resolution that requires time for reading because of the number of pixels.

[0002]

2. Description of the Related Art Data to be supplied is obtained corresponding to pixels, which are displayed on a screen as a group of image points, that is, dots. It is also known that, when a screen is constructed, by using a large number of these pixels for display, the image quality can be enhanced, and the resolution of the image quality can be enhanced if the dot pitch is narrow. In this way, one (still) image is generated. Further, in order to control a plurality of images to be displayed within a certain period of time, access to data management in a memory related to circumstances and processing that are difficult to obtain for a high-speed processing device used for these processing and data input / output are performed. It is known that there is a problem that display is restricted by double access to the memory such as access for the purpose.

Therefore, Japanese Patent Laying-Open No. 6-124073 proposes to enable continuous reproduction of high-quality moving images with a low-speed memory. Further, Japanese Patent Application Laid-Open No. 6-215120 proposes a system having a high display capability to provide at a low cost and a problem of double access. They propose to display moving images as an asynchronous movie system, which cannot be displayed in real time. This method will be briefly described. For example, when one of two memories is written for each field / frame, the other memory is also used for a read process for each field / frame. It is performed alternately for the memory. At this time, the synchronization relationship between the vertical synchronizing signal VI on the data supply side and the vertical synchronizing signal VD of the display device must be an integral multiple.

[0004]

Problems to be solved by the invention
In the proposals of Japanese Patent No. 4073 and Japanese Patent Application Laid-Open No. 6-215120, when there is a difference between the number of pixels and the input / output rate of the input data and the output data to be used, it is easy to simply switch the memory to solve the problem. I understand. That is, if the number of pixels is not substantially the same, the display screen will be shifted or an unnatural screen will occur, and if the input data rate is slower than the output display data rate, a screen with no data will occur. I will. This is because if the synchronization relationship between the vertical synchronizing signal VI and the vertical synchronizing signal VD is not an integral multiple, the screen display is shifted. Since it is necessary to avoid such a disconnection state of the video signal, in this case, a display longer than the specified display, that is, the same screen is repeatedly displayed to deal with it. However, depending on a series of these processes, the display may be shifted due to delay due to recording / reproducing or extra repetitive display. In other words, it can be seen that the above proposal is valid only when the input data rate is higher than the reproduction data rate.

[0005] It is known that a high-resolution digital still camera having, for example, hundreds of thousands of pixels or more has the same relationship as this phenomenon. More specifically, even if two frame buffers are provided for an image, since the synchronous relationship between the vertical synchronizing signal VI and the vertical synchronizing signal VD is not an integral multiple, a double access state is created, so that reproduction is performed. When the timing of screen switching and the start of imaging, that is, the vertical synchronization signal VI does not match, imaging of one screen is paused, and shooting is resumed after the next vertical synchronization signal VD is supplied. The number (the so-called frame number) decreases. Even if emphasis is placed on a clear image display, if such asynchronous playback of a movie is performed, a moving resolution cannot be obtained due to this cause.

The present invention solves the above-mentioned drawbacks of the prior art, and provides a display device and a control method for the same which can display a moving image so as to maintain a dynamic resolution and prevent image dropout and unnatural display. The purpose is to:

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention controls the input / output of supplied data with different rates of taking in the supplied data and reading rates of the taken data. And a buffer device including at least three or more storage units for temporarily storing supplied data, and a buffer unit for supplying data to the buffer unit. Input / output control means for controlling the input / output of data to be input, and data holding means for holding the data of the predetermined unit by handling the data supplied under the control of the input control means for each predetermined unit. And displaying the data supplied based on the output from the data holding means on the display means.

Here, it is preferable that the storage means has a data capacity of one screen or more required for displaying the storage capacity by the display means. This makes it possible for each storage unit to satisfy one of the conditions for the double access avoidance request for simultaneously performing the writing and reading processes when displaying an image.

The input / output control means includes a first control means for controlling the transfer of data handled by the storage means of the buffer means, a second control means for performing input / output management of data for providing a synchronous relationship with the data, It is desirable to have third control means for controlling the operation timing of the first and second control means. By performing decentralized control, the load on each control can be reduced, and in particular, the control of the third control means can be reduced, and various data processing can be performed quickly.

The buffer means uses one or two of the storage means for storing data under control of the input / output control means, uses the rest of the storage means for reproduction, and stores and stores the data. It is advantageous if the data is reproduced simultaneously. By specifying the use of the storage means in this way, for example, even if the transfer rate of the supplied data is lower than the transfer rate of the display data, the data amount of the rate difference can be reasonably compensated for by one storage means. Double access can be avoided.

In the display device according to the present invention, the input / output of the data supplied to the three storage units of the buffer unit is controlled by the input / output control unit, thereby avoiding double access to one storage unit. The data can be accurately displayed on the display unit by inputting and outputting the data handled by the data holding unit in synchronization with each predetermined unit.

Further, the present invention provides a data management system by controlling input / output of supplied data in which the supplied data capture rate and the captured data read rate are different, so that a continuous screen of data is obtained. A method of controlling a display device for performing display, wherein input / output control means for controlling input / output of data to / from buffer means including at least three or more storage means for temporarily storing supplied data is provided. When used, a transfer rate difference investigating step for examining a difference between the data taking-in rate and the data reading rate of the taken-in data, and one or more of the storage means according to the result of the transfer rate difference examining step. An operation designating step of designating an operation using two for data fetching and using the rest of the storage means for data reading;
An input / output control step of handling data supplied under the control of the input / output control means or data output from the buffer means for each predetermined unit, dividing the data into the predetermined units, and adjusting timing to perform input / output. And a display step of displaying the data whose timing has been adjusted in the input / output control step on a screen.

In the operation specifying step, when the difference between the data fetching rate in the transfer rate difference checking step and the reading rate of the fetched data is negative, the two storage means are always used for data fetching. It is preferable to manage the buffer means by shifting the operation specification of the buffer means while performing the operation specification. As a result, it is possible to prevent the fetch / read processing for one storage unit from being simultaneously performed.

The input / output control step desirably includes storing the data transferred from the storage means or transferring the data to the designated storage means of the buffer means in accordance with the control of the input / output control means. As a result, the supplied data and output data are subjected to timing adjustment, and each line or screen can be accurately displayed without any shift during display.

In the display step, it is preferable to switch the screen by synchronizing the data whose timing has been adjusted in the input / output control step with a vertical synchronization signal which is one of predetermined units. As a result, it is possible to make the change of the displayed screen natural without any discomfort.

According to the control method of the display device of the present invention, the difference between the input and output data transfer rates is checked in a transfer rate difference check step to detect a shift in the vertical synchronizing signal between the input and output. According to the result of (1), one or two of the storage means are used for data fetching, and the remaining storage means are used for data reading (operation specifying step). / Collecting of read processing, that is, simultaneous processing is avoided, and data supplied under the control of the input / output control means in the input / output control step or data output from the buffer means are handled in predetermined units, and By displaying the data, which has been classified into timings and the timing of which is adjusted, on the display means, the number of supplied screens can be matched between the input and output, and image display is interrupted. Strangely it can display video.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a display device and a control method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

The display device of the present invention is effective, for example, when there is a difference in transfer rate between input and output, particularly when the input rate for taking in data is slower than the output rate for outputting data. The feature is that the state of double access to one memory is prevented. In the present embodiment, a case where the present invention is applied to a digital still camera will be described with reference to FIGS.

The digital still camera 10 has a function of photographing and recording, displaying an image of a scene photographed with respect to display, and reproducing and displaying an already photographed and recorded image. As shown in FIG. 1, the digital still camera 10 includes an imaging system 12 and a signal generation unit so as to exhibit this function.
14, a data processing unit 16, an input / output control unit 18, a frame memory unit 20, a line memory unit 22, and a display system 24.

The imaging system 12 includes a CCD 12a, an A / D converter 12b
Is provided. Although not shown in FIG. 1, the imaging system 12 is provided with an optical system, and a color filter is provided immediately before the CCD 12a to obtain a color image. CCD
Reference numeral 12a photoelectrically converts light supplied through the color filter in accordance with the amount of light. This photoelectric conversion device includes:
For example, Charge Coupled Device
Is used.

Generally, pixels corresponding to color filters are arranged on the image pickup surface. Recently, there have been provided devices with a large number of pixels in which hundreds of thousands or millions of such pixels are formed within a predetermined area in order to obtain a high-quality image.
When the CCD 12a has such a high number of pixels, it takes a very long time to output signal charges after imaging. Further, the A / D converter 12b converts an analog electric signal obtained from the CCD 12a into a digital signal.

The signal generator 14 includes an image pickup system signal generator 14a.
And a recording / reproducing system signal generator 14b. The signal generation unit 14 has a signal generation source (not shown) in either the imaging system signal generation unit 14a or the recording / reproduction system signal generation unit 14b. In FIG. 1, this signal generation source is provided in the imaging system signal generation section 14a, and the generated signal is supplied to the recording / reproduction system signal generation section 14b. The imaging system signal generation unit 14a
A drive signal for driving the D 12a, a conversion clock for the A / D converter 12b, and the like are generated and supplied. The components of the imaging system 12 described above operate according to the signal supplied from the imaging system signal generation unit 14a.

The recording / reproducing system signal generator 14b generates various timing signals used in recording / reproducing and signal processing based on the signal supplied from the imaging system signal generator 14a. This timing signal is supplied to the data processing unit 16 and also to the system bus 100. This timing signal is supplied to each unit via the system bus 100. The system bus 100 includes a plurality of data buses and various control signal lines.

The data processing section 16 performs various processes on the image data supplied from the imaging system 12 and the data supplied from the frame memory section 20 and the line memory section 22 under the control of the input / output control section 18. Apply. The data processing unit 16 outputs, for example, imaging data to the system bus 100 under the control of the input / output control unit 18. The imaging data and the like are supplied to the frame memory unit 20 via the system bus 100. The data processing unit 16 also checks the difference between the rate of the input data and the rate of the output data.

For example, when the image data is simply displayed on the display system 24, the data processing section 16 performs an interpolation process on the position of the image data having no pixels, that is, the (color) data of the void pixels, and performs the interpolation of the three primary colors RGB. Performs YC conversion processing from the data. Further, the signal subjected to the YC conversion processing is displayed on the display system 24.
The data processing unit 16 receives an encoding process according to the standard. In addition, when recording photographing data, the data processing unit
16 performs compression processing on the photographing data. When reproducing the imaged data which has already been recorded after receiving the compression processing, the reverse processing to the compression processing, that is, the expansion processing is performed.
The data processing unit 16 is controlled by the control unit 18b of the input / output control unit 18 as described later.

The input / output control unit 18 includes a DMA controller (Direct Memory Access Controller: hereinafter simply referred to as DMA) 18a, a control unit 18b, and a CPU (Central Processing).
The unit has 18c. DMA 18a
Controls the data transfer according to the input request signal and the output request signal to the frame memory unit 20 and the line memory 22. The control unit 18b controls input / output so that data in the line memory unit 22 is synchronized with, for example, a horizontal synchronization signal or a vertical synchronization signal. The control unit 18b receives the signal indicating the operation state supplied from the line memory unit 22, and outputs a corresponding request signal. The CPU 18c controls operations of the DMA 18a and the control unit 18b. The operation of the input / output control unit 18 will be further described later.

The frame memory section 20 includes three frame buffers 20a to 20c. Each of the frame buffers 20a to 20c has a memory capacity exceeding one screen displayed by the display system 24.

The line memory section 22 includes a reproduction line memory section 22a and a recording line memory section 22b. Further, each of the reproduction line memory unit 22a and the recording line memory unit 22b is provided with two line buffers each having at least a capacity of one line, which is an upper element constituting an image. Reproduction line memory unit 22
a is provided with line buffers 220a and 222a, and the recording line memory unit 22a is provided with line buffers 220b and 222b. Here, since the line buffers of the reproduction line memory unit 22a and the recording line memory unit 22b do not cause a collision such as a double access under the control of the DMA 18a, only two lines can be used.

The display system 24 includes a D / A converter 24a and a liquid crystal display 24b. The D / A converter 24a converts the digital video signal that has been subjected to the encoding process from the data processor 16 into an analog signal. After this conversion, the video signal is supplied to the liquid crystal display unit 24b. LCD display 24b
Displays an image captured in synchronization with the horizontal synchronization or vertical synchronization of the video signal.

Next, the operation of the digital still camera 10 will be described with reference to the block diagram of FIG. 1 and the schematic diagram of FIG. Digital still camera
In a mode 10, although not shown, a mode in which the object scene is captured as an optical image by an operation input unit and the image is electrically displayed as a moving image is selected. In addition to the moving image display mode, the digital still camera 10 has a still image display mode, for example. A mode signal indicating the selection of the moving image display mode is supplied from the operation input unit to the CPU 18c of the input / output control unit 18 via the system bus 100 in FIG.

The CPU 18c operates the signal generator 14 via the system bus 100. The imaging system signal generation unit 14a of the signal generation unit 14 outputs a drive signal of each unit and a timing signal such as a conversion clock to the imaging system 12. The CCD 12a supplies the read signal to the A / D converter 12b. A / D converter 12b
Converts the supplied signal into a digital signal and outputs the digital signal to the data processing unit 16. The data processing unit 16 takes in the supplied digital signal under the control performed by the CPU 18c via the system bus 100, and performs various signal processing. To capture data, the recording / playback signal generator
The timing signal supplied from 14b is used. Interpolation processing and the like for the void pixels as described above are performed on the captured data. When displaying and recording data, the data processing unit 16
Also performs compression processing.

Here, the CPU 18c controls the data processing unit 16 as described above, and also controls the DMA 18a via the system bus 100. In this case, CPU 18c
Start 18a. For this activation, either an input request signal or an output request signal is supplied as a DMA transfer request signal. The DMA 18a transfers the output data from the data processing unit 16 to the frame memory unit 20 via the system bus 100 by DMA under this control.

The frame memory section 20 stores 3
Initial state setting is performed for each of the frame buffers 20a to 20c in consideration of the rate difference in the data processing unit 16. For example, the operation is performed by setting the frame buffer 20a as an input and setting the frame buffers 20b and 20c as an output. When the rate difference due to data input / output, that is, (input rate)-(output rate) is negative, it is preferable to set the above input / output setting.

Further, generally, the input / output settings of the three frame buffers 20a to 20c are set so that one of the three adjacent buffers to the center buffer among the three input / output buffers is set to the same value. The other has different settings. At this time, the buffer located at the center must operate as an output after the input is completed, for example. As a result, the buffers located at both ends are always processed by the input and the output, and the setting of this input / output is performed. Since the relationship rotates cyclically between the three buffers, collisions of writing and reading to one buffer at the same time, such as double access, are avoided. Further, specific examples will be described later.

When the data fetched in this manner is read out from, for example, one frame buffer 20c, the frame buffer 20c is controlled by the DMA 18a to control the line buffer of the reproduction line memory 22a of the line memory 22.
It is supplied to one of 220a and 222a via the control unit 18c. The control unit 18c is provided with the supplied line memory unit for reproduction.
One line of 22a is fetched, and one line of data that has already been read is operated in synchronization with the horizontal synchronization signal and the vertical synchronization signal.

In this display mode, the data output from the reproduction line memory unit 22a is, for example,
The data is sent to the data processing unit 16 under the control of a. The data processing unit 16 performs the above-described YC conversion processing and encoding processing on the supplied data, and then outputs the data to the display system 24. The display system 24 converts the supplied data into an analog signal by the D / A converter 24a. The converted analog signal is a video signal suitable for the current broadcasting system. D / A converter 24a
Supplies this video signal to the liquid crystal display unit 24b. The liquid crystal display unit 24b is mounted on the housing of the digital still camera 10. The screen is formed by the video signal scanning the liquid crystal display section 24b.

Also, in the case of the reproduction mode for reproducing the image data (hereinafter, simply referred to as data) which has already been recorded, the CP
The U 18c activates and controls the DMA 18a, and also controls the controller 18b. When displaying the read data on the liquid crystal display unit 24b, the control unit 18b sends data from a recording medium (not shown) to the reproduction line memory unit 22a once, though not shown. At this time,
The control unit 18b manages input / output including data synchronization adjustment so as to synchronize with the horizontal synchronization signal and the vertical synchronization signal.

The data is supplied to the data processing section 16 under the control of the DMA 18a. The data processing unit 16 performs a decompression process for decompressing data. The data after this processing is DM
The signal is supplied to the frame memory unit 20 under the control of A 18a. As a result, the DMA 18a manages the input / output of the frame memory unit 20. That is, for example, DMA 18a
Designates one of the three frame buffers 20a to 20c, and designates a predetermined address as a transfer destination. Data is transferred to the frame memory unit 20 by this series of processing. Thereafter, the transferred data is read from the frame buffer and displayed on the liquid crystal display unit 24b via the data processing unit 16 and the D / A conversion unit 24a.

For recording, the data supplied from the image pickup system 12 to the frame memory unit 20 via the data processing unit 16 is controlled by the DMA 18a for each line at a predetermined address. Transferred to 16. The data processing unit 16 compresses the transferred data and transfers the data to the recording line memory unit 22b via the system bus 100. During this transfer, the data is transferred to the DMA 18a,
Under the control of 18b, it is supplied to the recording line memory unit 22b. The control unit 18b controls data supply to the recording medium so that double access does not occur by alternately performing the input / output control of the line buffers 220b and 222b of the recording line memory unit 22b. The recording / reproducing device (not shown) writes data under the control of the control unit 18b or the CPU 18c. For example, when the recording / reproducing device is a semiconductor memory, data access control can be completed, so the controller 18b is used, and when a complicated drive control such as an optical recording medium or a magnetic recording medium is required, the CPU 18c It is preferable to use The digital still camera 10 operates in a controlled manner as described above, so that an image is displayed and displayed,
Playback display of recorded data is being performed.

The fact that double access can be effectively prevented by applying the present invention will be described more specifically with reference to the schematic diagram of FIG. FIG. 2A illustrates the flow of signals in the display of photographing data in the digital still camera 10.
The vertical synchronizing signal VI in FIGS. 2B and 2C is a timing signal supplied from the imaging system signal generator 14a in FIG. Also,
The vertical synchronizing signal VD shown in FIGS. 2B and 2C is the same signal as the vertical synchronizing signal of the current broadcast system, for example, supplied from the recording / reproducing system signal generator 14b.

Here, the CCD 12a captures three consecutive images. These images are referred to as A-side, B-side, and C-side, respectively.
The CCD 12a, as shown in FIG.
The vertical sync signal VI is output for each screen. CCD 12a
Captures an image and starts imaging at time t ₁ in synchronization with the vertical synchronizing signal VI (A plane). The fetched data is subjected to various processes, and is transferred to the frame buffer 20a set as the input by DMA under the control of the DMA 18a. The frame buffer 20a is in a write enable state.
Data to be output to the data and display (playback) system 14 from the imaging system 12, since the asynchronous relationship with each other, during the period from time t ₁ to time t ₂ when the next vertical synchronizing signal VI is supplied, the frame The buffers 20b and 20c are in a read enable state as time elapses (B-plane and C-plane). Also, the frame buffer 20b is in a standby state after the data reading is completed, and after fetching the data of the frame buffer 20a,
And is specified in a write enable state in synchronization with the vertical synchronizing signal VI at time t ₂ indicating the start data acquisition of the frame buffer 20b. Frame buffer 20a will read enable state at time t ₃ in synchronization with the vertical synchronizing signal VD.
It can be seen that the same operation state of the frame buffers 20a and 20b does not overlap.

[0042] Results Focusing on the time difference between the time t ₂ and time t _3, the time difference, which has absorbed the transfer rate difference in output by controlling the frame buffer 20b, and 20c in a different operating mode frame buffer 20a Means the time difference. At this time, the frame buffer 20c functions as a buffer for compensating the transfer rate difference. This allows the frame buffer 20a to access only a single function during this period.

[0043] At time t ₂ the next vertical synchronizing signal VI is supplied, as described above, the imaging system in the frame buffer 20b 12
, Data supply is started. Frame buffer 20b
During the period from the time t ₂ to capture data until time t _4, the frame buffer 20c, 20a is reading data. From the above relationship, the frame buffer 20a becomes a buffer for the compensation function during this period. As described above, among the buffers remaining for the buffer during data input, the buffer that operates later is borne by the buffer for compensation. Then, the DMA 18a moves this role in synchronization with the vertical synchronization signal VI, and the three frame buffers 20a to 20c
It is carried around in.

On the other hand, although not shown, the frame buffer 20a,
In the conventional configuration having only two 20b, data is input and output at the timing shown in FIG. 2 (c). In this case, at time t ₁ in synchronization with the vertical synchronizing signal VI is data in the frame buffer 20a from the imaging system 12 initiates the imaging is supplied. By the transfer rate due to the input data is slower than the transfer rate of the output, the frame buffer 20b is a switching time S ₁ in synchronization with the vertical synchronizing signal VD is also matter have completed the dihedral output B surface Since the frame buffer 20a has not yet completed data capture,
Output the side B and control the output so that the display is not interrupted.
After the data input to the frame buffer 20a is completed at time t _2, DMA 18a also turn completes the reading of the frame buffer 20b is data as attempts to switch control to the write enable state frame buffer 20b from the read-enable state immediately Operation mode cannot be switched. This is because if the switching is forcibly performed, the frame buffer 20b is simultaneously subjected to the dual access control.

[0045] Therefore, to prevent such access, when the frame buffer 20a at time t ₂ the output operation of the frame buffer 20b is a vertical synchronizing signal VI after completion is also supplied to end data acquisition (time t ₄ ) until DM
A 18a cannot put the frame buffer 20b into the write enable state. As a result, the frame buffer
20a, as shown in FIG. 2 (c), it is not possible to switch the screen to the time t _5, thereby displaying a surface A five consecutive. For this reason, the moving image to be displayed is not switched at regular intervals, and the screen display has a reduced dynamic resolution.

However, in the digital still camera 10 to which the present invention is applied, since the double access can be prevented and the screen display can be switched almost at regular intervals as described above, a decrease in the dynamic resolution can be prevented. Such a problem can be solved by performing this control even if it is required to use an imaging device having a still higher number of pixels in the future.

With the above configuration, the vertical synchronization signals VI and VD do not have a relationship of an integral multiple (completely asynchronous),
Even if the data input rate is slower than the output (or playback) rate, double access is prevented and data input / output is performed by adding one frame buffer and controlling the total to three. Can be performed without interruption, so that the displayed image can be displayed as a more natural moving image, and the moving resolution of the moving image can be made higher than that of the conventional moving image. The function can be greatly improved without increasing the cost simply by adding the simple components.

[0048]

As described above, according to the display device of the present invention,
The input and output of the data supplied to the three storage units of the buffer unit are controlled by the input / output control unit, and the storage unit for the captured image and the output image are separated to avoid double access to one storage unit. By compensating for the difference in the data transfer rate and accurately displaying the data synchronized with each data handled by the data holding means for each predetermined unit, the moving image display is more natural and more dynamic than before. It can be displayed as a high-resolution video. The function can be greatly improved without increasing the cost simply by adding the simple components.

According to the control method of the display device of the present invention, the difference between the input and output data transfer rates is checked in the transfer rate difference check step to detect that there is a shift in the input / output vertical synchronizing signal. In accordance with the result of the process, one or two of the storage means are used for data fetching, and the remaining storage means are used for data reading (operation specifying step). The collision of write / read processing, that is, simultaneous processing is avoided, and the data supplied under the control of the input / output control means in the input / output control step or the data output from the buffer means are handled for each predetermined unit, and By displaying the data which is divided into units and the timing is adjusted on the screen on the display means and the number of supplied screens is matched between the input and the output, the image display is not interrupted. Since it displaying a moving image, it is possible to obtain a high video of dynamic resolution than the natural conventionally. By adding in consideration of such simple control, the function can be greatly improved without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration when a display device of the present invention is applied to a digital still camera.

FIG. 2 is a timing chart schematically showing a relationship between data captured by imaging and data read out for display in the digital still camera of FIG.

[Explanation of symbols]

 10 Digital still camera 12 Imaging system 14 Signal generation unit 16 Data processing unit 18 I / O control unit 20 Frame memory unit 22 Line memory unit 24 Display system 18a DMA 18b Control unit 18c CPU 20a to 20c Frame buffer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/36 510 G09G 5/36 510M H04N 5/66 H04N 5/66 B // H04N 5/225 5 / 225F

Claims (8)

[Claims] A display for performing continuous data display by performing data management by controlling the input / output of supplied data in which the supplied data capture rate and the captured data read rate are different. An apparatus, comprising: buffer means including at least three or more storage means for temporarily storing supplied data; and input / output control for controlling input / output of data supplied to the buffer means. Means for handling data supplied under the control of the input control means for each predetermined unit, and data holding means for holding the data in the predetermined unit, and supplying the data based on an output from the data holding means. A display device for displaying the data to be displayed on display means for displaying the data. 2. The display device according to claim 1, wherein said storage means has a storage capacity of one screen or more required for display by said display means. 3. The apparatus according to claim 1, wherein said input / output control means provides a synchronous relationship between said data and a first control means for controlling transfer of data handled by a storage means of said buffer means. A display device comprising: a second control unit that performs data input / output management; and a third control unit that controls operation timings of the first and second control units. 4. The apparatus according to claim 1, wherein the buffer means uses one or two of the storage means for storing data under the control of the input / output control means.
A display device, wherein the rest of the storage means is used for reading and reproducing data, and the storage of the data and the reproduction of the data are simultaneously performed. 5. A display for performing data management by controlling the input / output of supplied data, wherein the supplied data capture rate and the captured data read rate are different, so that a continuous screen display of the data is performed. A method for controlling an apparatus, the method comprising: input / output control means for controlling input / output of data to / from buffer means including at least three storage means for temporarily storing supplied data; If used,
A transfer rate difference check step for checking a difference between the data capture rate and a read rate of the captured data; and storing one or two of the storage means in accordance with a result of the transfer rate difference check step. An operation designating step of designating an operation used for taking in and using the rest of the storage means for data reading; and a method for converting data supplied under the control of the input / output control means or data output from the buffer means into a predetermined unit. An input / output control step of inputting / outputting data by classifying the data into the predetermined unit and adjusting the timing, and a display step of displaying data adjusted in the input / output control step on a screen. Characteristic control method of a display device. 6. The method according to claim 5, wherein, in the operation specifying step, when the difference between the data acquisition rate and the data readout rate in the transfer rate difference examination step is negative, the storing is performed. A method of controlling a display device, characterized in that the operation of the buffer means is sequentially shifted while the operation of the two means is set to take in data, and the operation of the buffer means is managed. 7. The input / output control method according to claim 5, wherein the input / output control step includes storing the data transferred from the storage means or transferring the data to the designated storage means in the buffer means. A method for controlling a display device, the method comprising performing according to control of a means. 8. The method according to claim 5, wherein, in the displaying step, the screen is switched by synchronizing data adjusted in timing in the input / output control step with a vertical synchronization signal which is one of the predetermined units. A method for controlling a display device, comprising: