JPH11297074A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: The present invention relates to a semiconductor memory device, and more particularly to a reduction in load on a read bus. The read bus is divided into two, eight lines D11 to D18 connected to the block BA1 and eight lines D21 to D28 connected to the block BA2. Further, the read buses D11 to D18 have eight output circuits C
11 to C18, respectively, and the read bus D21
To D28 are connected to eight output circuits C21 to C28. Output circuits C11 and C21 and C18 and C28
Are connected by output wirings F1 and F8, respectively. [Effect] Since the load capacity of the read bus can be almost halved,
This has the effect of shortening the read time. Further, since a memory having an output data width of 2 bits can be easily configured from a memory having an output data width of m bits by changing the wiring layer, the memory can be easily designed and the design time can be shortened. is there.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a reduction in load on a read bus.

[0002]

2. Description of the Related Art FIGS. 3 and 4 show a conventional semiconductor memory device having an output data width of 8 bits. FIG. 3 shows the system L
FIG. 2 is a schematic block diagram showing a memory cell array and an output circuit of a memory configured as a macro cell for SI, and shows only blocks and signals necessary for description. M1 is a memory macro cell having an output data width of 8 bits. Reference numeral 1 denotes a main row decoder, which is a memory block BA1 in which n sub-memory blocks A11 to A1n are arrayed to the left with respect to the row decoder 1;
A memory block BA2 configured by arraying sub memory blocks A21 to A2n is arranged on the right of the row decoder 1 symmetrically to A1. B11, B1n, B2
1, B2n is a sub-memory block selection signal, which selects one sub-block from 2n sub-memory blocks during operation. FIG. 4 is a schematic block diagram of the sub memory block A11. Sub row decoder SRD
Decodes the output signal of the main row decoder and the sub-block selection signal B11 and drives one of the word lines WL. Each memory cell MC is connected to a bit line pair BL and XBL and a word line WL. PC is a bit line load and precharge circuit, and is connected to each bit line pair. DB
1, XDB1 and DB8, XDB8 are data bus pairs, and CG is a column gate. CT1 and CT2 are column selection signals, and control the ON / OFF of the column gate CG to electrically connect the bit line pair selected by the column address to the data bus pair. S11 to S18 are eight sense amplifiers corresponding to an output data width of 8 bits of the memory, and each has eight pairs of data buses DB1, XDB1 to DB8, XDB8 as inputs. The sense amplifiers S11 to S18 are activated by the sub memory block selection signal B11, amplify data of a memory cell located at the intersection of a word line and a bit line selected at the time of reading, and output the amplified data to the read buses D11 to D18. C11 to C18 in FIG. 3 are eight output circuits, which receive the output of the sense amplifier via eight read buses D11 to D18 traversing the memory block in the X direction, and Output to external data output lines F1 to F8.

[0003]

However, in the output circuit having the above-described configuration, the read buses D11 to D18 are wired across the entire memory block in the X direction.
The wiring length in the X direction that occupies most of the wiring length is L1 + L2
+ L3, which increases the load capacity of the wiring. Furthermore, since a total of 2n outputs of the sense amplifiers in each sub-memory block are connected to each read bus, 2n drain capacitances at the output terminals of the sense amplifiers are added, and the load capacitance increases. That is, there is a big problem in increasing the speed of the memory. As a means for solving this problem, a method as shown in FIG. 5 has been proposed. In FIG. 5, read buses D11 and D21 and D18 and D28 are divided into left and right blocks by selection switches T11, T21 and T18, T28, respectively, and connected to an output circuit by wirings H11 and H18. T11, T18, T2
1 and T28 control signals J1, J in synchronization with a block selection signal for selecting BA1 or BA2.
2, the number of sense amplifiers connected to the read bus D11 is halved to n, and the drain capacitance due to the output of the sense amplifier can be reduced by half. However, as for the reduction of the wiring length, a problem remains that the conventional wiring capacity cannot be reduced to half because a new wiring H11 is required. In addition, there remains a problem that the load capacity and the number of elements increase due to the addition of the switch.

[0004]

SUMMARY OF THE INVENTION The present invention provides a memory cell array in which memory cells are arranged in a matrix, a column gate connected to a bit line end of the memory cell array, and a sub-word whose output is connected to a word line. A sub-memory block is constituted by a line decoder, a bit line load and precharge circuit, and a sense amplifier connected to the column gate, and two memory blocks each having an array of n sub-memory blocks are arranged. In a semiconductor memory device symmetrically arranged around a row decoder block and the same number of sense amplifiers in the sub memory block as the output data width m of the memory, the 2n sub blocks are operated by a sub memory block selection signal. One of the sub-blocks is selected, and m with a single memory block
The outputs of the × n sense amplifiers are connected in common by n each via m read buses and connected to the inputs of m output circuits, and the m read buses and the m output circuits Are independently configured in units of the two memory blocks, and outputs of the m output circuits independently configured in units of the two memory blocks are commonly connected by m data output lines. It is characterized by the following.

Further, according to the present invention, means for disconnecting the m data output lines and switching of the sub-block selection signal so as to simultaneously select one sub-memory block of each of the two memory blocks. Means are constituted by metal wiring layers, and the same bulk is used to output m bits and 2 bits.
A memory having two types of output bit widths of an m-bit output can be configured.

[0006]

According to the above construction of the present invention, the read bus is connected to two buses.
By dividing the read bus, the load capacity of the read bus can be almost halved, so that the read time can be shortened.

Further, according to the above configuration of the present invention, a memory having an output bit width of m bits and the same load capacitance of the read bus can be used only by changing the wiring layer using the same bulk.
There is an effect that an m-bit memory can be easily configured.

[0008]

FIG. 1 shows a first embodiment of the present invention. The present embodiment is a case where the present invention is applied to the above-described conventional example, and the same reference numerals are given to portions corresponding to the conventional example, so that the description thereof will be omitted, and the features of the present invention will be described. The read bus D is connected to the memory block BA1.
It is divided into two, eight from 11 to D18 and eight from D21 to D28 connected to the memory block BA2. Further, the read buses D11 to D18 are connected to eight output circuits C11 to C18 corresponding to a data width of 8 bits, respectively. Similarly, the read buses D21 to D28 are connected to eight output circuits C21 to C28. Outputs of the output circuits C11 to C21 and outputs of C18 and C28 are connected by output wirings F1 and F8, respectively. The outputs of the output circuits C11 to C18 and C21 to C28 are controlled by control signals E1 and E2, respectively. The control signals E1 and E2 are signals synchronized with the sub memory block selection signals B11 to B1n and B21 to B2n, respectively, and control the output to an enable state or a high impedance state. That is, one of the sub memory block selection signals from B11 to B1n is activated,
When any one of the sub-blocks in the memory block BA1 is selected, the control signal E1 is selected and C
The output circuits from 11 to C18 are activated to enter the enable state. At this time, since the control signal E2 is in the non-selection state, the outputs from C21 to C28 are in a high impedance state, and 8-bit data of the memory block BA1 is output to the data output lines F1 to F8. In this embodiment, the selection output circuit is connected to the memory blocks BA1 and BA1.
Since eight lines are provided for each of the two lines, there is no need to provide a line corresponding to a new line H11 for connecting the read bus and the output circuit as shown in FIG. Therefore, the length of the conventional read bus in the X direction is L1 + L2 + L3.
What was needed is only L1. Here, by adding eight output circuits from C21 to C28, a drain capacitance equivalent to one output circuit is added to the output wirings F1 to F8 as compared with the conventional case.
Since F8 is connected to another macro cell such as a CPU as a data bus on the chip, for example, the wiring load capacitance is about 1 pF, while the drain capacitance of the output circuit is about 20 fF, which is negligibly small. There is almost no effect on the reading speed. Therefore, by dividing the read bus, the drain capacitance of the sense amplifier can be halved and the wiring length of the read bus can be almost halved at the same time, and the reading time can be shortened.

FIG. 2 shows a second embodiment of the present invention. FIG.
2 is a schematic block diagram when a memory macro cell having an output data width of 16 bits is formed using the same bulk as the memory macro cell having an output data width of 8 bits shown in FIG. As the output data width doubles from 8 bits to 16 bits, one address is reduced. Therefore, n sub memory block selection signals B11 to B1n separated in FIG. 1 and B21 to B2n B11 to B11
The number is up to 1n. Further, for the outputs from the output circuits C11 to C18 and the outputs from C21 to C28, a total of 16 data output lines from F1 to F8 and from F9 to F16 are provided. Further, the selection signals E1 and E2 of the output circuit of FIG. 1 become unnecessary. Here, the read operation will be described. For example, if the sub-memory block selection signal B11 is selected, the sub-memory block A11 in the memory block BA1 and the sub-memory block A21 in the memory block BA2 are selected at the same time, and the data of 8 bits each is stored in D11 to D18 and The data is output to the data bus from D21 to D28, and 16-bit data is output to the data output lines from F1 to F16 via the output circuits C11 to C18 and C21 to C28. Here, since the configuration of the read bus of FIG. 1 is the same as that of FIG. 2, even if the output data width is doubled, the delay time due to the read bus is the same. Further figure
The change of the output data width from 1 to FIG. 2 can be realized by only adding and deleting wiring. Therefore, since it can be easily realized by changing only the wiring layer, two types of memories having the same read bus load capacity and having output data widths of m and 2 m can be designed easily and in a short time.

[0010]

As described above, according to the above configuration of the present invention, the load capacity of the read bus can be substantially reduced by providing the number of output circuits corresponding to the bit width in units of two divided memory blocks. Since the reading time can be reduced by half, there is an effect of shortening the reading time.

According to another configuration of the present invention, a memory having an output data width of m bits and a memory having an output data width of 2 m bits having the same load capacity of the read bus can be constituted only by changing the wiring layer. This has the effect of facilitating design and reducing design time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a first conventional example.

FIG. 4 is a block diagram of a first conventional sub memory block.

FIG. 5 is a block diagram showing a second conventional example.

[Explanation of symbols]

1 Main row decoder A11, A1n, A21, A2n Sub memory block B11, B1n, B21, B2n Sub memory block selection signal BA1, BA2 ... Memory block S11, S18 ... Sense Amplifier D11, D18, D21, D28: Read bus C11, C18, C21, C28: Output circuit MC: Memory cell BL, XBL: Bit line pair DB1, XDB1, DB8, XDB8 ... Data bus pair CG: Column gate CT1, CT2: Column selection signal SRD: Sub-row decoder E1, E2: Output control signal J1, J2: Selection signal T11, T18, T21, T28,.・ Selection switch H11, H18 ・ ・ ・ Wiring F1, F8, F9, F16 ・ ・ ・ Data output line M ... memory macro cell L1, L3 ... X dimension of the X direction dimension L2 ... main row decoder of the memory block

Claims (2)

[Claims] A memory cell array in which memory cells are arranged in a matrix; a column gate connected to a bit line end of the memory cell array; a sub-word line decoder whose output is connected to a word line; A sub-memory block is constituted by a precharge circuit and a sense amplifier connected to the column gate, and two memory blocks formed by arranging n sub-memory blocks are arranged symmetrically about a main row decoder block. In a semiconductor memory device in which the same number of sense amplifiers in the sub-memory block as the output data width m of the memory are arranged, one of the 2n sub-blocks is selected by a sub-memory block selection signal during operation. Is configured to be stored in the one memory block. The outputs of the m × n sense amplifiers are connected in common by n each through m read buses and connected to the inputs of m output circuits, so that the m read buses and the m The output circuits are independently configured in units of the two memory blocks, and outputs of the m output circuits independently configured in units of the two memory blocks are commonly connected by m data output lines. A semiconductor memory device characterized by being performed. Means for disconnecting said m data output lines and means for switching said sub-block selection signal so as to simultaneously select one sub-memory block of each of said two memory blocks. Composed of metal wiring layers,
2. The semiconductor memory device according to claim 1, wherein memories having two types of output bit widths of an m-bit output and a 2m-bit output can be configured using the same bulk.