JPH11305418A - Reticle mask, semiconductor manufacturing apparatus, and semiconductor device manufacturing method - Google Patents

Abstract

(57) [Problem] To provide a reticle mask, a semiconductor manufacturing apparatus, and a semiconductor device manufacturing method that can narrow down to a specific internal circuit in a short time even when there are a plurality of internal circuit candidates. I do. SOLUTION: A reticle mask 1 according to the first embodiment of the present invention includes chip patterns 2 and 4 corresponding to chips having the same specifications and the same size. The chip pattern 2 includes an internal circuit pattern 6, and the chip pattern 4 includes an internal circuit pattern 8. Internal circuit pattern 6
And 8 correspond to circuits having different circuit configurations realizing the same function. As a result, through the same process, chips each including an internal circuit that is a candidate are manufactured.
By evaluating the performance of each chip under the same conditions,
The internal circuit pattern 6 or 8 is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a reticle mask,
The present invention relates to a semiconductor manufacturing apparatus and a method of manufacturing a semiconductor device, and more particularly, to a reticle mask, a semiconductor manufacturing apparatus, and a method of manufacturing a semiconductor device capable of narrowing down internal circuits to be mounted in a short period of time and performing chip development.

[0002]

2. Description of the Related Art In developing a semiconductor device (hereinafter referred to as a chip), it is desirable to narrow down internal circuits to be mounted by simulation in advance.

However, the time required for chip development has tended to be shortened, and one of a plurality of internal circuit candidates has been selected at the simulation stage due to the low voltage of the chip itself, high integration and miniaturization. It is difficult to determine the internal circuit.

For this reason, conventionally, when a plurality of circuits having different logical configurations are proposed as internal circuits for realizing a specific function, a method of configuring a chip so as to include all of the plurality of circuits has been proposed. Has been taken. Hereinafter, a conventional chip manufacturing will be described with reference to FIG.

FIG. 9 is a plan view conceptually showing an example of a chip pattern 102 used for manufacturing a conventional chip. As an example, a chip pattern including two internal circuit patterns corresponding to two internal circuit candidates is shown. 102 is shown.

As shown in FIG. 9, conventionally, reticle mask 100 includes internal circuit patterns 104 and 106 corresponding to candidate internal circuits, coupling wiring pattern 108,
In addition, a chip pattern 102 having a metal wiring pattern 110 is formed.

The connection wiring pattern 108 is a wiring for electrically connecting the internal circuit pattern 104 or 106 to another internal circuit pattern (not shown).

[0008] The metal wiring pattern 110 is in a connected state with the connection wiring pattern 108. Metal wiring pattern 1
Reference numeral 10 denotes the coupling wiring pattern 108 and the internal circuit pattern 1
It functions as a switch for coupling to the switch 04 or 106. In FIG. 9, the internal circuit pattern 10
4 is connected to the connection wiring pattern 108 via the metal wiring pattern 110.

At the same time, the reticle mask with the switch portion switched, that is, the internal circuit pattern 10
A reticle mask in which the metal wiring pattern 110 and the metal wiring pattern 110 are connected (the internal circuit pattern 104 and the metal wiring pattern 110 are not connected) is also prepared.

Specifically, a conventional procedure for narrowing down a plurality of internal circuit candidates to a specific internal circuit will be described with reference to a flow chart of FIG.

FIG. 10 is a flowchart for explaining the procedure of a conventional chip manufacturing method. Hereinafter, for explanation, a conventional chip including all of a plurality of candidate internal circuits is referred to as a chip 50, an internal circuit corresponding to the internal circuit pattern 104 is referred to as an internal circuit C1, and an internal circuit pattern 1 is referred to.
The internal circuit corresponding to 06 is referred to as an internal circuit C2.

Referring to FIG. 10, a reticle mask corresponding to chip 50 (reticle mask 100 including internal circuit patterns 104 and 106, switch portion shown in FIG. 9, and a switch portion, and a reticle mask in which the switch portion is switched) is manufactured. (Step S10).

Subsequently, a reticle mask 100 shown in FIG.
To perform wafer processing (eg, diffusion / ion implantation, photolithography / etching, CVD / metallization, etc.) (step S11). At this point, the internal circuit C1 (the internal circuit pattern 104) is in an electrically coupled state with other internal circuits.

Subsequently, an assembling / sealing process is performed (step S12). Inspection and evaluation of the manufactured chip 50 are performed (step S13). Specifically, the performance of the chip 50 is evaluated using the internal circuit C1.

Next, switching of the switch portion is performed (step S14). Specifically, a new chip 50 is manufactured using a reticle mask in which a switch portion is switched.
At this point, the internal circuit C2 (the internal circuit pattern 106)
Are electrically connected to other internal circuits.

Subsequently, inspection and evaluation of the manufactured chip 50 are performed (step S15). Specifically, the performance of the chip 50 is evaluated using the internal circuit C2.

Next, using the evaluation results in steps S13 and S15, a candidate internal circuit C1 or C1
It is determined which of the two internal circuits is to be adopted (step S16).

According to such a procedure, one of a plurality of internal circuit candidates is narrowed down (selected). Then, chips are mass-produced using a reticle mask in which a switch portion is connected to the selected internal circuit pattern (step S17).

[0019]

However, when the conventional manufacturing method is used, all of the candidate internal circuits are reduced to one.
Since it is provided in one chip, there is a problem that the area of the chip increases due to the presence of a circuit that does not operate on the actual chip (a circuit not selected).

Further, a reticle mask for connecting the metal wiring of the switch portion is required.

Further, a step for switching the switch portion is necessarily required. For this reason, there has been a problem that manufacturing efficiency is reduced and a development period is extended.

As described above, the evaluation conditions are different between when the chip 50 is evaluated using the internal circuit C1 and when the chip 50 is evaluated using the internal circuit C2. For this reason, there has been a problem that precise determination cannot be performed.

Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to efficiently narrow down to one internal circuit in a short period of time when there are a plurality of internal circuit candidates. To provide a reticle mask, a semiconductor manufacturing apparatus, and a semiconductor device manufacturing method.

Still another object of the present invention is to provide a reticle mask, a semiconductor manufacturing apparatus, and a semiconductor device capable of manufacturing a chip without increasing the chip area even when there are a plurality of internal circuit candidates. An object of the present invention is to provide a method for manufacturing a device.

[0025]

According to a first aspect of the present invention, there is provided a reticle mask including a plurality of chip patterns corresponding to a plurality of chips satisfying the same specifications, and each of the plurality of chips has a mutually configured configuration realizing the same function. Including different internal circuits.

A reticle mask according to a second aspect is the reticle mask according to the first aspect, wherein the plurality of chips have substantially the same size.

A reticle mask according to a third aspect is the reticle mask according to the first aspect, wherein the internal circuit is a circuit whose electrical characteristics have not been confirmed.

According to a fourth aspect of the present invention, there is provided a semiconductor manufacturing apparatus, comprising: a pattern forming means for forming a plurality of chip patterns corresponding to a plurality of chips satisfying the same specifications on one reticle mask; Manufacturing means for manufacturing a chip corresponding to each of the plurality of chip patterns from one wafer using the chip pattern, wherein each of the plurality of chips includes an internal circuit having a different configuration realizing the same function. .

A semiconductor manufacturing apparatus according to a fifth aspect is the semiconductor manufacturing apparatus according to the fourth aspect, further comprising an evaluation means for evaluating the performance of a chip corresponding to each of the plurality of chip patterns manufactured by the manufacturing means. Prepare.

A semiconductor manufacturing apparatus according to a sixth aspect is the semiconductor manufacturing apparatus according to the fourth aspect, wherein the plurality of chips have substantially the same size.

A semiconductor manufacturing apparatus according to a seventh aspect is the semiconductor manufacturing apparatus according to the fourth aspect, wherein the internal circuit is a circuit whose electrical characteristics have not been confirmed.

An eighth aspect of the present invention is the semiconductor manufacturing apparatus according to the fifth aspect, wherein the plurality of chips have substantially the same size.

A ninth aspect of the present invention is the semiconductor manufacturing apparatus according to the fifth aspect, wherein the internal circuit is a circuit whose electrical characteristics have not been confirmed.

According to a tenth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a pattern forming step of forming a plurality of chip patterns corresponding to a plurality of chips satisfying the same specifications on one reticle mask; and a pattern forming step. Using a plurality of chip patterns to manufacture chips corresponding to each of the plurality of chip patterns from one wafer, wherein the chips corresponding to each of the chip patterns are mutually configured to realize the same function. Including different internal circuits.

The method of manufacturing a semiconductor device according to claim 11 is the method of manufacturing a semiconductor device according to claim 10,
The method further includes an evaluation step of evaluating the performance of a chip corresponding to each of the plurality of chip patterns manufactured by the manufacturing step.

A method for manufacturing a semiconductor device according to claim 12 is the method for manufacturing a semiconductor device according to claim 10,
The size of each of the chips is substantially the same.

The method of manufacturing a semiconductor device according to claim 13 is the method of manufacturing a semiconductor device according to claim 10,
The internal circuit is a circuit whose electrical characteristics have not been confirmed.

A method of manufacturing a semiconductor device according to claim 14 is the method of manufacturing a semiconductor device according to claim 11,
The size of each of the chips is substantially the same.

A method of manufacturing a semiconductor device according to claim 15 is the method of manufacturing a semiconductor device according to claim 11,
The internal circuit is a circuit whose electrical characteristics have not been confirmed.

[0040]

[First Embodiment] A reticle mask, a method of manufacturing a semiconductor device using the reticle mask, and a semiconductor manufacturing apparatus according to a first embodiment of the present invention will be described.

FIG. 1 is a plan view showing chip patterns 2 and 4 in reticle mask 1 according to the first embodiment of the present invention.

In the first embodiment of the present invention, chip patterns each including a candidate internal circuit pattern are prepared on reticle mask 1. Specifically, as shown in FIG. 1, chip patterns 2 and 4 are formed. Both chip patterns 2 and 4 correspond to chips satisfying the same size and the same specifications.

The chip pattern 2 includes the internal circuit pattern 6
And the chip pattern 4 includes an internal circuit pattern 8. The internal circuit patterns 6 and 8 are circuit patterns for realizing the same function. The corresponding internal circuits have different configurations, and their electrical characteristics are both unconfirmed.

Next, a process of manufacturing a chip using the reticle mask 1 shown in FIG. 1 will be described with reference to a flow chart of FIG.

FIG. 2 is a flowchart showing a procedure of a method of manufacturing a chip according to the first embodiment of the present invention. Hereinafter, for explanation, a chip corresponding to the chip pattern 2 is referred to as a chip 10, a chip corresponding to the chip pattern 4 is referred to as a chip 20, an internal circuit corresponding to the internal circuit pattern 6 is referred to as an internal circuit C1, and an internal circuit pattern 8. The corresponding internal circuits are referred to as internal circuits C2, respectively.

As shown in FIG. 2, first, a reticle mask 1 including the chip patterns 2 and 4 shown in FIG. 1 is manufactured (step S1). Subsequently, a wafer process is performed using the reticle mask 1 (step S2).

FIG. 3 is a conceptual diagram for explaining the result when wafer processing is performed using reticle mask 1 shown in FIG. In this case, as shown in FIG. 3, a plurality of chips 10 corresponding to the chip pattern 2 and a plurality of chips 20 corresponding to the chip pattern 4 are simultaneously formed on the wafer 90 by the reticle mask 1.

Referring to FIG. 2, after wafer processing (step S2), assembly / sealing processing is performed (step S2).
3). At this point, a plurality of chips 10 and 20 in a molded state are completed.

Next, the inspection and evaluation of the chips 10 and 20 are performed simultaneously (step S4). Specifically, the performance evaluation of the chip 10 including the internal circuit C1 (step S4.1) and the performance evaluation of the chip 20 including the internal circuit C2 (step S4.2) are performed.

Subsequently, steps S4.1 and S4.2
Is used to determine which of the internal circuits C1 and C2 is to be adopted (step S5).

According to such a procedure, one of a plurality of internal circuit candidates (internal circuit patterns 6 or 8) is selected. Then, chips are mass-produced using the chip pattern corresponding to the selected internal circuit pattern (step S6).

Next, as a specific example, a case where two types of preamplifiers are listed as candidates will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 4 is a diagram showing an example of the configuration of a chip 50 manufactured by a conventional manufacturing method, and FIG.
FIG. 5 is a diagram showing an example of a configuration of a chip 10 manufactured by the manufacturing method according to the first embodiment of the present invention.
(B) is a diagram showing an example of a configuration of a chip 20 manufactured by the manufacturing method according to Embodiment 1 of the present invention.

The conventional chip 50 shown in FIG. 4 has memory cell arrays 40.1, 40.2, 40.3, and 40.
4, and preamplifier bands 42.1, 42.2, 42.
3 and 42.4.

Memory cell arrays 40.1, 40.2, 4
Each of 0.3 and 40.4 (hereinafter collectively referred to as memory cell array 40) includes a plurality of memory cells arranged in a matrix (not shown). Preamplifier band 42.
1, 42.2, 42.3, and 42.4 (hereinafter, collectively referred to as preamplifier band 42) include a plurality of preamplifiers 5.
2 inclusive. Each of preamplifier bands 42 is provided corresponding to memory cell array 40. The preamplifier 52
The data of the selected memory cell in the corresponding memory cell array 40 is amplified.

Chip 10 shown in FIG. 5A includes memory cell arrays 40.1, 40.2, 40.3 and 40.
4, and preamplifier bands 44.1, 44.2, 44.
3, and 44.4. Preamplifier band 44.1, 4
4.2, 44.3, and 44.4 (hereinafter, collectively referred to as preamplifier band 44) include a plurality of preamplifiers 54. Each of preamplifier bands 44 is provided corresponding to memory cell array 40. The preamplifier 54 amplifies data of a selected memory cell in the corresponding memory cell array 40.

Chip 20 shown in FIG. 5B includes memory cell arrays 40.1, 40.2, 40.3, and 40.
4, and preamplifier bands 46.1, 46.2, 46.
3, and 46.4. Preamplifier band 46.1, 4
6.2, 46.3, and 46.4 (hereinafter, collectively referred to as preamplifier band 46) include a plurality of preamplifiers 56. Each of preamplifier bands 46 is provided corresponding to memory cell array 40. The preamplifier 56 amplifies data of a selected memory cell in the corresponding memory cell array 40.

As described above, the chip 10 shown in FIG. 5A and the chip 20 shown in FIG. 5B are manufactured in the same process.

The preamplifier 52 shown in FIG. 4 has the internal circuit patterns 104 and 106 shown in FIG. 9 and the preamplifier 54 shown in FIG.
The preamplifier 56 shown in FIG. 5B corresponds to the internal circuit pattern 8 shown in FIG.

The preamplifier 52 shown in FIG.
The preamplifier 54 shown in FIG. 5 and the preamplifier 5 shown in FIG.
6 and a switch portion for switching between the preamplifier 54 and the preamplifier 56.

More specifically, the configuration of the preamplifiers 52, 54, and 56 will be described with reference to FIGS.

FIG. 6 shows a conventional preamplifier 52 shown in FIG.
FIG. 3 is a circuit diagram showing an example of a specific configuration of FIG. FIG.
5 is a circuit diagram showing an example of a specific configuration of the preamplifier 54 shown in FIG. 5A, and FIG. 8 is a circuit diagram showing an example of a specific configuration of the preamplifier 56 shown in FIG.

The preamplifier 52 shown in FIG. 6 includes P-channel MOS transistors P1, P2,..., P19, N-channel MOS transistors N1, N2,.
1, SW2,..., SW14. Switches SW1, S
W2,..., SW14 are terminals A and B, respectively.
And one of them is connected to the circuit element. In FIG. 6, the terminal B is in a connected state.

The preamplifier 52 is enabled when the preamplifier enable signal PAE changes from the L level to the H level. The preamplifier 52 receives input data DIN from an external circuit (sense amplifier) (not shown) and inverted input data DIN. Amplify ZDIN and output data R
D and its inverted output data ZRD.

In the switches SW1, SW2,..., SW14, when the terminal A is in the connected state, it operates as a new Arita type preamplifier. Switches SW1, SW2,...
When the terminal B is in the connected state in SW14, it operates as a cross-coupling type preamplifier.

The preamplifier 54 shown in FIG. 7 includes P-channel MOS transistors P1, P2,..., P19, N-channel MOS transistors N1, N2,..., N12, and inverter circuits I1 and I2. The preamplifier 54 is a new Arita type preamplifier, and corresponds to a circuit in which the terminal A is selected (connected) in the preamplifier 52 shown in FIG.

The preamplifier 56 shown in FIG. 8 includes P-channel MOS transistors P1, P2, P4, P6, P7,
, P19, N-channel MOS transistors N3,..., N7, N9, N11, N12, and inverter circuits I1 and I2. Preamplifier 56
Is a cross-coupling type preamplifier. In the preamplifier 52 shown in FIG. 6, the terminal B is selected (connected state).
Corresponding circuit.

In the preamplifier 54 shown in FIG. 7 and the preamplifier 56 shown in FIG. 8, the preamplifier enable signal PAE is changed from L level to H level similarly to the preamplifier 52 shown in FIG.
When the level changes to the enable state, input data DIN received from an external circuit (sense amplifier) not shown and inverted input data ZDIN obtained by inverting the input data DIN are obtained.
And outputs output data RD and inverted output data ZRD obtained by inverting the output data RD.

As described above, the preamplifier 54 shown in FIG. 7 and the preamplifier 56 shown in FIG. 8 are both one type of preamplifier. Therefore, since unnecessary transistor portions and switch portions are not provided, the layout area is smaller than that of the preamplifier 52 shown in FIG.

Further, the number of preamplifiers in one chip increases according to the number of memory cells. Therefore, chips 10 and 20 including preamplifiers 54 and 56 each having a small circuit area can have a smaller chip size than chip 50 including preamplifier 52 having a large circuit area. Specifically, the chip 1 shown in FIG.
5 or the chip 20 shown in FIG. 5B can reduce the chip area by about 1% compared to the chip 50 shown in FIG.

As described above, in the first embodiment of the present invention, chips having the same specifications and the same size, each including a candidate internal circuit, can be manufactured in the same process. As a result, the performance of each chip can be evaluated under the same conditions, so that the internal circuits mounted on the chips to be mass-produced can be accurately narrowed (selected).

Since it is not necessary to include a plurality of candidate internal circuits and switches in one chip, an increase in chip area can be suppressed.

Further, compared with the conventional semiconductor device manufacturing procedure (FIG. 9), according to the procedure of the manufacturing method in the first embodiment of the present invention, the step of switching the switch portion is not required, so that the development period is reduced. Can be shortened. Also,
It is not necessary to manufacture an extra mask corresponding to the switch portion. As a result, a specific internal circuit can be narrowed down in a short period of time.

It should be understood that the embodiments disclosed herein are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0075]

As described above, according to the reticle mask according to the first aspect, chips of the same specifications including the candidate internal circuits can be manufactured in the same process. This eliminates the need for a reticle mask for switching the internal circuit as compared with the related art. In addition, it becomes possible to manufacture chips corresponding to the respective internal circuits in the same process. Therefore, the performance of each chip can be evaluated under the same conditions. As a result, it is possible to accurately narrow down (select) an internal circuit mounted on a chip to be mass-produced.

The reticle mask according to the second aspect is the reticle mask according to the first aspect, wherein all chips to be manufactured have the same chip size. Thus, even if a chip corresponding to any of the internal circuits is selected, the relationship with the peripheral circuit including the chip is
It is always kept constant. Therefore, the development period of the entire device including the chip can be shortened.

The reticle mask according to the third aspect is the reticle mask according to the first aspect, and in particular, chips including respective electrically unconfirmed internal circuits can be manufactured in the same process. Therefore, even when a specific internal circuit cannot be narrowed down by a simulation, it is possible to accurately narrow down the internal circuit using an actual chip.

According to the semiconductor manufacturing apparatus of the fourth aspect,
Using one reticle mask, chips having the same specifications and including the candidate internal circuits can be manufactured in the same process. This eliminates the need for a reticle mask for switching the internal circuit as compared with the related art. Further, the process of switching the internal circuit (switch switching process) becomes unnecessary.
Further, the area of the chip itself can be reduced.

A semiconductor manufacturing apparatus according to a fifth aspect is the semiconductor manufacturing apparatus according to the fourth aspect, and further evaluates chips to be manufactured at the same time. This makes it possible to evaluate the performance of each chip under the same conditions. As a result, it is possible to narrow down the internal circuits in a short period of time and accurately determine (select) chips to be mass-produced.

A semiconductor manufacturing apparatus according to a sixth aspect is the semiconductor manufacturing apparatus according to the fourth aspect, wherein all chips to be manufactured have the same chip size. Thus, even if a chip corresponding to any of the internal circuits is selected, the relationship with the peripheral circuit including the chip is
It is always kept constant. Therefore, the development period of the entire device including the chip can be shortened.

The semiconductor manufacturing apparatus according to the seventh aspect is the semiconductor manufacturing apparatus according to the fourth aspect, and in particular, can manufacture chips each including an electrically unconfirmed circuit in the same process. Therefore, even if the internal circuits cannot be narrowed down by the simulation, it is possible to accurately narrow down the internal circuits using the actual chip.

The semiconductor manufacturing apparatus according to claim 8 is the semiconductor manufacturing apparatus according to claim 5, wherein all the chips to be manufactured have the same chip size. Thus, even if a chip corresponding to any of the internal circuits is selected, the relationship with the peripheral circuit including the chip is
It is always kept constant. Therefore, the development period of the entire device including the chip can be shortened.

According to a ninth aspect of the present invention, there is provided the semiconductor manufacturing apparatus according to the fifth aspect, in which chips including respective electrically unconfirmed circuits can be manufactured in the same process. Therefore, even if the internal circuits cannot be narrowed down by the simulation, it is possible to accurately narrow down the internal circuits using the actual chip.

According to the method of manufacturing a semiconductor device according to the tenth aspect, it is possible to manufacture chips of the same specifications each including a candidate internal circuit in the same step using one reticle mask. This eliminates the need for a reticle mask for switching the internal circuit as compared with the related art. Also,
The process of switching the internal circuit (switch switching process) becomes unnecessary. Further, the area of the chip itself can be reduced.

The method of manufacturing a semiconductor device according to claim 11 is the method of manufacturing a semiconductor device according to claim 10,
Further, the evaluation of the manufactured chip is performed at the same time. This makes it possible to evaluate the performance of each chip under the same conditions. As a result, the internal circuits are narrowed down in a short period of time, and the chips to be mass-produced are accurately determined (selected).
It is possible to do this.

The method of manufacturing a semiconductor device according to claim 12 is the method of manufacturing a semiconductor device according to claim 10,
Further, all manufactured chips have the same chip size. Thus, even when a chip corresponding to any of the internal circuits is selected, the relationship with the peripheral circuit including the chip is always kept constant. Therefore,
The development period of the entire device including the chip can be shortened.

The method of manufacturing a semiconductor device according to claim 13 is the method of manufacturing a semiconductor device according to claim 10,
In particular, chips each including an electrically unconfirmed circuit can be manufactured in the same process. Therefore, even if the internal circuits cannot be narrowed down by the simulation, it is possible to accurately narrow down the internal circuits using the actual chip.

The method of manufacturing a semiconductor device according to claim 14 is the method of manufacturing a semiconductor device according to claim 11,
Further, all manufactured chips have the same chip size. Thus, even when a chip corresponding to any of the internal circuits is selected, the relationship with the peripheral circuit including the chip is always kept constant. Therefore,
The development period of the entire device including the chip can be shortened.

The method of manufacturing a semiconductor device according to claim 15 is the method of manufacturing a semiconductor device according to claim 11,
In particular, chips each including an electrically unconfirmed circuit can be manufactured in the same process. Therefore, even if the internal circuits cannot be narrowed down by the simulation, it is possible to accurately narrow down the internal circuits using the actual chip.

[Brief description of the drawings]

FIG. 1 is a plan view showing chip patterns 2 and 4 in reticle mask 1 according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing a procedure of a method for manufacturing a chip according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram for explaining a result when wafer processing is performed using the reticle mask 1 shown in FIG.

FIG. 4 shows a chip 50 manufactured by a conventional manufacturing method.
FIG. 3 is a diagram showing an example of the configuration of FIG.

FIG. 5 is a diagram showing an example of a configuration of chips 10 and 20 manufactured by the manufacturing method according to the first embodiment of the present invention.

6 is a circuit diagram showing an example of a specific configuration of the conventional preamplifier 52 shown in FIG.

FIG. 7 is a circuit diagram showing an example of a specific configuration of a preamplifier shown in FIG.

FIG. 8 is a circuit diagram showing an example of a specific configuration of a preamplifier 56 shown in FIG.

FIG. 9 is a plan view conceptually showing an example of a chip pattern 102 used for manufacturing a conventional chip.

FIG. 10 is a flowchart illustrating a procedure of a conventional chip manufacturing method.

[Explanation of symbols]

1,100 reticle mask, 2, 4, 102 chip pattern, 6, 8, 104, 106 internal circuit pattern, 10, 20, 50 chip, 52, 54, 56 preamplifier, 40.1, 40.2, 40.3 , 40.4
Memory cell array, 42.1, 42.2, 42.3, 4
2.4,44.1,44.2,44.3,44.4,4
6.1, 46.2, 46.3, 46.4 Preamplifier band, P1 to P19 P-channel MOS transistors,
N1 to N12 N-channel MOS transistors, I
1, I2 inverter circuit, SW1 to SW14 switches.

Claims (15)

[Claims] 1. A reticle mask comprising: a plurality of chip patterns corresponding to a plurality of chips satisfying the same specification; each of the plurality of chips includes internal circuits having different configurations realizing the same function. 2. The reticle mask according to claim 1, wherein said plurality of chips have substantially the same size. 3. The reticle mask according to claim 1, wherein the internal circuit is a circuit whose electrical characteristics have not been confirmed. 4. A pattern forming means for forming a plurality of chip patterns corresponding to a plurality of chips satisfying the same specifications on one reticle mask, and using the plurality of chip patterns formed by the pattern forming means. Manufacturing means for manufacturing the chips corresponding to each of the plurality of chip patterns from one wafer, wherein each of the plurality of chips includes an internal circuit having a different configuration realizing the same function. apparatus. 5. The semiconductor manufacturing apparatus according to claim 4, further comprising evaluation means for evaluating the performance of said chip corresponding to each of said plurality of chip patterns manufactured by said manufacturing means. 6. The semiconductor manufacturing apparatus according to claim 4, wherein said plurality of chips have substantially the same size. 7. The semiconductor manufacturing apparatus according to claim 4, wherein said internal circuit is a circuit whose electrical characteristics have not been confirmed. 8. The semiconductor manufacturing apparatus according to claim 5, wherein said plurality of chips have substantially the same size. 9. The semiconductor manufacturing apparatus according to claim 5, wherein said internal circuit is a circuit whose electrical characteristics have not been confirmed. 10. A pattern forming step of forming a plurality of chip patterns corresponding to a plurality of chips satisfying the same specification on one reticle mask, and using the plurality of chip patterns formed by the pattern forming step, Manufacturing steps for manufacturing the chips corresponding to each of the plurality of chip patterns from one wafer, wherein the chips corresponding to each of the chip patterns have internal circuits having different configurations realizing the same function. And a method of manufacturing a semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising an evaluation step of evaluating the performance of said chip corresponding to each of said plurality of chip patterns manufactured by said manufacturing step. 12. The method according to claim 10, wherein the sizes of the chips are substantially the same. 13. The method of manufacturing a semiconductor device according to claim 10, wherein said internal circuit is a circuit whose electrical characteristics have not been confirmed. 14. The method according to claim 11, wherein the sizes of the chips are substantially the same. 15. The method of manufacturing a semiconductor device according to claim 11, wherein said internal circuit is a circuit whose electrical characteristics have not been confirmed.