JPH11307696A - Power semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Problem] There is a problem that the withstand voltage is low. SOLUTION: A semiconductor chip 2, a metal base plate 3 for radiating heat generated in the semiconductor chip, a ceramic plate 4 for insulating the semiconductor chip 2 from the metal base plate 3, and an upper surface of the ceramic plate 4 A first metal electrode 5a provided, a second metal electrode 5b provided on the lower surface of the ceramic plate 4, a metal spacer 7 for widening a gap between the metal base plate 3 and the ceramic plate 4, and a semiconductor chip 2,
Metal base plate 3, ceramic plate 4, first metal electrode 5
a, a silicon gel 11 for sealing the second metal electrode 5 b and the metal spacer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a structure of a main part of a conventional power semiconductor device. In FIG. 5, 101 is a power semiconductor device, 102 is a semiconductor chip made of IGBT or the like, 103 is a metal base plate of about 4 mm thick made of copper or the like for radiating heat generated in the semiconductor chip 102, 104 is a semiconductor chip 102 is a metal base plate 103
A ceramic plate made of aluminum nitride or the like having a thickness of about 0.6 mm for insulation from the ceramic plate;
m of the first metal electrode, 105b is the ceramic plate 10
4, a second metal electrode 106a made of copper or the like and having a thickness of about 0.2 mm, and a first metal electrode 106a having a thickness of about several hundred μm for bonding the ceramic plate 104 and the first metal electrode 105a. A brazing paste 106b is a second brazing paste having a thickness of about several hundred μm for bonding the ceramic plate 104 and the second metal electrode 105b, and 107a is a semiconductor chip 102.
Thickness of 0.2 mm for bonding the first metal electrode 105a with the first metal electrode 105a
The first solder 107b is a second solder having a thickness of about 0.2 mm for bonding the metal base plate 103 and the second metal electrode 105b, and the first solder 108a is made of aluminum to be connected to the semiconductor chip 102. A metal wire 108b is a second metal wire made of aluminum connected to the first metal electrode 105a; 109 covers the semiconductor chip 102, the ceramic plate 104, the first metal electrode 105a and the second metal electrode 105b, Silicon gel to be sealed.

In a conventional power semiconductor device 101, a semiconductor chip 102, a ceramic plate 104, a first metal electrode 105a and a second metal electrode 105b are
09 and sealing, a dielectric breakdown voltage (hereinafter referred to as dielectric withstand voltage) is secured.

In the conventional power semiconductor device 101, the ceramic plate 104 is connected to the first and second metal electrodes 105.
a, 105b to increase the withstand voltage.

Next, a method for manufacturing a conventional power semiconductor device will be described. When manufacturing the conventional power semiconductor device 101, first, the first and second brazing pastes 106a,
The solder paste to be 106b is printed on both surfaces of the ceramic plate 104 with a thickness of about several hundred μm. And the first,
The two metal electrodes serving as the second metal electrodes 105a and 105b are placed on the brazing paste printed on both sides of the ceramic plate 104 and heat-treated at about 850 ° C. to bond the metal electrodes to both surfaces of the ceramic plate 104. I do.

Thereafter, the ceramic plate 104 having the metal electrodes adhered to both sides thereof is adhered to the metal base plate 103 by high-temperature solder (melting point: about 260 ° C.) serving as the second solder 107b. The low-temperature solder (melting point: about 150 ° C.) serving as the first solder 107 a is bonded to the ceramic plate 104 having metal electrodes bonded to both surfaces.

Thereafter, the metal wire serving as the first metal wire 108a is connected to the semiconductor chip 102 by wire bonding, and the metal wire serving as the second metal wire 108b is connected to the metal electrode serving as the first metal electrode 105a. Connection is made by wire bonding.

Thereafter, the metal base plate 103 on which the semiconductor chip 102, the ceramic plate 104, the first metal electrode 105a, the second metal electrode 105b, etc. are mounted is housed in a package (not shown). And silicon gel 1
The semiconductor chip 102, the ceramic plate 104, the first metal electrode 105a, and the second metal electrode 1 are vacuum-injected into a package (not shown) and hardened by heating.
05b and the like are covered with the silicon gel 109 and sealed. Thus, the conventional power semiconductor device 101 is manufactured.

There are two possible modes of the dielectric breakdown of the power semiconductor device. The first mode is a mode in which the first metal electrode provided on the upper surface of the ceramic plate passes through the interface between the ceramic plate and the silicon gel and passes through the second metal electrode provided on the lower surface of the ceramic substrate. Mode 2 is a mode in which the first metal electrode passes through the inside of the silicon gel and exits to the metal base plate.

FIG. 6 is an explanatory diagram of a dielectric breakdown mode of the power semiconductor device. In FIG. 6, 111 is a power semiconductor device, 112 is a semiconductor chip, 113 is a metal base plate,
114 is a ceramic plate, 115a is a first metal electrode, 1
15b is a second metal electrode. In FIG. 6, the solder paste and the solder are omitted and not shown.

L1 is the first metal electrode 1 from the end of the ceramic plate 114 on the upper surface of the ceramic plate 114.
L2 is a distance from the end of the ceramic plate 114 on the lower surface of the ceramic plate 114 to the second metal electrode 1
15, d is the thickness of the ceramic plate 114, and t is the distance between the metal base plate 113 and the ceramic plate 114.

The path length X1 of the first mode is L1 + d +
L2, and as X1 becomes longer, the withstand voltage in the first mode becomes higher. The path length X2 of the second mode is L1 +
d + t, and the longer the X2, the higher the dielectric strength in the second mode. When the path length X1 of the first mode and the path length X2 of the second mode are the same, the withstand voltage of the first mode is smaller than the withstand voltage of the second mode.

[0013]

Since the conventional power semiconductor device is configured as described above, the path length X2 of the second mode is short, and the withstand voltage is small depending on the withstand voltage of the second mode. There was a problem of becoming something.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a power semiconductor device having a large withstand voltage since the second mode has a high withstand voltage.

[0015] As a related technology of the present invention, there is a technology disclosed in Japanese Patent Application Laid-Open No. 61-51947.
FIG. 7 is a sectional view of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 61-51947. 7, reference numeral 121 denotes a semiconductor device; 122, an insulator; 123a, a first metallized pattern provided on the upper surface of the insulator 122; 123b, a second metallized pattern provided on the lower surface of the insulator 122; Protrusions provided on the peripheral edges of both surfaces of the insulator 122, radiation fins 126, radiation fins 127
Is a convex portion provided on the surface.

The technique disclosed in Japanese Patent Application Laid-Open No. S61-51947 is to improve the withstand voltage in the above-described first mode by providing protrusions 124 on the peripheral edges of both surfaces of the insulator 122 to improve the withstand voltage. And is different from the present invention. Also, the projection 127 is formed on the radiation fin 126.
Is also provided in order to simplify the operation of assembling the semiconductor device, and this point is also different from the present invention.

[0017]

A power semiconductor device according to the present invention includes a spacer for increasing a distance between a base plate and an insulating plate.

In the power semiconductor device according to the present invention, the spacer is configured such that a distance between the base plate and the insulating plate is larger than a distance from an end of the insulating plate on a lower surface of the insulating plate to the second electrode. Is what it is.

In the power semiconductor device according to the present invention, the spacer is formed integrally with the second electrode.

[0020] In the power semiconductor device according to the present invention, the spacer is fitted into the opening formed in the base plate.

In the power semiconductor device according to the present invention, the spacer is integrally formed with the base plate.

In the method for manufacturing a power semiconductor device according to the present invention, the solder paste is printed on the upper surface of the base plate, the spacer is placed on the solder paste printed on the upper surface of the base plate, and heat treatment is performed. And a step of bonding an insulating plate having electrodes serving as first and second electrodes on both surfaces thereof to the spacer by soldering.

In the method for manufacturing a power semiconductor device according to the present invention, an electrode serving as a first electrode is bonded to one surface, and a spacer integrally formed with the second electrode is bonded to the other surface. The method includes a step of bonding the insulating plate to the base plate by soldering.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a sectional view showing a configuration of a main part of a power semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a power semiconductor device, 2 is a semiconductor chip made of IGBT or the like, 3 is a metal base plate (base plate) of about 4 mm thick made of copper or the like for radiating heat generated in the semiconductor chip 2, Reference numeral 4 denotes a ceramic plate (insulating plate) made of aluminum nitride or the like for insulating the semiconductor chip 2 from the metal base plate 3 and having a thickness d of about 0.6 mm.
Denotes a first metal electrode (first electrode) made of copper or the like provided on the upper surface of the ceramic plate 4 and having a thickness of about 0.4 mm;
Denotes a second metal electrode (second electrode) made of copper or the like provided on the lower surface of the ceramic plate 4 and having a thickness of about 0.2 mm;
Is a first brazing paste having a thickness of about several hundred μm for bonding the ceramic plate 4 and the first metal electrode 5a, and 6b is a thickness of several hundred μm for bonding the ceramic plate 4 and the second metal electrode 5b.
The second brazing paste 7 has a metal spacer (spacer) made of copper or the like for widening the space between the metal base plate 3 and the ceramic plate 4, and has a thickness 8 for bonding the metal base plate 3 and the metal spacer 7. A third solder paste having a thickness of about several hundred μm, 9a is a first solder having a thickness of about 0.2 mm for bonding the semiconductor chip 2 and the first metal electrode 5a, and 9b is a metal spacer 7 and a second metal. Thickness for bonding to electrode 5b 0.2
mm, a first metal wire made of aluminum connected to the semiconductor chip 2; 10b a second metal wire made of aluminum connected to the first metal electrode 5a; 11 a semiconductor chip 2 , A silicon gel (insulating sealing material) that covers and seals the ceramic plate 4, the first metal electrode 5a, the second metal electrode 5b, the metal spacer 7, and the like.

In the power semiconductor device 1 according to the first embodiment, the metal spacer 7 is provided between the metal base plate 3 and the ceramic plate 4. The thickness of the metal spacer 7 is set to about 3 mm. Therefore, the interval t between the metal base plate 3 and the ceramic plate 4 is about 3 mm or more.

In the power semiconductor device 1 according to the first embodiment, the distance L1 from the end of the ceramic plate 4 on the upper surface of the ceramic plate 4 to the first metal electrode 5a and the distance of the ceramic plate 4 from the lower surface of the ceramic plate 4 The distance L2 from the end to the second metal electrode 5b is about 2 mm.

Next, a method of manufacturing the power semiconductor device according to the first embodiment will be described. When manufacturing the power semiconductor device 1 according to the first embodiment, first, a brazing paste to be the first and second brazing pastes 6a and 6b is printed on both surfaces of the ceramic plate 4 with a thickness of about several hundred μm. Then, two metal electrodes serving as the first and second metal electrodes 5a and 5b are placed on the brazing paste printed on both surfaces of the ceramic plate 4 and heat-treated at about 850 ° C. A metal electrode is adhered to.

Thereafter, a brazing paste to be the third brazing paste 8 is printed on the upper surface of the metal base plate 3 to a thickness of about several hundred μm. Then, the metal spacer 7 is placed on the brazing paste printed on the upper surface of the metal base plate 3, and about 85 mm.
By performing a heat treatment at 0 ° C., the metal spacer 7 is bonded to the metal base plate 3.

Thereafter, the ceramic plate 4 having the metal electrodes adhered to both sides thereof is bonded to the second solder 9b by high-temperature solder.
The semiconductor chip 2 is adhered to the metal spacer 7, and the semiconductor chip 2 is adhered to the ceramic plate 4 to which metal electrodes are adhered on both surfaces by low-temperature solder serving as the first solder 9 a.

Thereafter, the metal wire serving as the first metal wire 10a is connected to the semiconductor chip 2 by wire bonding, and the metal wire serving as the second metal wire 10b is connected to the metal electrode serving as the first metal electrode 5a. Connection is made by wire bonding.

Thereafter, the metal base plate 3 on which the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a, the second metal electrode 5b, the metal spacer 7 and the like are mounted is housed in a package (not shown). . And the silicon gel 11
Is vacuum-injected into a package (not shown) and cured by heating, so that the semiconductor chip 2, the ceramic plate 4, the first
The metal electrode 5a, the second metal electrode 5b, the metal spacer 7 and the like are covered with the silicon gel 11 and sealed. Thus, the power semiconductor device 1 according to the first embodiment is manufactured.

As described above, according to the first embodiment, the metal spacer 7 made of copper or the like for increasing the distance between the metal base plate 3 and the ceramic plate 4 is provided.
The effect of increasing the path length X2 in the second mode and increasing the dielectric strength is obtained.

Further, according to the first embodiment, the thickness of the metal spacer 7 is set to about 3 mm, and the second metal electrode 5 is formed from the end of the ceramic plate 4 on the lower surface of the ceramic plate 4.
Since the distance L2 to b is about 2 mm, the path length X2 of the second mode is longer than the path length X1 of the first mode. As a result, the withstand voltage of the second mode is higher than the withstand voltage of the first mode. As a result, the effect is obtained that the breakdown voltage of the power semiconductor device 1 becomes a saturated value determined by the breakdown voltage of the first mode.

Further, according to the first embodiment, the metal spacer 7 is bonded to the metal base plate 3 with the brazing paste, and then the ceramic plate 4 having the metal electrodes bonded to both surfaces is bonded to the metal spacer 7 by high-temperature soldering. After bonding, the semiconductor chip 2 is bonded to the ceramic plate 4 to which metal electrodes are bonded on both sides by low-temperature soldering, so that the metal electrodes are bonded to both surfaces without detaching the metal spacer 7 and the metal base plate 3. The ceramic plate 4 can be bonded to the metal spacer 7, and the metal plate 7 and the metal base plate 3 and the ceramic plate 4 and the metal spacer
The effect that the semiconductor chip 2 can be adhered to the ceramic plate 4 to which the metal electrodes are adhered to both surfaces without detaching the semiconductor chip 2 is obtained.

Embodiment 2 FIG. 2 is a sectional view showing a configuration of a main part of a power semiconductor device according to a second embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a power semiconductor device;
Reference numeral 2 denotes a metal spacer (spacer) made of copper or the like for increasing a distance between the metal base plate 3 and the ceramic plate 4, and reference numeral 23 denotes a second adhesive having a thickness of about several hundred μm for bonding the ceramic plate 4 and the metal spacer 22. A brazing paste, 24 is a second solder having a thickness of about 0.2 mm for bonding the metal base plate 3 and the metal spacer 22, 25 is a semiconductor chip 2, a ceramic plate 4, a first metal electrode 5a, a metal spacer 22, and the like. Is a silicone gel (insulating sealing material) that covers and seals. Other components are the same as those shown in FIG.

Power semiconductor device 21 according to the second embodiment
Here, the metal spacer 22 is provided between the metal base plate 3 and the ceramic plate 4. Then, the metal spacer 22
Has a thickness of about 3 mm. Therefore, the interval t between the metal base plate 3 and the ceramic plate 4 is about 3 mm or more.

In the power semiconductor device 21 according to the second embodiment, the metal spacer 22 is formed integrally with the second metal electrode provided on the lower surface of the ceramic plate 4.

In the power semiconductor device 21 according to the second embodiment, the distance L1 from the end of the ceramic plate 4 on the upper surface of the ceramic plate 4 to the first metal electrode 5a and the distance of the ceramic plate 4 from the lower surface of the ceramic plate 4 are reduced. Metal spacer 2 integrally formed with the second metal electrode from the end
The distance L2 to 2 is about 2 mm.

Next, a method of manufacturing the power semiconductor device according to the second embodiment will be described. When manufacturing the power semiconductor device 21 according to the second embodiment, first, a brazing paste to be the first and second brazing pastes 6a and 23 is printed on both surfaces of the ceramic plate 4 to a thickness of about several hundred μm. Then, the metal electrode to be the first metal electrode 5a is placed on the brazing paste printed on one surface of the ceramic plate 4, and the metal spacer 22 is placed on the brazing paste printed on the other surface of the ceramic plate 4. By performing a heat treatment at about 850 ° C., a metal electrode is bonded to one surface of the ceramic plate 4 and a metal spacer 22 is bonded to the other surface.

Thereafter, a metal electrode is adhered to one surface,
The ceramic plate 4 with the metal spacer 22 adhered to the other surface is adhered to the metal base plate 3 by high-temperature solder to be the second solder 24, and the semiconductor chip 2 is bonded by low-temperature solder to be the first solder 9a. , A metal electrode is adhered to one side,
The other surface is bonded to the ceramic plate 4 to which the metal spacer 22 is bonded.

Thereafter, the metal wire serving as the first metal wire 10a is connected to the semiconductor chip 2 by wire bonding, and the metal wire serving as the second metal wire 10b is connected to the metal electrode serving as the first metal electrode 5a. Connection is made by wire bonding.

Thereafter, the metal base plate 3 on which the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a, and the metal spacer 22 integrally formed with the second metal electrode are mounted is packaged (not shown). ). And
The silicon gel 25 is vacuum-injected into a package (not shown) and heat-cured to form a metal integrally formed with the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a, and the second metal electrode. The spacer 22 and the like are covered with a silicon gel 25 and sealed. Thus, power semiconductor device 21 according to the second embodiment is manufactured.

As described above, according to the second embodiment, since the metal spacer 22 made of copper or the like for increasing the distance between the metal base plate 3 and the ceramic plate 4 is provided, the second mode The effect of increasing the path length X2 and increasing the withstand voltage is obtained.

According to the second embodiment, the thickness of the metal spacer 22 is set to about 3 mm, and the metal spacer 22 is formed integrally with the second metal electrode from the end of the ceramic plate 4 on the lower surface of the ceramic plate 4. Distance L2 to metal spacer 22
Is about 2 mm, so that the path length X in the second mode
2 is longer than the path length X1 of the first mode, so that the withstand voltage of the second mode is higher than the withstand voltage of the first mode, and the withstand voltage of the power semiconductor device 21 is equal to the withstand voltage of the first mode. The effect of obtaining a determined saturated value is obtained.

Further, according to the second embodiment, since the metal spacer 22 is formed integrally with the second metal electrode, the effect of simplifying the manufacturing process can be obtained.

Further, according to the second embodiment, the metal electrode is bonded to one surface and the metal spacer 22 is bonded to the other surface.
Is bonded to the metal base plate 3 by high-temperature solder, so that the distortion of the metal base plate 3 is reduced, and as a result, the effect of increasing the heat dissipation from the metal base plate 3 is obtained.

Embodiment 3 FIG. 3 is a sectional view showing a configuration of a main part of a power semiconductor device according to a third embodiment of the present invention. In FIG. 3, reference numeral 31 denotes a power semiconductor device;
2 is a metal base plate (base plate) of about 4 mm in thickness made of copper or the like for radiating heat generated in the semiconductor chip 2,
Reference numeral 33 denotes an opening formed in the metal base plate 32, reference numeral 34 denotes a metal spacer (spacer) made of copper or the like for increasing the distance between the metal base plate 32 and the ceramic plate 4, reference numeral 35 denotes the semiconductor chip 2, the ceramic plate 4, Silicon gel (insulating sealing material) that covers and seals the first metal electrode 5a, the second metal electrode 5b, the metal spacer 34, and the like. Other components are the same as those shown in FIG.

Power semiconductor device 31 according to the third embodiment
Here, the metal spacer 34 is fitted into the opening 33 formed in the metal base plate 32 and having a slightly smaller size than the metal spacer 34. Then, the metal spacer 32
The thickness of the metal base plate 32 is about 7 mm.
The length of the portion protruding outside from 3 is about 3 mm. Therefore, the interval t between the metal base plate 3 and the ceramic plate 4 is about 3 mm or more.

In the power semiconductor device 31 according to the third embodiment, the distance L1 from the end of the ceramic plate 4 on the upper surface of the ceramic plate 4 to the first metal electrode 5a and the distance of the ceramic plate 4 from the lower surface of the ceramic plate 4 The distance L2 from the end to the second metal electrode 5b is about 2 mm.

Next, a method of manufacturing the power semiconductor device according to the third embodiment will be described. When manufacturing the power semiconductor device 31 according to the third embodiment, first, an opening 33 having a size slightly smaller than the metal spacer 34 is formed in the metal base plate 32 by a boring process. Then, the metal spacer 34 is cooled and inserted into the opening 33 formed in the metal base plate 32. When returning to room temperature, due to thermal expansion,
The metal spacer 34 is fitted into an opening 33 formed in the metal base plate 32.

Then, the first and second brazing pastes 6a,
The solder paste to be 6b is printed on both surfaces of the ceramic plate 4 with a thickness of about several hundred μm. Then, the two metal electrodes to be the first and second metal electrodes 5a and 5b are placed on the brazing paste printed on both surfaces of the ceramic plate 4 for about 85%.
By performing heat treatment at 0 ° C., metal electrodes are bonded to both surfaces of the ceramic plate 4.

After that, the ceramic plate 4 having the metal electrodes adhered to both surfaces is separated by a high-temperature solder to be the second solder 9b.
The semiconductor chip 2 is adhered to the metal spacer 34, and the semiconductor chip 2 is adhered to the ceramic plate 4 to which metal electrodes are adhered on both surfaces by low-temperature solder that becomes the first solder 9a.

Thereafter, the metal wire serving as the first metal wire 10a is connected to the semiconductor chip 2 by wire bonding, and the metal wire serving as the second metal wire 10b is connected to the metal electrode serving as the first metal electrode 5a. Connection is made by wire bonding.

Thereafter, the metal base plate 32 on which the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a, the second metal electrode 5b, the metal spacer 34 and the like are mounted is housed in a package (not shown). . Then, the semiconductor chip 2, the ceramic plate 4, and the silicon gel 35 are vacuum-injected into a package (not shown) and cured by heating.
The first metal electrode 5a, the second metal electrode 5b, the metal spacer 34 and the like are covered with a silicon gel 35 and sealed. Thus, power semiconductor device 31 according to the third embodiment is manufactured.

As described above, according to the third embodiment, since the metal spacers 34 made of copper or the like for increasing the distance between the metal base plate 32 and the ceramic plate 4 are provided, the second mode of the second mode is provided. The effect of increasing the path length X2 and increasing the withstand voltage is obtained.

According to the third embodiment, by setting the thickness of the metal spacer 34 to about 7 mm, the height of the portion protruding outside from the opening 33 of the metal base plate 32 to about 3 mm, Distance L from the end of ceramic plate 4 on the lower surface of plate 4 to second metal electrode 5b
2 is about 2 mm, so that the path length X2 of the second mode is longer than the path length X1 of the first mode.
The second mode has an effect that the withstand voltage in the second mode is higher than the withstand voltage in the first mode, and the withstand voltage of the power semiconductor device 31 becomes a saturated value determined by the withstand voltage in the first mode.

According to the third embodiment, the metal spacer 34 is fitted into the opening 33 formed in the metal base plate 32 and having a slightly smaller size than the metal spacer 34. And metal base plate 3
2 has a high adhesiveness to the metal base plate 3, and thus has an effect of increasing heat radiation to the metal base plate 3.

Embodiment 4 FIG. 4 is a sectional view showing a configuration of a main part of a power semiconductor device according to a fourth embodiment of the present invention. 4, reference numeral 41 denotes a power semiconductor device;
2 is a metal base plate (base plate) of about 4 mm in thickness made of copper or the like for radiating heat generated in the semiconductor chip 2,
Reference numeral 43 denotes a metal spacer (spacer) made of copper or the like for increasing a distance between the metal base plate 42 and the ceramic plate 4;
Reference numeral 4 denotes a silicon gel (insulating sealing material) that covers and seals the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a, the second metal electrode 5b, the metal spacer 43, and the like. Other components are the same as those shown in FIG.

Power semiconductor device 41 according to the fourth embodiment
Here, the metal spacer 43 is formed integrally with the metal base plate 42. The height of the convex portion of the metal base plate 42 as the metal spacer 43 is about 3 mm. Therefore, the interval t between the metal base plate 42 and the ceramic plate 4 is about 3 mm or more.

Further, in the power semiconductor device 41 according to the fourth embodiment, the distance L1 from the end of the ceramic plate 4 on the upper surface of the ceramic plate 4 to the first metal electrode 5a and the distance of the ceramic plate 4 from the lower surface of the ceramic plate 4 The distance L2 from the end to the second metal electrode 5b is about 2 mm.

Next, a method of manufacturing the power semiconductor device according to the fourth embodiment will be described. When manufacturing the power semiconductor device 41 according to the fourth embodiment, first, a metal base plate 42 having a convex portion as a metal spacer 43 is formed by shaving.

Thereafter, the first and second brazing pastes 6a,
The solder paste to be 6b is printed on both surfaces of the ceramic plate 4 with a thickness of about several hundred μm. Then, the two metal electrodes to be the first and second metal electrodes 5a and 5b are placed on the brazing paste printed on both surfaces of the ceramic plate 4 for about 85%.
By performing heat treatment at 0 ° C., metal electrodes are bonded to both surfaces of the ceramic plate 4.

After that, the ceramic plate 4 having the metal electrodes bonded to both sides thereof is bonded to the second solder 9b by high-temperature solder.
The semiconductor chip 2 is adhered to the metal spacer 43, and the ceramic chip 4 is adhered to the ceramic plate 4 to which metal electrodes are adhered on both surfaces by low-temperature solder that becomes the first solder 9a.

Thereafter, the metal wire serving as the first metal wire 10a is connected to the semiconductor chip 2 by wire bonding, and the metal wire serving as the second metal wire 10b is connected to the metal electrode serving as the first metal electrode 5a. Connection is made by wire bonding.

Thereafter, the metal base plate 42 on which the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a and the second metal electrode 5b are mounted is housed in a package (not shown). Then, the silicon chip 44 is vacuum-injected into a package (not shown), and is cured by heating, so that the semiconductor chip 2, the ceramic plate 4, the first metal electrode 5a,
The second metal electrode 5b and the protrusions of the metal base plate 42 as the metal spacer 43 are covered with the silicon gel 44 and sealed. Thus, power semiconductor device 41 according to the fourth embodiment is manufactured.

As described above, according to the fourth embodiment, the metal spacer 43 made of copper or the like for increasing the distance between the metal base plate 42 and the ceramic plate 4 is provided. The effect of increasing the path length X2 and increasing the withstand voltage is obtained.

According to the fourth embodiment, the height of the convex portion of the metal base plate 42 as the metal spacer 43 is set to 3
mm, and the distance L2 from the end of the ceramic plate 4 on the lower surface of the ceramic plate 4 to the second metal electrode 5b is set to approximately 2 mm, so that the path length X2 of the second mode
Is longer than the path length X1 of the first mode, so that the second
This has the effect that the withstand voltage in the mode is higher than the withstand voltage in the first mode, and the withstand voltage of the power semiconductor device 41 becomes a saturated value determined by the withstand voltage in the first mode.

Further, according to the fourth embodiment, since the metal spacer 43 is formed integrally with the metal base plate 42, an effect of increasing heat radiation to the metal base plate 42 can be obtained.

[0069]

As described above, according to the present invention, since the spacer is provided to widen the distance between the base plate and the insulating plate, there is an effect that the withstand voltage is increased.

According to the present invention, the spacer is configured so that the distance between the base plate and the insulating plate is larger than the distance from the end of the insulating plate on the lower surface of the insulating plate to the second electrode. Has the effect of becoming a saturated value.

According to the present invention, since the spacer is formed integrally with the second electrode, there is an effect that the manufacturing process can be simplified.

According to the present invention, since the spacer is configured to be fitted into the opening formed in the base plate, there is an effect that heat radiation to the base plate is enhanced.

According to the present invention, since the spacer is formed integrally with the base plate, there is an effect that heat radiation to the base plate is enhanced.

According to the present invention, the step of printing the brazing paste on the upper surface of the base plate, placing the spacer on the brazing paste printed on the upper surface of the base plate, and performing heat treatment to bond the spacer to the base plate. And a step of bonding an insulating plate having electrodes serving as first and second electrodes on both sides to a spacer by soldering, so that metal electrodes are provided on both sides without detaching the spacer and the base plate. The bonded insulating plate can be bonded to the spacer, and the spacer and the base plate and the insulating plate with the metal electrodes bonded on both sides and the insulating plate with the metal electrodes bonded on both surfaces without removing the spacer. It has the effect of being able to adhere to the board.

According to the present invention, an insulating plate in which an electrode serving as a first electrode is adhered to one surface and a spacer integrally formed with the second electrode is adhered to the other surface is formed by soldering. Since the method includes the step of bonding to the base plate, there is an effect that a power semiconductor device having high heat dissipation to the base plate can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a main part of a power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration of a main part of a power semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view showing a configuration of a main part of a power semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a sectional view showing a configuration of a main part of a power semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a configuration of a main part of a conventional power semiconductor device.

FIG. 6 is an explanatory diagram of a dielectric breakdown mode of the power semiconductor device.

FIG. 7 is a sectional view of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 61-51947.

[Explanation of symbols]

1, 21, 31, 41 power semiconductor device, 2 semiconductor chips, 3, 32, 42 metal base plate (base plate),
4 Ceramic plate (insulating plate), 5a First metal electrode (first electrode), 5b Second metal electrode (second electrode), 7, 22, 34, 43 Metal spacer (spacer), 11, 25 , 35, 44 Silicon gel (insulating sealing material), 33 Opening.

Claims (7)

[Claims] 1. A semiconductor chip, a base plate for radiating heat generated in the semiconductor chip, an insulating plate for insulating the semiconductor chip from the base plate, and an upper surface of the insulating plate. A first electrode, a second electrode provided on a lower surface of the insulating plate, a spacer for increasing a distance between the base plate and the insulating plate, a semiconductor chip, the base plate, the insulating plate, A power semiconductor device comprising: the first electrode, the second electrode, and an insulating sealing material that seals a spacer. 2. The spacer according to claim 1, wherein a distance between the base plate and the insulating plate is larger than a distance from an end of the insulating plate to a second electrode on a lower surface of the insulating plate. The power semiconductor device according to claim 1, wherein 3. The power semiconductor device according to claim 1, wherein the spacer is formed integrally with the second electrode. 4. The power semiconductor device according to claim 1, wherein the spacer is fitted in an opening formed in the base plate. 5. The power semiconductor device according to claim 1, wherein the spacer is formed integrally with the base plate. 6. A semiconductor chip, a base plate for radiating heat generated in the semiconductor chip, an insulating plate for insulating the semiconductor chip from the base plate, and an upper surface of the insulating plate. A method of manufacturing a power semiconductor device comprising: a first electrode; a second electrode provided on a lower surface of the insulating plate; and a spacer for increasing a distance between the base plate and the insulating plate. Is printed on the upper surface of the base plate, a spacer is placed on the brazing paste printed on the upper surface of the base plate, and heat treatment is performed to bond the spacer to the base plate. Bonding the insulating plate to which the electrode serving as the second electrode is bonded to the spacer by soldering. 7. A semiconductor chip, a base plate for radiating heat generated in the semiconductor chip, an insulating plate for insulating the semiconductor chip from the base plate, and an upper surface of the insulating plate. In a method for manufacturing a power semiconductor device, comprising: a first electrode; a second electrode provided on a lower surface of the insulating plate; and a spacer for increasing a distance between the base plate and the insulating plate. Bonding an insulating plate having a surface to which an electrode to be the first electrode is bonded and a spacer integrally formed with the second electrode to the other surface to a base plate by soldering A method for manufacturing a power semiconductor device, comprising: