JPH11328984A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a nonvolatile memory device including a booster circuit that stably forms a desired boosted voltage when power is turned on, and a charge pump circuit that performs efficient operation. SOLUTION: A reference voltage and a divided voltage of a boosted voltage are compared to control the boosted voltage to a predetermined potential corresponding to the reference voltage, and to detect that the output voltage has reached a predetermined reference voltage. Then, the operation of the booster circuit is made effective. A first booster circuit that forms a first boosted voltage that is boosted to be equal to or higher than the power supply voltage by a charge pump circuit that operates in response to the power supply voltage and the pulse signal; And a second booster circuit that forms a second boosted voltage. In the capacitance series type charge pump circuit, during the pump-up period, the capacitance values are distributed so that the capacitance values are sequentially reduced in accordance with the capacitance connection order from the small voltage side connected to the operating voltage to the boosted voltage side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective for use in a charge pump circuit built in a nonvolatile memory.

[0002]

2. Description of the Related Art An electrically erasable EEPROM is a device that collectively collects all memory cells formed on a chip or collectively collects a group of memory cells among memory cells formed on a chip. This is a non-volatile storage device having a function of erasing information. Such a batch erase type EEPR
Regarding OM, in 1980, IEE, International, Solid-State Circuits Conference (IEEE INTERNATIONAL SOLID-STA)
TE CIRCUITS CONFERENCE) Pages 152-153, 1987, IEE, International, Solid-State Circuits Conference (IEEE IN
(TERNATIONAL SOLID-STATE CIRCUITSCONFERENCE) page 76
~ 77, IEE Journal of Solid State Circuits, Vol. 23, No. 5 (198
8 years) Pages 1157 to 1163 (IEEE, J. Solid-State Cic
uits, vol. 23 (1988) pp. 1157-1163).

The International Electronic Device Conference 1987 (Inter
The memory cell of the electrically erasable EEPROM disclosed at the National Electron Device Meeting) has a structure very similar to the memory cell of a normal EPROM.
That is, the memory cell is constituted by an insulated gate field effect transistor (hereinafter, simply referred to as a MOSFET or a transistor) having a two-layer gate structure, and information is substantially held in the transistor as a change in threshold voltage. The operation of writing information to the memory cell is performed by EPR
It is similar to that of OM.

That is, a write operation is performed by injecting hot carriers generated near a drain region connected to a drain electrode into a floating gate. With this write operation, the storage transistor
The threshold voltage as seen from the control gate is higher than that of a storage transistor that has not performed a write operation.

In the erase operation, the control gate is grounded, and a high voltage is applied to the source electrode to generate a high electric field between the floating gate and the source region connected to the source electrode. The electrons accumulated in the floating gate are extracted to the source electrode via the source region by utilizing the tunneling phenomenon.
As a result, the stored information is erased. That is, the threshold voltage of the storage transistor as viewed from its control gate is lowered by the erase operation.

In the read operation, the voltage applied to the drain electrode and the control gate is relatively low so that weak writing to the memory cell, that is, undesired injection of carriers into the floating gate is not performed. Limited to low values. For example, a low voltage of about 1 V is applied to the drain electrode, and a low voltage of about 5 V is applied to the control gate. By detecting the magnitude of the channel current flowing through the storage transistor based on these applied voltages, “0” and “1” of the information stored in the memory cell are determined.

[0007]

The above-described erasing and writing operations for the non-volatile memory cell require a relatively large voltage, and the control gate is used to prevent over-erasing and over-writing. It is necessary to set the potential of the connected word line in accordance with the amount of erasing (threshold voltage) and the amount of writing (threshold voltage), and perform erase verify and write verify of the memory cell. Various types of voltages corresponding to the respective operation modes are required for the erasing operation, the writing operation, and the verifying and reading operations. If such a variety of voltages are supplied from external terminals, the power supply device becomes complicated and the number of power supply terminals increases, so that the usability of the nonvolatile memory becomes extremely poor.

Therefore, the applicant of the present application has considered that the operating voltage is formed in an internal circuit using a charge pump circuit. In the nonvolatile memory, as described above, the selection level of the word line has an important role in determining the write amount or erase amount of the memory cell and “0” or “1” of the stored information, and thus is high. It is necessary to make the voltage stable with accuracy. The voltage thus formed is output in accordance with each operation mode. For example, by using the same word line drive circuit and switching the operation voltage using a switch MOSFET, the potential of the word line is changed corresponding to other times at the time of writing or erasing. In this case, the above switch MOSFET
When a P-channel MOSFET is used when the level of the control signal transmitted to the gate of the P-channel MOSFET is a positive voltage, it is necessary to use a voltage corresponding to the operating voltage in order to turn off the P-channel MOSFET.

[0009] As such an operating voltage, one kind of voltage which is higher than the highest voltage among other kinds of voltages necessary for the operation of the nonvolatile memory by the effective threshold voltage is formed. do it. At this time, in order that the external power supply voltage applied to the non-volatile memory can be shared between the voltage of 5 V and the voltage of 3.3 V, the boosted voltage is divided and compared with the reference voltage to obtain a predetermined voltage. Thus, the control of the operation of the charge pump circuit was studied.
At this time, if the reference voltage is not correctly formed when the power is turned on, the voltage comparison circuit does not operate normally and the limiter function for limiting the boosted voltage even when the boosted voltage becomes higher than the desired voltage does not work. It has been found that the boosted voltage becomes abnormally high, and in the worst case, a new problem arises in that the breakdown voltage of the element is caused. In addition, an efficient charge pump circuit is required to form the above boosted voltage.

An object of the present invention is to provide a semiconductor integrated circuit device having a booster circuit capable of stably forming a desired boosted voltage when power is turned on. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a charge pump circuit that performs an efficient operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the operation of the booster circuit is controlled by comparing the reference voltage and the divided voltage of the boosted voltage, and the booster voltage is controlled by the limiter circuit so that the boosted voltage becomes a predetermined potential corresponding to the reference voltage. And a reference voltage rise detecting circuit for detecting that the output voltage of the reference voltage generating circuit has reached a predetermined reference voltage and enabling the operation of the booster circuit.

The outline of another representative invention among the inventions disclosed in the present application will be briefly described as follows. That is, a first booster circuit that forms a first boosted voltage that is boosted to be equal to or higher than the power supply voltage by a charge pump circuit that operates in response to the power supply voltage and the pulse signal, and the first boosted voltage corresponding to the first boosted voltage A second boosted voltage that is boosted to a voltage equal to or higher than the boosted voltage by a capacitor series charge pump circuit that operates in response to the pulse signal;
To form a boosted voltage.

The outline of still another representative invention disclosed in the present application will be briefly described as follows. That is, in the precharge period, the operating voltage is precharged to a plurality of capacitors, and in the pump-up period, the plurality of capacitors are connected in series, the operating voltage is supplied to one end of the series capacitor, and the other end of the series capacitor is In the capacitor series charge pump circuit that obtains a boosted voltage, the capacitance value sequentially decreases in the pump-up period according to the capacitance connection order from the small voltage side connected to the operating voltage to the boosted voltage side. The capacity values as shown.

[0014]

FIG. 1 is a block diagram showing one embodiment of a voltage generating circuit provided in a semiconductor integrated circuit device such as a nonvolatile memory according to the present invention. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon together with other circuit blocks constituting a nonvolatile memory by a known semiconductor integrated circuit manufacturing technique.

The VCN boosting circuit is constituted by a charge pump circuit as described later, and forms a boosted voltage VCN that is higher than the voltage voltage VCC. Although not particularly limited, the internal operation voltage used in the nonvolatile memory is set higher than the highest internal voltage by the threshold voltage of the N-channel MOSFET. By forming such a boosted voltage VCN, a control signal that can switch-control an N-channel switch MOSFET that outputs an arbitrary operating voltage without a level loss among a plurality of operating voltages used in a nonvolatile memory is provided. Can be formed.

The limiter circuit controls the boosted voltage VCN to a desired constant voltage regardless of whether the power supply voltage VCC supplied from an external terminal is 5 V or 3.3 V. The limiter circuit sets the boosted voltage VCN to 1
/ A and a differential amplifier for comparing the voltage VCN / N divided to / A with the reference voltage VREF.
When the divided voltage VCN / A becomes higher than F, the operation of the VCN booster circuit is stopped by the detection signal CPCP2, and when the divided voltage VCN / A becomes lower than the reference voltage VREF, the detection signal is outputted. The operation of the VCN boosting circuit is started by CPCP2. By such intermittent operation control of the VCN boosting circuit by the limiter circuit, the boosted voltage VCN multiplied by A with respect to the reference voltage VREF can be stably formed.

The above-mentioned differential amplifier section includes a differential type N
Load resistors RL1 and RL2 are provided at the drains of the channel MOSFETs Q1 and Q2, respectively.
MO that allows operating current to flow through the commonly connected sources of 1 and Q2
The SFET Q3 is provided. The above MOSFET Q
The gate 1 is supplied with the divided voltage VCN / A,
The reference voltage VREF is supplied to the gates of the MOSFETs Q2 and Q3. The MOSFET Q3 operates as a constant current source by supplying a reference voltage VREF as a constant voltage to its gate. Although not particularly limited, in order to reduce the operating current of the semiconductor integrated circuit device, the MOSFET Q3 is constituted by a MOSFET having a relatively small size so that only a small current flows.

The VREF (reference voltage) generation circuit receives the high level of the power supply return start signal RESOB such as the power supply voltage VCC, and generates the predetermined reference voltage VREF. This VREF generation circuit is not particularly limited, but is designed to flow only a relatively small DC current in order to reduce current consumption. Therefore, it is necessary to spend a relatively long time from when the start signal RESOB is input by power return to when a desired voltage is formed. That is, the time during which the desired reference voltage VREF is formed in the VREF generation circuit is set longer than the time required to reach the maximum output voltage in the booster circuit.

As a result, the necessary operating current does not flow through the differential amplifier section until the reference voltage VREF is stabilized, so that the detection signal CPCP2 becomes the power supply voltage VCC level via the load resistor RL. VREF <VCN / A
Does not stop the operation of the VCN booster circuit. Therefore, the booster circuit goes into a runaway state in which the maximum output voltage is formed. In particular, when the external power supply voltage VCC is 5 V
When the voltage is relatively high as described above, the booster circuit is designed so that a desired boosted voltage VCN can be obtained even at a voltage of 3.3 V, so that at the above 5 V power supply voltage, the voltage reaches such a high voltage as to cause destruction of the element. Resulting in.

In this embodiment, a VREF rising detection circuit is provided. This VREF rise detection circuit detects that the reference voltage VREF formed by the VREF generation circuit has reached a predetermined voltage. This detection signal is used to limit the operation of the VCN booster circuit before the reference voltage VREF reaches a predetermined voltage. That is, when the VREF rising detection circuit detects that the reference voltage VREF has reached a predetermined voltage, the detection signal SVREF enables the operation of the VCN booster circuit. Specifically, the supply of the pulse signal to the booster circuit is restricted using the gate circuit and the control signal.

FIG. 2 is a circuit diagram showing one embodiment of the VREF rising detection circuit of FIG. Power supply voltage VC
P-channel MOSFET MP1 between C and ground potential
And the N-channel MOSFET MN1 are connected in series,
A bias voltage VBASP close to the ground potential is supplied to the gate of the P-channel MOSFET MP1, and an input voltage VBASN corresponding to the reference voltage VREF is supplied to the gate of the N-channel MOSFET MN1. When the reference voltage VREF does not sufficiently rise immediately after the power is turned on, the on-resistance value of the P-channel MOSFET MP1 becomes N
It is set smaller than the on-resistance value of the channel MOSFET MN1, and sets the input voltage of the inverter circuit IV1 to a high level corresponding to the power supply voltage VCC. Therefore,
Detection signal SVRE output from inverter circuit IV1
F is set to the low level.

Since the input voltage VBASN rises in response to the rise of the reference voltage VREF, the on-resistance of the N-channel MOSFET MN1 gradually decreases. When the input voltage VBASN reaches a desired voltage, the on-resistance value of the N-channel MOSFET MN1 becomes smaller than the on-resistance value of the P-channel MOSFET MP1, and the input voltage of the inverter circuit IV1 is reduced to a logic threshold voltage or less. Therefore, the detection signal SVREF output from the inverter circuit IV1 changes to a high level to enable the operation of the booster circuit as described above.

In this embodiment, although not particularly limited, N
The reference voltage VREF supplied to the gate of the channel MOSFET MN1 can be switched by a metal switch. That is, by selectively forming the metal wiring layer, the reference voltage VREF is formed in a plurality of ways by a resistance circuit or the like, and VREF is supplied as it is, or is set as high as (17/16) VREF. hand,
A method in which the time when the detection signal SVREF is formed is set to be shorter, or a signal in which the time when the detection signal SVREF is formed is set to a low value such as (15/16) VREF, and the like is selected. Can be. The metal switch may be realized by forming a fuse with a metal wiring of the uppermost layer, connecting the terminals, and cutting off all but one with a laser beam or the like.

FIG. 3 is a waveform chart for explaining an example of the operation of the voltage generating circuit according to the present invention. Start signal R formed by the rise of power supply voltage VCC
In response to the high level rising of ESOB, VREF
In the generation circuit, the reference voltage VREF rises toward a desired voltage. The rise of the reference voltage VREF is monitored by a detection circuit, and a period until the reference voltage VREF reaches a desired voltage is defined as a limiter circuit insensitive area, and the detection signal SVR is detected.
EF is set to low level. Thereby, the start signal R
Even if the detection signal CPCP2 of the limiter circuit is set to the high level at the same time as the rise of ESOB, the operation of the VCN boosting circuit is restricted, and the output voltage VCN is maintained at the low level such as the ground potential of the circuit. This allows
Runaway of the booster circuit at power-on can be prevented beforehand.

When the reference voltage VREF formed by the VREF generation circuit reaches a desired voltage, the output signal SVREF of the VREF rising detection circuit rises from a low level to a high level, thereby enabling the operation of the VCN boosting circuit. The boost voltage rises. Then, when the boosted voltage VCN reaches, for example, 7 V, the limiter circuit detects and sets the detection signal CPCP2 to a low level, so that the boosting operation is stopped to prevent the voltage from rising further. When the boosted voltage VCN decreases, the detection signal CPCP2 of the limiter circuit changes to the high level, and the boosting operation is started again. Therefore, the boosted voltage VCN is considered to be substantially constant centering on the set voltage (about 7 V). Is controlled to be

FIG. 4 is a schematic block diagram showing one embodiment of the booster circuit according to the present invention. In this embodiment, in order to obtain an efficient boosted voltage, the power supply voltage VCC
And a booster circuit 2 operating with the boosted voltage VCP formed by the booster circuit 1 as an operating voltage
Are combined to form the above-described boosted voltage VCN from the booster circuit 2. In this case, a capacitor series charge pump circuit is used as the booster circuit 2.

As is well known, charge pump circuits are classified into a capacitance parallel type and a capacitance series type. In the parallel capacitance type, when the number of stages of the capacitor is increased, the effective threshold voltage of the MOSFET that operates as a switch increases as the boosted voltage transmitted increases, and the level loss in the switch MOSFET increases. The boost voltage is limited. On the other hand, in the case of the series capacitance type, the maximum boosted voltage is the same as described above due to the existence of parasitic capacitance generated between each stage and the ground potential of the circuit, which is inevitably generated when the circuit is formed of a semiconductor integrated circuit. Is restricted.

In the above-mentioned capacitance series type, each capacitance is added in series with a voltage stored by precharge to obtain a boosted voltage. A parasitic capacitance is provided between each connection point and the ground potential of the circuit. When such a parasitic capacitance is pumped up, a parallel circuit is formed to perform charge sharing with the above-mentioned series capacitance, thereby limiting an increase in voltage. At this time, the charge share becomes negligible because the combined capacitance value of the series capacitance as viewed from the parasitic capacitance decreases as the number of stages increases. For example, if the capacitance value C connected in series is the same, the combined capacitance value when N capacitance values are connected in series decreases like C / N. Is not negligible even if it is sufficiently smaller than the capacitance value C of the individual capacitors.

In the present invention, attention is paid to the fact that the boosted voltage is limited by the number of stages of the series capacitance in the capacitance series type as described above, in other words, that if the number of stages is small, the parasitic capacitance is hardly affected. The booster circuit is divided into two, and the number of stages in each booster circuit is reduced to realize an efficient boosting operation. That is, the first boosted voltage VCP is formed by the booster circuit 1 using the power supply voltage VCC, and this boosted voltage VCP is used as the operating voltage of the second booster circuit 2,
This is to obtain an output boost voltage VCN.

For example, the booster circuits 1 and 2 are each connected to 3
Using one capacitor, the booster circuit 1 forms a boosted voltage VCP such as 4VCC, and the booster circuit 2 generates the boosted voltage VCP.
By using P as the operating voltage, 4VCP is formed. That is, although six capacitors are used as a whole, a boosted voltage that can be output as high as 4 × 4 VCC can be obtained if the parasitic capacitance is ignored. In other words, it is possible to obtain a voltage that is twice or more as high as 7 VCC when six capacitors are connected in series. Even if the parasitic capacitance is taken into account, the effect can be greatly reduced because of the three-stage connection as described above.

The inventor of the present application has conceived that in order to increase the efficiency of the above-described capacitance series type charge pump circuit, the capacitance ratio of the capacitors connected in series should be unbalanced rather than being equalized. In other words, when a circuit is formed by a semiconductor integrated circuit as described above, the parasitic capacitance is inevitably interposed. Therefore, if the capacitance values of the whole capacitors connected in series are the same, in other words, the semiconductor substrate Under the condition that the total area of the capacitors formed above is the same, it has been found that the influence of the parasitic capacitance can be reduced by setting the capacitance value of the former-stage capacitor larger.

FIG. 5 shows the relationship between the capacitance ratio and output characteristics of a capacitance series type charge pump circuit when three capacitors are used. In the three-stage series type circuit as shown in FIG. 3B, the capacitance value of the central capacitor C1 is set to 100 pF, and the capacitance C0 + C of the capacitors C0 and C2 before and after it is set.
2 = 200 pF, the capacitance C0 of the preceding stage
Looking at the attained voltage and current supply capability when the capacitance value of the capacitor is changed in the range from 80 pF to 150 pF, when the capacitance value of the capacitor C0 is increased, both the attained voltage and the supply capability are increased. The supply capacity is maximized.

FIG. 6 is a schematic circuit diagram of an embodiment of a charge pump circuit of the capacitance series type to which the present invention is applied. In consideration of the above voltage characteristics, the capacitance ratio of the capacitance values C0 to C2 of the capacitors C0 to C2 is C0> C1.
> C2. At this time, the parasitic capacitances (C1β1) and (C2β2) are connected to the input sides of the capacitors C1 and C2.

FIG. 7 is an equivalent circuit diagram for explaining the operation of the capacitance series type charge pump circuit according to the present invention. FIG. 7A shows an equivalent circuit diagram at the time of precharge, and each of the capacitors C0 to Ci includes:
The power supply voltage VCC is precharged and the charge Q at that time is
0 to Qi are respectively set as follows: Q0 = C0 × VCC Q1 = C1 × VCC Q2 = C2 × VCC Qi = Ci × VCC At this time, the parasitic capacitances C1β1, C2β2
... Ciβi, only 0 V is applied to them, so that each of the charges Q1p, Q2p,. In FIG. 3, the power supply voltage V is applied to each of the capacitors C0 to Ci.
A switch for precharging for supplying a ground potential of 0 V between the CC and the circuit is omitted. A switch, which is exemplarily shown as a representative and connects the capacitors C0 to Ci in series, is in an off state at this time.

FIG. 7B shows an equivalent circuit diagram at the time of pump-up, in which the capacitors C0 to Ci are connected in series. Each capacitor C after this pump-up
0 to Ci charges Q0 'to Qi' and the parasitic capacitance C1β1
The charges Q1p ′ to Qip ′ of Ciβi are respectively Q0 ′ = C0 × V0 Q1 ′ = C1 × V1 Q2 ′ = C2 × V2 Qi ′ = Ci × Vi, and Q1p ′ = (C1β1) × (VCC + V0) Q2p ′ = (C2β2) × (VCC + V0 + V1) Qip ′ = (Ciβi) × (VCC + V0 + V1 +...
Vi-1).

By the charge preservation before and after the pump-up, Q0-Q1 + Q1p = Q0'-Q1 '+ Q1p' Q1-Q2 + Q2p = Q1'-Q2 '+ Q2p' Qi-1-Qi + Qip = Qi-1'-Qi '+ Qi
p 'Qi = Qi' And the ultimate voltage V is as follows: V = VCC + V0 + V1 +... Vi.

Each of the voltages V0 to Vi is numerically calculated from the above-mentioned charge conservation formula, and the reached voltage V can be obtained by the above-mentioned reached voltage formula. The case where i = 2 is the reached voltage shown in FIG. On the other hand, when the above equation is solved analytically, the following equation is obtained. V0 = VCC-D [2C1β1 + 3C2β2] VCC V1 = VCC-D [3C2β2] VCC V2 = VCC where D = 1 / (C0 + C1β1 + 2C2β2), where C0 = C1 = C2, and 1≫β1β2 (the secondary term of β Ignored). As can be seen from the above equation, V0 is lower than V1 because all the parasitic capacitances (C1β1 attached to C1 and C2β2 attached to C2) of the subsequent stage capacitors are visible. Therefore, as described above, the capacitance value of the capacitor C0 is set to be larger than the capacitance values of the capacitors C1 and C2 at the subsequent stages, the effect of the voltage drop due to the parasitic capacitance is suppressed, and the ultimate voltage V is increased. This is the same for the relationship between C1 and C2.

FIG. 8 is a schematic block diagram showing one embodiment of a nonvolatile memory to which the present invention is applied. Each circuit block in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The memory matrix is
A nonvolatile memory cell having a stacked gate structure including a control gate and a floating gate is arranged in a matrix at an intersection of a word line and a data line. The control gate of the memory cell is connected to a corresponding word line, the drain is connected to a corresponding data line, and the source is connected to a corresponding source line.
SVC is a source potential control circuit.

The address buffer XADB has an external terminal A
The decoder XDCR receives the X address signal supplied from X and receives the received address signal and the internal voltages Vrw, Vww, Vwv, Vew and Vev, and changes the potentials of the selected word line and the unselected word line. The setting is made according to each operation mode of writing, erasing, and reading.

The memory matrix of this embodiment (Memory
Matrix) data lines are provided with sense amplifiers SA and write circuits DR in one-to-one correspondence. The address buffer YADB fetches a Y address signal supplied from the external terminal AY, and the decoder YCR decodes the fetched address signal and supplies a data line selection signal to the data line selection circuit YG. The data line selection circuit YG performs a substantial data line selection operation according to the selection signal. That is, at the time of a read operation, the amplified signal of the sense amplifier SA is selected, and at the time of a write operation, write data is transmitted to the write circuit DR. The voltages Vrd and Vwd are used in the read operation and the write operation.

The multiplexer MP has a data terminal I / O
Mode control circuit MC
And the operation of transmitting the write data supplied from the data terminal I / O to the data input circuit DIB. The output signal of the data output circuit DOB is transmitted to the data terminal I / O through the multiplexer MP.

The control signal input circuit CSB receives the control signals / CE, / OE, / WE and the clock signal SC supplied from the external terminals and transmits them to the mode control circuit MC, where writing, reading and erasing operations are performed. In addition, various mode determinations such as command input are performed. Vcc is a power supply terminal to which a power supply voltage such as 3.3 V is supplied, although not particularly limited. Vss is a ground terminal to which a circuit ground potential such as 0 V is applied.

The voltage generating circuit VS includes a positive boosting voltage generating circuit such as +12 V, a negative voltage generating circuit such as -10 V, and an intermediate voltage generating circuit near the power supply voltage Vcc as described above. The indicated voltages Vrw, Vww,
Vwv, Vew, Vev, Vec, Vrd, Vwd and the above-mentioned boosted voltage VCN are formed.

FIG. 9 shows a batch erase type EE according to the present invention.
A block diagram of another embodiment of the PROM is shown.
In this embodiment, although not particularly limited, the memory array includes four memory mats MAT. Each memory mat MAT is provided with a sub-decoder SUB-DCR that forms a word line WL selection signal. Since the word line pitch is formed narrow for high integration,
Sub-decoder SUB- sandwiched between memory mats MAT
The DCR forms a word line selection signal for the memory mats MAT on both sides. Therefore, as exemplarily shown, the word lines of the memory mat MAT are alternately connected to every other two sub-decoders SUB-DCR provided therebetween.

The main decoder MAN-DCR includes a selection MOSFET for selecting a plurality of memory cells as described later.
And a circuit for forming a selection level and a non-selection level of the sub-decoder SUB-DCR. The gate decoder GDCR is connected to the main decoder MAN-D.
1 in one memory block selected by CR
A selection signal for selecting one memory cell is formed.

The storage transistor constituting the nonvolatile memory cell formed in the memory mat MAT is not particularly limited, but the one in which charge and charge are injected into and released from the floating gate by tunnel current in both erase and write operations. It is. Alternatively, only the erasing operation may be performed by the tunnel current as described above.

The sense amplifier SA is not particularly limited, but is divided into two groups as described later, and each of them is controlled in an amplification operation by the sense amplifier control circuit SAC. Although not particularly limited, in the first read cycle, both of the sense amplifiers are activated, and thereafter, in the case of continuous reading with word line switching, the read signal from one sense amplifier group is terminated and the other sense amplifier is terminated. While the serial readout signal is being output from the group, the word line is switched, and the one sense amplifier group starts the amplification operation.

The sense amplifier SA has a latch function. When receiving a read signal required for an amplification operation from a data line, the sense amplifier SA is separated from the data line and amplifies and holds the fetched signal. Therefore, the signal selected by the data selection circuit YG is applied to the data output buffer O
B, and the word line corresponding to the next address can be switched in parallel with such a signal output operation as described above.

The status register SREG receives the signal TS
Thus, status data can be received, and the operation state can be monitored from the outside through the data output buffer OB as necessary. In this embodiment, the continuous access operation and the electrical writing and erasing operations are performed as described above, and it is necessary to know the internal state from the outside during each operation. A register SREG is provided.

The voltage generating circuit VS receives the power supply voltage VCC such as 3.3 V and the ground potential VSS of the circuit, and receives various voltages Vpw, Vpv, Vew, Ved, Vev and V
r as a DC-DC converter. This voltage generation circuit VS includes the booster circuit shown in FIGS. 1, 3 and 5.

The address buffer ADB takes in the address signal Ai supplied from the external terminal, and makes the address latch ALH hold the address signal. Signal T
A is a control signal for latching the address signal, and TSC is an internal serial clock.

The address generation circuit ADG performs an address increment operation by an internal serial clock TSC generated in synchronization with an externally supplied clock SC, and activates a sense amplifier SA corresponding to an odd-numbered data line. An address signal Ayo, an address signal Aye for activating the sense amplifier SA corresponding to the even-numbered data line, and a word line switching signal AC are generated. That is, in the semiconductor memory device of this embodiment, only by inputting a designated start address, an address signal for subsequent continuous access is internally generated in response to a clock SC supplied from an external terminal. . The clock signal S
Although not particularly limited, C can be used to form a clock signal for the charge pump circuit.
The signals Ayo and Aye and AC and / AC are supplied to the sense amplifier control circuit SAC. Here, / attached to the signal AC indicates that the signal is a bar signal, and the signal / AC indicates that the low level is the active level. This is the same for the other signals described below.

The data selection circuit YG forms a selection signal for one data line at the time of a read operation in response to the Y-system address signal Ay, selects an amplified signal of the sense amplifier corresponding to the data line, and selects a data output buffer OB. Tell In a write operation, a select signal for one data line is formed, and a signal corresponding to write data input from the data input buffer IB is transmitted to the data line.

The command decoder CDCR decodes the color input from the data input buffer IB and transmits the command data Di to the control circuit CONT described below. The signal TC is a command decoder control signal, which takes in a command and controls the decoder.

The control circuit CSB includes a mode control circuit MC, and includes a chip enable signal / CE, an output enable signal / OE, supplied from external terminals.
In response to the write enable signal / WE, the clock SC and the reset signal RS, various timing signals necessary for the operation of the internal circuit are formed. The signal TMX is a main decoder control signal, and is a signal for switching between positive / negative logic at the time of program-program verify. The signal TXG is
This is a gate decoder control signal. Signal TV is a power supply circuit control signal. The signal TA is an address buffer control signal, and controls an address latch and the like. Signal TI
Is a data input buffer control signal, which controls data and command capture.

The signal TO is a data output buffer control signal for controlling data output and the like. The signal TC is a command decoder control signal, and controls a command fetching and decoding. The signal TS is a status register control signal, and performs control such as setting or resetting of the status register SREG. Signal TSA is a sense amplifier control signal, and is used for controlling activation timing. Signal TSC is an internal serial clock. The signal AC is a word line switching signal. Signal O
i is output data output from the data output buffer OB, the signal Do is status data, and the signal D
i is command data. Also, the signal RDY / BUS
Y is a signal for outputting the state of the chip.

In addition, the signal Ax0 supplied from the address latch ALH to the main decoder MAN-DCR is an X-system address signal designating the memory block to be selected, and supplied from the address latch ALH to the gate decoder GDCR. The signal Ax1 is an X-system address signal designating one word line in one memory block. The signal Ay supplied to the Y gate YG is a Y-system address signal.

Vpw is a word line voltage at the time of writing.
Vpv is a word line voltage at the time of write verification. V
ev is the word line voltage during erase verify. Vew is a word line voltage at the time of erasing. Ved is the data line voltage at the time of erasing. Vr is a data line precharge voltage.

FIG. 10 is a schematic circuit diagram showing one embodiment of the memory mat and its peripheral portion. The memory cell is a MOSFET having a stacked gate structure including the similar control gate and floating gate. In this embodiment, as will be described later, both the write operation and the erase operation are performed using a tunnel current passing through a thin oxide film.

The storage MOSFET constituting the memory cell
T has a plurality of blocks, and a drain and a source are shared. The common drain of the storage MOSFET is connected to the data line DL through the selection MOSFET. The common source of the storage MOSFET is supplied with the ground potential of the circuit through the selection MOSFET. The control gate of the storage MOSFET is
Connected to word line WL. The selection MOSFET is
It is selected by a selection line extending in parallel with the word line WL. That is, the selection MOSFET is regarded as a main word line selected by the main decoder MAN-DCR.

As described above, the memory cells are divided into blocks, each of which is connected to the data line DL via the selection MOSFET.
And a structure for applying a ground potential to a circuit can reduce stress on unselected memory cells. That is, a memory cell in which a word line is selected and a data line is deselected or, conversely, a word line is deselected,
By setting the data line to the non-selected state, the voltage for writing or erasing is prevented from being applied to a memory cell to hold data in a writing or erasing operation. In this configuration, the above-described stress is applied only to a small number of memory cells in the block.

In this embodiment, adjacent data lines DL are divided into odd and even data lines. Then, a short MOSFET is provided corresponding to each. This short MOSFET alternately selects the odd-numbered and even-numbered data lines DL, sets the unselected data lines DL to a fixed level of the circuit ground potential, and sets the mutual coupling between adjacent data lines DL. This is to reduce ring noise. In response to such a configuration of the data line DL, the data selection circuit YG is also selected for the sense amplifier SA that amplifies the read signal appearing on the data line DL, divided into an odd number and an even number. The data selection circuit YG is realized by a transfer MOSFET described later.

One of the memory cells in the block selected by the main decoder MAN-DCR is selected by the sub-decoder SUB-DCR. The sub-decoder SUB-DCR selects one word line WL in the block. Such a selection signal for one word line is formed by the gate decoder GDCR. That is, the sub-decoder SUB-DCR receives the word line selection signal formed by the gate decoder GDCR and the selection / non-selection level formed according to the operation mode formed by the main decoder MAN-DCR. , And a drive signal for selecting / non-selecting a word line in the block.

[0065]

[Table 1]

The storage MOSFET in each of the read, write, and erase operation modes
T gate voltage (word line WL) Vg, drain voltage V
As d and the source voltage Vs, voltages as shown in Table 1 above are given. As described above, the gate voltage Vg and the drain voltage V
d and the relative potential relationship with each voltage Vs,
By generating a tunnel current through a thin gate insulating film and injecting or discharging charges to / from the floating gate, the threshold voltage is changed to perform a write operation and an erase operation. In Table 1, in non-selection, two voltages or states separated by /
It corresponds to the selected block / non-selected block.

The above 12V, -10V, 4V and -4V are formed by the power supply circuit as in the above embodiment. The drain voltage Vd of 1 V is directly formed by stepping down a voltage of 3.3 V by a step-down circuit. When such various voltages are outputted through the switch MOSFET, a switch control signal using the high boosted voltage VCN as described above is formed. Since a control signal such as -10 V is required to output the voltage of -10 V, a boosted voltage is similarly formed on the negative voltage side. In this case, an N-channel MOSFET is used as a switch.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a reference voltage and a divided voltage of the boosted voltage are applied to a booster circuit that forms a boosted voltage that is boosted to be equal to or higher than the power supply voltage by a charge pump circuit that operates in response to the power supply voltage and the pulse signal. The operation is controlled by a limiter circuit for comparing the boosted voltage to a predetermined potential corresponding to the reference voltage, and the output voltage of the reference voltage generation circuit is determined to reach a predetermined reference voltage. By making the operation of the booster circuit effective by detecting with the voltage rise detecting circuit, an effect that runaway of the boosted voltage at the time of turning on the power can be prevented can be obtained.

(2) As the booster circuit, a first booster circuit that forms a first boosted voltage that is boosted to be equal to or higher than the power supply voltage by a charge pump circuit that operates by receiving a power supply voltage and a pulse signal; A combination of a first boosted voltage and a second booster circuit that forms a second boosted voltage that is boosted to a voltage equal to or higher than the boosted voltage by a capacity series charge pump circuit that operates in response to a pulse signal corresponding to the first boosted voltage Accordingly, the effect that a high ultimate voltage can be obtained because the influence of the parasitic capacitance can be reduced can be obtained.

(3) A first booster circuit for forming a first boosted voltage that is boosted above the power supply voltage by a charge pump circuit that operates in response to a power supply voltage and a pulse signal, and the first boosted voltage And a second booster circuit that forms a second boosted voltage that is boosted to be equal to or higher than the boosted voltage by a capacitance series charge pump circuit that operates in response to a pulse signal corresponding to the internal power supply circuit. By using a semiconductor integrated circuit, it is possible to obtain an effect that a charge pump circuit capable of obtaining a high ultimate voltage can be obtained because the influence of the parasitic capacitance can be reduced.

(4) The first booster circuit of (3) is also a charge pump circuit of a capacitance series type, so that
Since the effect of the effective threshold voltage of the SFET can be eliminated, the efficiency can be further improved.

(5) As the capacitance series type charge pump circuit of (3), when the pump-up is performed, the capacitance values are distributed according to the capacitance connection order from the smaller voltage side so that the respective capacitance values become smaller. It is possible to prevent the holding voltage of the capacitor at the time of the increase from being lowered due to the charge share with the parasitic capacitance of the subsequent stage, and it is possible to obtain the effect that the holding voltage of each stage can be made substantially equal and the attained voltage can be increased. .

(6) In the precharge period, the operating voltage is precharged to a plurality of capacitors, and in the pump-up period, the plurality of capacitors are connected in series to supply the operating voltage to one end of the series capacitor. In a capacitance series type charge pump circuit that obtains a boosted voltage from the other end of
In the pump-up period, by distributing the capacitance values so that the capacitance values are sequentially reduced in accordance with the capacitance connection order from the small voltage side connected to the operating voltage to the boosted voltage side, the pump-up time is reduced. Can be prevented from decreasing due to the charge share with the parasitic capacitance of the subsequent stage, the holding voltages of the respective stages can be made substantially equal, and the ultimate voltage can be increased.

(7) By setting the boosted voltage to an operating voltage used for writing and erasing operations of the nonvolatile memory cell, power consumption can be reduced while preventing element destruction at power-on. The effect that it can be obtained is obtained.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the specific configuration of each circuit other than the reference voltage rise detection circuit and the charge pump circuit can employ various embodiments. A specific configuration of a nonvolatile memory using the above-described voltage generation circuit can employ various embodiments. The booster circuit according to the present invention can be used for various semiconductor integrated circuit devices requiring a boosted voltage in addition to the nonvolatile memory.

[0076]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a reference voltage and a divided voltage of the boosted voltage are compared with a booster circuit that forms a boosted voltage that is boosted above the power supply voltage by a charge pump circuit that operates by receiving a power supply voltage and a pulse signal. The operation is controlled by a limiter circuit so that the boosted voltage is controlled to a predetermined potential corresponding to the reference voltage, and a reference voltage rise detection is made when the output voltage of the reference voltage generation circuit reaches the predetermined reference voltage. By making the operation of the booster circuit effective by detecting by the circuit, runaway of the boosted voltage at the time of power-on can be prevented.

A first booster circuit for forming a first boosted voltage that is boosted above the power supply voltage by a charge pump circuit that operates in response to a power supply voltage and a pulse signal; And a second booster circuit that forms a second boosted voltage that is boosted to a voltage equal to or higher than the above boosted voltage by a capacitance series type charge pump circuit that operates in response to the generated pulse signal. With this configuration, it is possible to obtain a charge pump circuit that can obtain a high ultimate voltage because the influence of the parasitic capacitance can be reduced.

In the precharge period, an operating voltage is precharged to a plurality of capacitors, and in the pump-up period, the plurality of capacitors are connected in series to supply the operating voltage to one end of the series capacitor and the other end of the series capacitor. In the capacitance series type charge pump circuit configured to obtain a boosted voltage from the above, in the pump-up period, the capacitance value sequentially decreases according to the capacitance connection order from the small voltage side connected to the operating voltage to the boosted voltage side. By distributing the capacitance values in such a manner, the holding voltage of the capacitor at the time of pump-up can be prevented from decreasing due to charge sharing with the parasitic capacitance on the subsequent stage, and the holding voltage of each stage can be made almost equal. , The ultimate voltage can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a voltage generation circuit provided in a semiconductor integrated circuit device such as a nonvolatile memory according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a VREF rising detection circuit of FIG. 1;

FIG. 3 is a waveform chart for explaining an example of the operation of the voltage generation circuit according to the present invention.

FIG. 4 is a schematic block diagram showing one embodiment of a booster circuit according to the present invention.

FIG. 5 is an explanatory diagram of a capacitance ratio and output characteristics of a capacitance series type charge pump circuit when three capacitors are used.

FIG. 6 is a schematic circuit diagram showing an embodiment of a capacitance series type charge pump circuit to which the present invention is applied.

FIG. 7 is an equivalent circuit diagram for explaining the operation of the capacitance series type charge pump circuit according to the present invention.

FIG. 8 is a schematic block diagram showing one embodiment of a nonvolatile memory to which the present invention is applied.

FIG. 9 is a block erase EEPROM to which the present invention is applied;
FIG. 10 is a block diagram showing another embodiment of the present invention.

FIG. 10 is a schematic circuit diagram showing an embodiment of the memory mat of FIG. 9 and peripheral portions thereof.

[Explanation of symbols]

Q1-Q10, MP1, MN1 ... MOSFET, RL
1, RL2: load, IV1: inverter circuit, C0 to C
i: capacitor, C1β1 to Ciβi: parasitic capacitance, V
S: voltage generating circuit, XADB: X address buffer, X
DCR ... X decoder, YADB ... Y address buffer,
ADCR: Y decoder, SA: sense amplifier, DR: write circuit, MC: mode control circuit, MP: multiplexer, SVC: source potential control circuit, YG: data line selection circuit, CSB: control signal buffer circuit, MA
T: memory mat, SUB-DCR: sub-decoder, M
AN-DCR: Main decoder, GDCR: Gate decoder, SCB (MC): Control circuit, ADB: Address buffer, ALH: Address latch, ADG: Address generation circuit, VG: Voltage generation circuit, CDCR: Command decoder, SREG: Status Register, SAC: sense amplifier control circuit, SA: sense amplifier, YG: data line selection circuit, IB: data input buffer, OB: data output buffer, DL: data line, WL: word line.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jiro Kishimoto 3-16-1, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shoji Kubono 5-chome, Josuihoncho, Kodaira-shi, Tokyo 22-1, Hitachi Co., Ltd. Hitachi Systems Ltd. Systems (72) Inventor Hiroshi Sato 6-16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Harada Toshinori 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Stock Company, Ltd. Hitachi Ultra-SII Systems Co., Ltd. (72) Megumi Maejima 2-3-2, Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In company

Claims (7)

[Claims] 1. A booster circuit that forms a boosted voltage that is boosted above the power supply voltage by a charge pump circuit that operates by receiving a power supply voltage and a pulse signal, and a reference voltage that generates a reference voltage by receiving the power supply voltage A generation circuit, a limiter circuit that controls the operation of the booster circuit by comparing the reference voltage and the divided voltage of the boosted voltage, and controls the boosted voltage to be a predetermined potential corresponding to the reference voltage. A reference voltage rise detection circuit for detecting that the output voltage of the reference voltage generation circuit has reached a predetermined reference voltage and enabling the operation of the booster circuit. apparatus. 2. A booster circuit, comprising: a first booster circuit that forms a first boosted voltage boosted to be equal to or higher than the power supply voltage by a charge pump circuit that operates in response to the power supply voltage and a pulse signal; A second booster circuit that forms a second boosted voltage that is boosted to be equal to or higher than the boosted voltage by a capacitance series type charge pump circuit that operates in response to the first boosted voltage and a corresponding pulse signal; 2. The semiconductor integrated circuit device according to claim 1, wherein said second boosted voltage is used as an output boosted voltage. 3. A first booster circuit for forming a first boosted voltage that is boosted above the power supply voltage by a charge pump circuit that operates in response to a power supply voltage and a pulse signal; And a second booster circuit that forms a second boosted voltage that is boosted to a voltage equal to or higher than the boosted voltage by a capacitance series charge pump circuit that operates in response to the corresponding pulse signal. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The semiconductor integrated circuit device according to claim 2, wherein said first booster circuit is a capacitance series charge pump circuit. 5. The capacity-series charge pump circuit is characterized in that, at the time of pump-up, the capacitance values are distributed so that the capacitance values become smaller in accordance with the capacitance connection order from the smaller voltage side. Claim 3
Alternatively, the semiconductor integrated circuit device according to claim 4. 6. In a precharge period, an operating voltage is precharged to a plurality of capacitors, and in a pump-up period, the plurality of capacitors are connected in series.
A capacitor series charge pump circuit configured to supply the operating voltage to one end of the series capacitor and obtain a boosted voltage from the other end of the series capacitor; A semiconductor integrated circuit device, wherein capacitance values are distributed so that capacitance values are sequentially reduced in accordance with a capacitance connection order from a small voltage side connected to the operating voltage to the boosted voltage side. 7. The semiconductor integrated circuit device according to claim 1, wherein the boosted voltage is an operating voltage used for a write / erase operation of a nonvolatile memory cell.