JPH11339403A - Information reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information reproducing apparatus capable of decoding, with single Viterbi decoding means, information that has been channel-encoded by way of a plurality of different block codes, and obtaining stable synchronization against noises. SOLUTION: Mode switching means 96 switches addition and comparison selecting means ACS 21c in variable Viterbi decoding means 99, so that the status transition of the Viterbi decoding becomes variable. Thus, information that has been channel-encoded by a plurality of different block codes is set in a decodable condition. In addition, the mode switching as set forth above is performed between a synchronization information region and an information region recorded on a recording medium, thereby obtaining stable synchronization for Viterbi decoding against noises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus, and more particularly to an information reproducing apparatus in which information is reproduced as sectors and decoded by Viterbi decoding means.

[0002]

2. Description of the Related Art As an information reproducing apparatus for reproducing information recorded on a tape-shaped or disk-shaped recording medium, for example, a magnetic reproducing apparatus for reproducing information from a magnetic disk or a magnetic tape by a magnetic head, or an optical pickup by an optical pickup. There is a magneto-optical reproducing device for reproducing information from a magnetic disk.

For example, in a magneto-optical reproducing apparatus which irradiates a magneto-optical disk with a laser beam and receives reflected light generated thereby to generate a reproduction signal, conventionally, synchronization information recorded on the magneto-optical disk is included. The information is divided into sectors prior to recording, and the information unit of the information is, for example, RLL (1, 7) which is a variable length code with a constraint described later.
(Hereinafter, this coding is referred to as channel coding, and a channel-coded information unit is referred to as a recording information unit), and further modulated by means of a precode described later. The magneto-optical reproducing apparatus reproduces a recording information unit from a magneto-optical disk, equalizes a reproduced signal with a partial response waveform equalization characteristic described later, decodes the original recording information unit by Viterbi decoding (hereinafter, referred to as a decoded information unit). ) Often restore information.

Here, the RLL (1,7) code will be described. For the information unit in the information, a long code is assigned to a unit having a small appearance probability, and a long code is assigned to a unit having a large appearance probability. This is a variable length code intended to shorten the average code length. Among such variable-length codes, those in which the minimum value of the number of 0s between 1 and 1 (this is called a run) is 1 and the maximum value is 7 are RLL (1,
7). The aforementioned constraint of the minimum value 1 is provided to suppress intersymbol interference caused by adjacent waveforms of a reproduced signal interfering with each other. The constraint of the maximum value 7 is provided so that the synchronization signal can be stably extracted from the signal waveform sequence.

[0005] Next, the partial response allows interference between reproduced signal waveforms from the beginning and sets the amount of interference at each sample point to a constant integer ratio to keep the band limitation within the Nyquist frequency. Waveform equalization. In addition, the precode is a method of recording the characteristic opposite to the partial response waveform equalization characteristic in the above-mentioned channel-encoded information in order to suppress the propagation of an error in the partial response waveform equalized output. It is for giving it ahead.

In recent years, with the increase in storage capacity of recording media,
It has means capable of reproducing information recorded and encoded using the above-mentioned RLL (1, 7), and also capable of reproducing recorded information encoded with a code having higher encoding efficiency. A new information reproducing device is required.

[0007]

As described above, RLL is used.
(1, 7) has a constraint of a minimum value of 1 and a maximum value of 7, but without such a constraint, a more efficient code exists in the block code. Here, the block code is a code obtained by mapping a binary finite sequence of information units '1' and '0' to another binary finite sequence of '1' and '0'.

Codes without restrictions as described above, in particular, minimum value 1
In the case of using a high-efficiency block code in which the restriction of the above is removed, the state transition of the reproduction output is different from the state transition of the reproduction output of the RLL (1, 7), so that the conventional RLL (1, 7)
It is necessary to prepare a plurality of Viterbi decoding means corresponding to each code in order to enable decoding of For this reason, there has been a problem that the scale and power consumption of the information reproducing apparatus increase.

Also, in a reproduced signal waveform of a high-efficiency block code from which the restriction of the minimum value 1 has been removed, the value of each sample point is closer to each other than in the case of the RLL (1, 7) code ( Hereinafter, this is referred to as a small Euclidean distance), it is extremely weak to fixed noise or other random noise due to scratches on a recording medium, and it is extremely difficult to extract a synchronization signal for synchronizing by a PLL, and therefore, synchronization is unstable. There was a problem that it was easy to become.

The present invention has been made in view of such a point, and uses a single Viterbi decoding means for both a conventional RLL (1,7) code and a highly efficient block code. An object of the present invention is to provide an information reproducing apparatus capable of performing stable reproduction even when a conventional RLL (1,7) code is used and when a highly efficient block code is used.

[0011]

In order to solve the above-mentioned problems, an information reproducing apparatus according to the present invention divides information into a plurality of information units, and synchronizes at least the phases of the plurality of information units. In order to add information, reproduce a sector from a recording medium on which information is recorded as a sector, and decode and extract synchronization information stable from noise from the sector, a recording on which the synchronization information is recorded is performed. A mode switching unit for changing a state transition condition of Viterbi decoding between an area on the medium and an area on the recording medium on which the plurality of information units are recorded, and the state transition can be controlled by the mode switching unit. A variable Viterbi decoding means.

According to a preferred embodiment of the information reproducing apparatus of the present invention, the mode switching timing can be controlled in accordance with reproduction conditions by control information sent serially from the outside, and a specific state transition of Viterbi decoding It has a mode switching means capable of fixedly selecting conditions.

Further, as a preferred embodiment of the information reproducing apparatus of the present invention, a variable Viterbi decoding means capable of changing the state transition by externally controlling means for comparing and selecting the likelihood of the state transition is provided. is there.

The operation of the above-described means will be described below. The variable Viterbi decoding means enables a plurality of Viterbi decoding means having different state transition conditions to be realized by a single variable Viterbi decoding means. Can be significantly reduced. Further, when combined with the mode switching means described above, in a plurality of different Viterbi decodings, a synchronization signal can be decoded and extracted stably with respect to noise, and stable Viterbi decoding can be performed. It is also possible to select one of the Viterbi decoding means and fix the mode.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an information reproducing apparatus for reproducing information recorded on a tape-shaped or disk-shaped recording medium, for example, a magnetic reproducing apparatus for reproducing information from a magnetic disk or a magnetic tape with a magnetic head, The present invention is applicable to an optical information reproducing apparatus for reproducing information from a layer-change disk by an optical pickup and a magneto-optical reproducing apparatus for reproducing information from a magneto-optical disk by an optical pickup. In particular, an example of a magneto-optical reproducing apparatus for reproducing information from a magneto-optical disk by an optical pickup will be described.

[0016]

EXAMPLES In order to facilitate understanding of the present invention,
First, in a magneto-optical reproducing apparatus having a reproducing system for performing Viterbi decoding, an RLL (1, 7) code is used, and a PR (described later) is used.
[(1.A) Outline of magneto-optical reproducing apparatus] using (1, 2, 1) type partial response waveform equalization characteristics,
[(1.B) Outline of sector format of recording medium],
[(1.C) Outline of 4-level 4-state Viterbi decoding method] and [(1.D) Outline of configuration and operation of 4-level 4-state Viterbi decoding means] for implementing 4-level 4-state Viterbi decoding method will be described. Secondly, [(2) in the case of using the same PR (1,2,1) type partial response waveform equalization characteristic and sector format as described above and using a block code from which the constraint of the minimum value 1 has been removed. .A) Outline of 5-valued 4-state Viterbi decoding method] and [(2.B) Outline of configuration and operation of 5-valued 4-state Viterbi decoding means] are described below with respect to the difference between the former and [(2.C). ) Embodiment of information reproducing apparatus of the present invention].

[(1.A) Outline of Magneto-optical Reproducing Apparatus] The outline of the above-described magneto-optical reproducing apparatus will be described below with reference to FIGS.
This will be described with reference to FIG. FIG. 1 is a block diagram showing an overall configuration of an example of a magneto-optical reproducing device having a reproducing system for performing a Viterbi decoding method. On the magneto-optical disk, as described above,
The RLL (1, 7) code is precoded and recorded as pits. FIG. 2 shows the relationship between recorded pits and precode output. A recording method in which pits are formed for "1" and no pits are formed for "0" during precode output is referred to as a mark position recording method. On the other hand, a recording method in which the inversion of the polarity at the boundary of each bit in the precode output expressed by the edge of each pit corresponds to, for example, “1” is referred to as a mark edge recording method. At the time of reproduction, the boundaries of each bit in the reproduction signal are recognized according to a read clock DCK generated as described later.

In FIG. 1, an optical pickup 7 irradiates a laser beam to the magneto-optical disk 6, receives reflected light generated thereby, and generates a reproduction signal. The playback signal is
It is composed of a sum signal R +, a difference signal R-, a focus error signal (not shown), and a tracking signal. The sum signal R + is supplied to the sum signal / difference signal switch 10 after the gain is adjusted by the amplifier 8. The difference signal R− is supplied to a sum signal / difference signal changeover switch 10 after gain adjustment and the like are performed by the amplifier 9. Further, the focus error signal is supplied to a means (not shown) for eliminating the focus error. On the other hand, the tracking error signal is supplied to a servo system or the like (not shown) and used in those operations.

The sum signal / difference signal switching switch 10 is supplied with a sum signal / difference signal switching signal S as described later.
The sum signal / difference signal changeover switch 10 supplies the sum signal R + or the difference signal R− to the filter unit 11 in accordance with the sum signal / difference signal change signal S as follows. That is,
In a sector format of the magneto-optical disk 6 described later, a reproduction signal reproduced from a portion formed by embossing is a sum signal / difference signal switch 10.
, The sum signal R + is supplied to the filter unit 11. Further, during a period in which a reproduction signal reproduced from a magneto-optically recorded portion is supplied to the sum signal / difference signal switch 10, the difference signal R− is supplied to the filter unit 11.

The sum signal / difference signal switching signal S is generated, for example, as follows. That is, first, a signal reproduced from a predetermined pattern defined in the sector format is detected from the reproduced signal. As such a predetermined pattern, for example, a sector mark SM described later is used. Then, the sum signal / difference signal switching signal S is generated at a predetermined time point recognized by a method such as counting read clocks, which will be described later, with reference to the time point at which the detection is performed.

The filter section 11 includes a low-pass filter for performing noise cut and a waveform equalizer for performing waveform equalization. As will be described later, the waveform equalization characteristics used in the waveform equalization process at this time are adapted to the Viterbi decoding method performed by the Viterbi decoding unit 13. The A / D converter 12 supplied with the output of the filter unit 11 samples the reproduced signal value z (k) according to the read clock DCK supplied as described later.

The Viterbi decoding means 13 outputs a reproduced signal value z
Based on (k), the above-described decoded information unit is generated by the Viterbi decoding method. Such a decoded information unit is a maximum likelihood decoded sequence for the recorded information unit recorded as described above. Therefore, when there is no decoding error, the decoding information unit matches the recording information unit.

The decoded information unit is supplied to the controller 2. As described above, the recording information unit is a codeword generated from the information unit by encoding such as channel encoding. Therefore, if the decoding error rate is sufficiently low, the decoding information unit can be regarded as a recording information unit as a codeword. The controller 2 processes the information unit and the like by performing a decoding process on the code such as the channel coding described above for the decoded information unit.

The output of the Viterbi decoding means 13 is PL
It is also supplied to the L section 14. The PLL unit 14 generates a read clock DCK based on the supplied signal. The read clock DCK is supplied to the controller 2, the A / D converter 12, the Viterbi decoding means 13, and the like. The operations of the controller 2, the A / D converter 12, and the Viterbi decoding means 13 are performed at a timing according to the read clock DCK. Further, the read clock DCK is supplied to a timing generator (not shown). The timing generator generates a signal for controlling the timing of the apparatus, for example, for switching the reproduction operation.

[(1.B) Outline of Sector Format of Recording Medium] The sector format of the recording medium reproduced by the magneto-optical reproducing apparatus will be described below with reference to FIG. Information is recorded on the magneto-optical disk 6 using a sector as a unit of recording / reproduction. An example of a sector format used in the magneto-optical disk 6 will be described with reference to FIG. As shown in FIG. 3A, one sector includes a header, an ALPC, a gap,
It is divided into VFO ₃ , sync, data field, and buffer areas. The numbers given in FIG. 3 represent the number of bytes. Encoded data such as block encoding is recorded on the magneto-optical disk 6. For example, 8 bits are converted into 12 channel bits and recorded.

As an example of this sector format, a format having a user data amount of 1024 bytes and a format having a user data amount of 512 bytes are prepared. In the format in which the user data amount is 1024 bytes, the number of bytes in the data field is 1278.
Bytes. In the format in which the amount of user data is 512 bytes, the data field is 670 bytes. In these two sector formats, a 63-byte preformatted header, A
The LPC and the 18 bytes of the gap area are the same.

FIG. 3B shows a 63-byte header in an enlarged manner. The header includes a sector format SM (8 bytes), a VFO field VFO ₁ (26 bytes), an address mark AM (1 byte), and an ID field ID.
₁ (5 bytes), VFO ₂ (16 bytes) in the VFO field, address mark AM (1 byte), ID ₂ (5 bytes) in the ID field, and postamble PA
(1 byte) are arranged in order.

FIG. 3C shows an enlarged 18 byte ALPC and gap area. 18 bytes are a gap field (5 bytes), a flag field (5 bytes),
It consists of a gap field (2 bytes) and ALPC (6 bytes).

Next, these fields will be described. The sector mark SM is a mark for identifying the start of a sector, and has a pattern formed by embossing that does not occur in the RLL (1, 7) code.
The VFO field stores the VFO in the PLL unit 14 described above.
(Variable Frequency Oscilator) and is composed of VFO ₁ , VFO ₂ and VFO ₃ . VFO ₁ and VFO ₂ are formed by embossing. The VFO ₃ is written magneto-optically when a recording operation is performed on the sector. VFO
₁ , VFO ₂ and VFO ₃ each have a pattern (2T pattern) in which channel bits “0” and “1” appear alternately. Therefore, if the time corresponding to the one-bit length time is T, when the VFO field is reproduced,
A reproduction signal whose level is inverted every T is obtained.

[0030] The address mark AM indicates the following ID field.
Used to provide byte synchronization for the device to the device.
Used in RLL (1,7) code
Has a bossed pattern. The ID field is
Data address, ie track number and sector number
No. information and CR for error detection for these information
It has C bytes. The ID field consists of 5 bytes.
You. ID₁And ID _TwoBy the same address information
Is recorded twice. Postamble PA channel
A pattern (2) in which bits “0” and “1” appear alternately
T pattern). ID₁, ID_TwoAnd post-a
The amble PA is also formed by embossing.
In this way, the header area is pitted by embossing.
Is a preformatted area in which is formed.

FIG. 3C shows the ALPC and the gap area in an enlarged manner. No pit is formed in the gap. The first gap field (5 bytes) is the first field after the pre-formatted header, which reserves the time required by the device for processing after reading the header. The second gap field (2 bytes) is for allowing a displacement of VFO ₃ later.

In the ALPC and gap area, a 5-byte flag field is recorded. The flag field indicates a continuous 2T when sector data is recorded.
The pattern has been recorded. ALPC (Auto Laser P
The power control field is provided to test the laser power during recording. The sync field (4 bytes) is provided for the magneto-optical reproducing apparatus to obtain byte synchronization for a subsequent data field, and has a predetermined bit pattern.

In the data field, a precoded recording information unit is recorded. The 670-byte data field described above includes a 512-byte precoded recording information unit, a 144-byte parity for error detection and correction, and a 12-byte sector write flag. In the case of a 1278-byte data field, the data field includes 1024-byte user data, 242-byte parity for error detection and correction, and a 12-byte sector write flag. The buffer field at the end of the sector is used as a tolerance for electrical or mechanical errors.

In the above example of the sector format, the header is an area in which pits are formed by embossing. The ALPC and the gap area are not used during reproduction. Furthermore, VF
O ₃ , the sync field and the data field are areas of magneto-optically recorded data.

[(1.C) Outline of 4-Valued 4-State Viterbi Decoding Method] The outline of the 4-valued 4-state Viterbi decoding method will be described below with reference to FIGS. Hereinafter, the Viterbi decoding means 13
Will be described. As described above, the information unit is converted into a codeword as a recording information unit by various encoding methods. An appropriate encoding method is adopted according to the characteristics of the recording medium and the recording / reproducing method. For example, in a conventional magneto-optical reproducing apparatus, in block encoding, RLL for limiting the Run Length, that is, the number of “0” s between “1” and “1”,
(Run Length Limited) An encoding method is often used. Generally, an m / n block code in which the number of '0's between' 1 'and' 1 'is at least d and at most k is referred to as an RLL (d, k; m, n) code.

For example, in a 2/3 block code,
The number of '0's between 1' and '1' is at least 1 and up to 7
The block encoding method used is RLL (1, 7; 2,
3). Generally, the RLL (1, 7; 2, 3) code is R
Since it is often referred to as an LL (1, 7) code, the RLL (1, 7; 2, 3) code will be simply referred to as an RLL (1, 7) code in the following description. .

A Viterbi decoding method can be used to decode a reproduction signal reproduced from a magneto-optical disk recorded by a combination of the RLL encoding method and the mark edge recording method described above.

By the way, as shown in FIG.
In the combination of the L (1,7) encoding method and the mark edge recording method, at least one '1' is inserted between '1' and '1' in the precode output generated based on the recording information unit.
Since 0 'is included, the minimum inversion width is 2. When such a coding method having a minimum inversion width of 2 is used, as described later, as a method of decoding a recording information unit from a reproduction signal affected by intersymbol interference and noise, as described later, A 4-state Viterbi decoding method can be applied.

As described above, the waveform equalization processing is performed on the reproduced signal by the filter unit 11. Such a waveform equalization process performed as a preceding stage of the Viterbi decoding method includes:
A partial response method that actively uses intersymbol interference is used. The waveform equalization characteristics used at this time are:
From the partial response characteristics generally represented by (1 + D) ⁿ , the linear recording density and MTF of the recording / reproducing system
(Modulation TransferFunction). For a recording information unit recorded by a combination of the RLL (1, 7) encoding method and the mark edge recording method described above, the waveform equalization processing using PR (1, 2, 1) is a 4-level 4-state Viterbi This is the preceding stage of the decoding method.

On the other hand, in the mark edge recording method,
Prior to actual recording on the magneto-optical disk medium, precoding is performed based on the recording information unit encoded by the RLL encoding described above. The recording information unit sequence at each time point k is a (k), and the precode output based on this is b
Assuming that (k), the precode is represented by the following equation (1).

B (k) = mod 2 {a (k) + b (k−1)} (1) Such a precode output b (k) is actually recorded on a magneto-optical disk medium. On the other hand, the waveform equalization characteristic PR (1, 2, 2,
The waveform equalization processing in 1) will be described. However, in the following description, the waveform equalization characteristic is PR (B, 2A, B) without normalizing the signal amplitude. The value of the reproduced signal when noise is not taken into account is denoted by c (k). Further, an actual reproduced signal including noise (that is, a reproduced signal reproduced from a recording medium) is denoted by z (k).

PR (B, 2A, B) is such that the contribution of the amplitude at time k to the value of the reproduced signal at a certain time k is 2A times the amplitude value, and furthermore, at the preceding and following time k-1 and k + 1. The contribution of the amplitude is B times the amplitude of the signal at each point in time. Accordingly, the maximum value of the value of the reproduced signal is a case where a pulse is detected at any of the time points k-1, k, and k + 1. In such a case, the maximum value of the reproduced signal is as follows: B + 2A + B = 2A + 2B.

The minimum value of the value of the reproduced signal is 0.
However, in actual handling, c (k) is D
The following equation (2) obtained by subtracting A + B of the C component is used. c (k) = B × b (k−2) + 2A × b (k−1) + B × b (k) −AB (2) Therefore, the reproduced signal c (k) when noise is not considered.
Takes any value of A + B, A, -A,-(A + B). In general, as one of methods for indicating the properties of a reproduced signal, an eye pattern is obtained by superimposing a large number of reproduced signals in units of, for example, five points.
FIG. 5 shows an example of an eye pattern of an actual reproduced signal z (k) that has been subjected to waveform equalization under PR (B, 2A, B) in the magneto-optical reproducing apparatus. From FIG. 5, it can be confirmed that the value of the reproduced signal z (k) at each point in time has a variation due to noise, but is substantially any one of A + B, A, -A, and -AB. As described later, A +
The values of B, A, -A, and -AB are used as identification points.

The outline of the Viterbi decoder for restoring the reproduced signal subjected to the waveform equalization processing as described above is as follows. All possible states are identified based on the step encoding method and the recording method for the recording medium. Starting from each state at a certain point in time,
All state transitions that can occur at the next point in time, the recording information unit a (k) and the value c (k) of the reproduction signal when each state transition occurs are specified.

All states and state transitions specified as a result of the step and the state, and when each state transition occurs, [value a (k) of recording information unit / value c of reproduced signal]
(K)] is referred to as a state transition diagram. As will be described later, a state transition diagram in the 4-value 4-state Viterbi decoding method is as shown in FIG. The Viterbi decoding means 13 is configured to perform a decoding operation based on this state transition diagram.

Further, as described above, on the premise of the state transition diagram, the reproduced signal z (k) reproduced from the recording medium at each time point k is waveform-equalized in a stage prior to being supplied to the Viterbi decoding means 13. It is a thing. Each time such maximum likelihood state transition is selected, the value of the recording information unit a (k) described in the state transition diagram is set as a decoded value in accordance with the selected state transition. The decoded information unit a ′ (k) can be obtained as the maximum likelihood decoded value sequence for the recording information unit.

The PMU 23a in the Viterbi decoding means 13, which will be described later, has a configuration for obtaining a maximum likelihood decoded value sequence from the value of the decoded information unit at each time point k. Therefore, as described above, the decoding information unit sequence a '(k) matches the recording information unit sequence a (k) when there is no decoding error.
The above steps are described in detail below.

The above steps will be described. First, as a state used here, a state at a certain point in time is defined as follows using a pre-code output before a point in time k. That is, n = b (k) and m = b (k
-1), the state when l = b (k-2) is defined as Snml. With such a definition, it is considered that there are 2 ³ = 8 states, but as described above, the states that actually occur are limited based on the encoding method and the like.

In the recording information unit sequence a (k) encoded as the RLL (1,7) code, at least one '0' is included between '1' and '1', so that two More than'
1 'does not continue. Precode output b based on such conditions imposed on recording information unit sequence a (k)
Certain conditions are fulfilled for (k), placing restrictions on the resulting states.

Such a limitation will be specifically described. As described above, in the recording information unit sequence generated by the RLL (1, 7) encoding, there cannot be one in which two or more '1's are continuous, that is, the following formulas (3) to (5).

A (k) = 1, a (k−1) = 1, a (k−2) = 1 (3) a (k) = 1, a (k−1) = 1, a (k− 2) = 0 (4) a (k) = 0, a (k-1) = 1, a (k-2) = 1 (5) Based on such conditions imposed on the recording information unit sequence,
Examining the conditions imposed on b (k) according to the above equation (1), it can be seen that the two states S010 and S101 cannot occur. Therefore, there are 2 ³ −2 = 6 possible states.

Next, the steps will be described. In order to obtain a state that can occur at the next time point k + 1 from a state at a certain time point k as a starting point, a check is performed separately when the value a (k + 1) of the recording information unit at the time point k + 1 is 1 and 0. There is a need.

Here, the state at the time point k is S000
The following is an example of the case. According to the above equation (1), S000, that is, n = b (k) = 0, l = b (k−
The recording information unit precoded as 1) = 0 and m = b (k−2) = 0 is represented by the following equation (7).

A (k) = 0, a (k−1) = 0, a (k−2) = 0 (7) (when a (k + 1) = “1”) At this time, b (k + 1) is It is calculated as follows according to equation (1).

B (k + 1) = mod2 {a (k + 1) + b (k)} = mod2 {1 + 0} = 1 (8) For the state Snml at the next time point k + 1, n = b
(K + 1), 1 = b (k), and m = b (k-1).
From equation (8), b (k + 1) = 1, and
Since b (k) = 0 and b (k-1) = 0, the next time point k +
The state at 1 is S = 100. Therefore, a (k
In the case of +1) = '1', it can be specified that a transition of S000 → S100 occurs.

The value of the reproduced signal c (k + 1) is calculated as follows in accordance with the above equation (2).

C (k + 1) = {B × b (k + 1) + 2A × b (k) + B × b (k−1)} − AB = {B × 1 + 2A × 0 + B × 0} −AB = − A (9) From the above, when the value of the new reproduction signal value c (k + 1) is −A within the range of the error in the state S000 at the time point k, the state transition S000 → S100 occurs, The value “1” of a (k + 1) as the decoded information unit value
Is obtained.

(When a (k + 1) = '0') At this time, b (k + 1) is calculated by the following equation (1) according to the equation (1).
0).

B (k + 1) = mod2 {a (k + 1) + b (k)} = mod2 {0 + 0} = 0 (10) For the state Snml at the next time point k + 1, n = b
(K + 1), 1 = b (k), and m = b (k-1).
Then, from equation (10), b (k + 1) = 0, b (k) = 0, and b (k-1) = 0, so the state at the next time point k + 1 is S000. Therefore, a
When (k + 1) = '0', it can be specified that a transition from S000 to S000 occurs.

The value of the reproduced signal c (k + 1) is calculated as follows in accordance with the above-mentioned equation (2).

C (k + 1) = {B × b (k + 1) + 2A × b (k) + B × b (k−1)} − AB = {B × 0 + 2A × 0 + B × 0} −AB = − AB (11) From the above, when the value of the new reproduction signal value c (k + 1) is −AB within the range of the error in the case of the state S000 at the time point k, the state transition S000 → S00
0 occurs, and the value of a (k + 1) ′
It can be seen that 0 'is obtained.

In this way, S000 at time k
For each state other than the above, the correspondence between the state transition occurring at the next time point k + 1 starting from them and the recording information unit value a (k + 1) and the reproduction signal value c (k + 1) when such a state transition occurs Can be requested.

As described above, for each state, the correspondence between the state transition that can occur starting from the state, the value of the recording information unit and the value of the reproduction signal at the time when each state transition occurs is determined, and the correspondence is shown in the form of FIG. FIG. 6 shows this. The aforementioned times k and k + 1 are not special times. Accordingly, the correspondence between the possible state transitions obtained as described above and the values of the recording information units and the values of the reproduction signals accompanying the state transitions is as follows:
It can be applied at any time. For this reason,
In FIG. 6, a value of a recording information unit accompanying a state transition occurring at an arbitrary time point k is denoted by a (k), and a value of a reproduced signal is denoted by c (k).

In FIG. 6, the state transition is represented by an arrow. In addition, the sign given to each arrow indicates [record information unit value a (k) / reproduction signal value c (k)]. While there are two types of state transition starting from the states S000, S001, S111, and S110, the state S011
Only one transition can occur starting from S100 and S100.

Further, in FIG. 6, S000 and S001
Takes a value of c (k) =-A for a (k) = 1, and transits to S100. On the other hand, a (k)
= 0, take the value of c (k) =-AB,
The process has transitioned to S000. Similarly, S111 and S110 have the same c (k +) for the same value of a (k + 1).
It takes the value of 1) and transits to the same state. Therefore, S000 and S001 are collectively expressed as S0, and S1
11 and S110 can be collectively expressed as S2. Further, FIG. 7 shows an arrangement in which S011 is expressed as S3 and S100 is expressed as S1.

As described above, FIG. 7 is a state transition diagram used in the 4-value 4-state Viterbi decoding means. FIG.
The four states 0 to S3 and the four values -AB, -A, A, and A + B as the value of the reproduced signal c (k + 1) are shown. While there are two types of state transitions starting from the states S0 and S2, there is only one state transition starting from the states S1 and S3.

On the other hand, a trellis diagram as shown in FIG. 8 is used as a format for expressing a state transition along time. FIG. 8 shows a transition between two time points, but a transition between many more time points can also be shown. As the time elapses, a state in which the image sequentially transits to the right time point is expressed. Therefore, a horizontal arrow represents a transition to the same state, for example, S0 → S0, and a diagonal arrow represents, for example, S1 → S2.
And so on.

The Viterbi decoding step described above, ie,
Based on the state transition diagram shown in FIG. 7, a method of selecting the most likely state transition from the actual reproduced signal z (k) including noise will be described below.

In order to select the maximum likelihood state transition, first, for the state at a certain time point k, the sum of the likelihoods of the state transitions between a plurality of time points passed in the process of reaching the state is calculated. It is necessary to select the maximum likelihood decoded sequence by comparing the calculated sums of likelihoods. Such a sum of likelihoods is called a path metric.

In order to calculate a path metric, it is first necessary to calculate the likelihood of a state transition between adjacent time points. Such calculation of likelihood is performed as follows based on the value of the reproduced signal z (k) with reference to the above-described state transition diagram. First, as a general explanation, the time k-
Consider the case where the state is Sa in state No. 1. At this time, when the reproduced signal z (k) is input to the Viterbi decoding means 13, the likelihood that a state transition to the state Sb occurs is calculated according to the following equation. However, the state Sa and the state Sb
Is any of the four described in the state transition diagram of FIG.

{Z (k) −c (Sa, Sb)} ² (12) In the equation (12), c (Sa, Sb) is a state transition from the state Sa to the state Sb in the state transition of FIG. This is the value of the reproduced signal shown in the figure. That is, in FIG. 7 described above, for example, for the state transition S0 → S1,
A is a value calculated. Therefore, equation (12) becomes
It is the Euclidean distance between the value of the actual reproduced signal z (k) including noise and the value of the reproduced signal c (Sa, Sb) calculated without considering noise. The path metric at a certain point in time is defined as the sum of likelihoods of state transition between such adjacent points up to that point.

Now, consider the case where the state is Sa at the time point k. In this case, assuming that the state that can transition to the state Sa at the time point k-1 is Sp, the path metric L (Sa, k) is calculated as follows using the path metric at the time point k-1. .

L (Sa, k) = L (Sp, k−1) + {z (k) −c (Sa, Sp)} ² (13) That is, when the state Sp is reached at the time point k−1 The path metric L (Sp, k-1) and the likelihood 状態 z of the state transition of Sp → Sa occurring between time k-1 and time k
By adding (k) −c (Sa, Sb) 加 算² , the path metric L (Sa, k) is calculated. The likelihood of the latest state transition, such as {z (k) -c (Sa, Sb)} ² , is called a branch metric. However, the branch metric here is a branch metric calculation circuit in the Viterbi decoding means 13 described later, BMC2
It should be noted that the branch metric calculated by Oa, ie, the branch metric corresponding to the normalized metric, is different.

When the state is the state Sa at the time point k, there may be a plurality of states that can transition to the state Sa at the time point k-1. In FIG. 7, states S0 and S2 are such cases. That is, if the state S0 is at time k, the state S
There are two states that can transition to 0: S0 and S3. Further, when the state is the state S2 at the time point k, the states that can transition to the state S2 at the time point k-1 are two states S1 and S2. As a general explanation, at time k, state Sa
, And when there are two states that can transition to the state Sa at the time point k−1, Sp and Sq, the path metric L (Sa, k) is calculated as in the following equation.

L (Sa, k) = min [(L (Sp, k−1) + {z (k) −c (Sa, Sb)} ² , L (Sq, k−1) + Δz (k ) −c (Sa, Sb)｝ ² ] (14) That is, at time k−1, the state is Sp, and Sp →
The sum of the likelihoods is calculated for each of the case where the state Sa is reached by the state transition Sa and the case where the state Sq is reached at the time k-1 and the state Sq is reached by the state transition Sq → Sa. Then, the respective calculated values are compared, and the smaller value is set as the path metric L (Sa, k) for the state Sa at the time point k.

The calculation of such a path metric is shown in FIG.
Is specifically applied to the above-described quaternary and four states by using, the respective states S0, S1, S2 and S3 at the time point k.
, L (0, k), L (1,
k), L (2, k), and L (3, k) are the time points k-
1 can be calculated as follows using the path metrics L (0, k-1) to L (3, k-1) for each of the states S0 to S3.

L (0, k) = min [L (0, k−1) + {z (k) + A + B} ² , L (3, k−1) + {z (k) + A} ² ] (15 ) L (1, k) = L (0, k-1) + {z (k) + A} ² (16) L (2, k) = min [L (2, k-1) + ｛z (k ) -AB｝ ² , L (1, k−1) + ｛z (k) −A｝ ² ] (17) L (3, k) = L (2, k−1) + ｛z (k ) −A｝ ² (18) As described above, the value of the path metric calculated in this way is compared, and the maximum likelihood state transition may be selected. By the way, in order to select the maximum likelihood state transition, it suffices if the value of the path metric can be compared without calculating the value of the path metric itself. Therefore, in the actual 4-valued 4-state Viterbi decoding, the calculation based on z (k) at each time point k is facilitated by using a normalized path metric defined below instead of the path metric. It is done as follows.

M (i, k) = {L (i, k) −z (k) ² − (A + B) ² } / 2 × (A + B) (19) Equation (19) is applied to each of the states S0 to S3. When applied, specific normalized path metrics are given by the following equations (20) to (23).
Does not include the square calculation. Therefore, the addition, comparison, and calculation in the selection circuit ACS21a, which will be described later, can be simplified.

M (0, k) = min {m (0, k−1) + z (k), m (3, k−1) + α × z (k) −β} (20) m (1, k ) = M (0, k−1) + α × z (k) −β (21) m (2, k) = min ｛m (2, k−1) −z (k), m (1, k−) 1) −α × z (k) −β｝ (22) m (3, k) = m (2, k−1) −α × z (k) −β (23) However, Expressions (20) to (20) Α and β in 23) are as in the following formulas (24) and (25).

Α = A / (A + B) (24) β = B × (B + 2 × A) / 2 × (A + B) (25) State transition in the 4-value 4-state Viterbi decoding method based on such a normalized path metric FIG. 9 shows the condition (1). Since there are two expressions for selecting one from two of the above four normalized path metrics, there are 2 × 2 = 4 conditions.

[(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means] Hereinafter, an outline of the configuration and operation of the 4-valued 4-state Viterbi decoding means will be described with reference to FIGS. I do. The Viterbi decoding means 13 for implementing the above-described four-value four-state Viterbi decoding will be described below.
FIG. 10 shows an overall configuration diagram of the Viterbi decoding means 13. The Viterbi decoding means 13 includes a branch metric calculation circuit (hereinafter, referred to as BMC) 20a, an addition, comparison and selection circuit (hereinafter, referred to as ACS) 21a, a compression and latch circuit 22, and a path memory unit (hereinafter, PMU).
23a). By supplying the above-described read clock DCK (hereinafter simply referred to as a clock) to these components, the operation timing of the entire Viterbi decoding unit 13 is adjusted. Hereinafter, each component will be described.

The BMC 20a receives the reproduced signal z
Based on (k), the values BM0, BM1, BM2, and BM3 of the branch metrics corresponding to the normalized path metrics are calculated. BM0 to BM3 are calculated by the above equation (2)
The following are required to calculate the normalized path metrics of (0) to (23).

BM0 = z (k) (26) BM1 = α × z (k) −β (27) BM2 = −z (k) (28) BM3 = −α × z (k) −β (29) Α and β required for the calculation are reference values calculated by the BMC 20a according to the above-described equations (24) and (25). Such a calculation is detected by a method such as envelope detection based on the reproduced signal z (k), for example.
0a supplied to the identification points -AB, -A, A and A +
This is performed based on the value of B.

The values of BM0 to BM3 are supplied to the ACS 21a. On the other hand, the ACS 21a is supplied with normalized path metric values M0, M1, M2, and M3 one clock before (but compressed as described later) from the compression and latch means 22 described later. . Then, M0 to M3 and BM0 to BM3 are added, and the latest standardized path metric value L is added as described later.
Calculate 0, L1, L2 and L3. Since M0 to M3 are compressed, it is possible to avoid overflow when calculating L0 to L3.

Further, the ACS 21a selects a maximum likelihood state transition based on the latest standardized path metric values L0 to L3, as described later, and supplies it to the path memory PMU 23a in accordance with the selection result. Selection signal SE
L0 and SEL2 are set to 'High' or 'Low'.

The ACS 21a supplies L0 to L3 to the compression and latch means 22. The compression and latch means 22 latches the supplied L0 to L3 after compressing them. Then, the normalized path metric M one clock before
The data is supplied to the ACS 21a as 0 to M3.

As a compression method at this time, for example, a method of uniformly subtracting one of them, for example, L0 from the latest standardized path metrics L0 to L3 as shown below is used.

M0 = L0−L0 (30) M1 = L1−L0 (31) M2 = L2−L0 (32) M3 = L3−L0 (33) As a result, M0 always takes a value of 0. However, in the following invention, in order not to impair generality,
This is denoted as M0 as it is. The difference between the values of M0 to M3 calculated by the equations (30) to (33) is equal to the difference between the values of L0 to L3. As described above, in the selection of the most likely state transition, only the difference between the values of the normalized path metrics becomes a problem. Therefore, such a compression method is effective as a method of compressing the value between the normalized path metrics without affecting the selection result of the maximum likelihood state transition and preventing overflow. As described above, the ACS 21a and the compression and latch unit 22 form a loop related to the calculation of the normalized path metric.

The above-mentioned ACS 21a will be described in more detail with reference to FIG. The ACS 21a includes six adders 51, 52, 53, 54, 56, 58 and two comparators 55, 57. On the other hand, as described above, the compressed standardized path metric values M0 to M3 one clock before and the branch metric values BM0 to BM3 corresponding to the standardized path metric are supplied to the ACS 21a.

M0 and BM0 are supplied to the adder 51. The adder 51 adds these to calculate L00 as follows.

L00 = M0 + BM0 (34) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above-described equation (26) based on the reproduced signal z (k) input at the time point k, that is, the value of z (k) itself. Therefore, the value of equation (34) is calculated by the above-mentioned equation (2) under the action of compression as described above.
The value of m (0, k-1) + z (k) in (0) is calculated. In other words, the calculated value corresponds to the state S0 at the time point k−1 and the state transition S0 → S0 at the time point k, which finally leads to the state transition S0.

On the other hand, M3 and BM1 are added to the adder 52.
Is supplied. The adder 51 adds these to calculate the following L30.

L30 = M3 + BM1 (35) As described above, M3 is in the state S3 at the time point k-1.
, Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, B
M1 is calculated based on the reproduced signal z (k) input at the time point k in accordance with the above-described equation (27), that is, α × z (k) −β. Therefore, the value of equation (35) is calculated by the above-described equation (2) under the action of compression as described above.
0), the value of m (3, k−1) + α × z (k−1) −β is calculated. That is, this is a calculated value corresponding to the case where the state is S3 at the time point k−1 and finally reaches the state transition S0 by the state transition S3 → S0 at the time point k.

The aforementioned L00 and L30 are provided by the comparator 55
Supplied to The comparator 55 compares the values of L00 and L30, and determines the smaller one as the latest standardized path metric L0.
In addition, the polarity of the selection signal SEL0 is switched according to the selection result as described above. Such a configuration,
In equation (20), this corresponds to the selection of the minimum value. That is, when L00 <L30 (in this case, S0 → S0 is selected), L00 is output as L0, and SEL0 is set to, for example, 'Low'. If L30 <L00 (in this case, S3 → S0 is selected), L30 is output as L0, and SE is output.
L0 is set to, for example, 'High'. SEL0 is supplied to the A-type path memory 24 corresponding to the state S0, as described later.

Thus, the adders 51 and 52 and the comparator 55 are the most likely state transitions at the time point k from S0 → S0 and S3 → S0, corresponding to the above-mentioned equation (20). Is performed. Then, it outputs the latest standardized path metric L0 and the selection signal SEL0 according to the selection result.

The adder 56 has M0 and BM1
Is supplied. The adder 56 adds these to calculate the following L1.

L1 = M0 + BM1 (36) As described above, M0 is in the state S0 at the time point k−1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
1 is a value calculated according to the above-described equation (27) based on the reproduced signal z (k) input at the time point k, that is, α × z (k) −β. Therefore, the value of (36) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side of (1) (0, k-1) + α × z (k) −β is calculated.

That is, this is a calculated value corresponding to the case where the state S0 is at time k−1 and the state transition S1 is finally reached by the state transition S0 → S1 at time k. In response to equation (21) not selecting a value,
The output of the adder 56 is used as it is as the latest standardized path metric L1.

The adder 53 is supplied with M2 and BM2. The adder 53 adds these to calculate the following L22.

L22 = M2 + BM2 (37) As described above, M2 is in the state S2 at the time point k−1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above-described equation (28) based on the reproduced signal z (k) input at the time point k, that is, -z (k). Therefore, the value of the expression (37) is obtained by calculating the value of m (2, k-1) -z (k) in the above expression (22) under the effect of the above-described compression. . That is, the calculated value corresponds to the case where the state S2 is at the time point k−1 and the state transition S2 is finally reached by the state transition S2 → S2 at the time point k.

On the other hand, the adder 54 has M1 and BM3
Is supplied. The adder 54 adds these to calculate L12 as follows.

L12 = M1 + BM3 (38) As described above, M1 is in the state S1 at the time point k−1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z (k) input at the time point k, that is, -α × z (k) -β. Therefore, the value of equation (38) is calculated by the above equation (2) under the action of compression as described above.
The value of m (1, k-1) -α × z (k) -β in 2) is calculated. That is, the calculated value corresponds to the case where the state S1 is at time k−1 and the state transition S2 is finally reached at time k by the state transition S1 → S2.

The aforementioned L22 and L12 are connected to the comparator 57
Supplied to The comparator 57 compares the values of L22 and L12, and determines the smaller one as the latest standardized path metric L2.
Then, the polarity of the selection signal SEL2 is switched according to the selection result as described above. Such a configuration,
In equation (22), this corresponds to the selection of the minimum value.

That is, when L22 <L12 (in this case, S2 → S2 is selected), L22 is output as L2, and SEL2 is set to, for example, 'Low'. Also,
If L12 <L22 (in this case, S1 → S2 is selected), L12 is output as L2, and SEL is output.
2 is, for example, 'High'. SEL2 is supplied to the A-type path memory 26 corresponding to the state S2 as described later.

As described above, the adders 53 and 54 and the comparator 57 correspond to the above-mentioned equation (22) and calculate the maximum likelihood state transition at the time point k from S1 → S2 and S2 → S2. Select Then, it outputs the latest standardized path metric L2 and the selection signal SEL2 according to the selection result.

The adder 58 has M2 and BM3
Is supplied. The adder 58 adds these to calculate the following L3.

L3 = M2 + BM3 (39) As described above, M2 is in the state S2 at the time point k−1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z (k) input at the time point k, that is, -α × z (k) -β. Therefore, the value of equation (39) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (2, k−1) −α × z (k) −β of 3) is calculated. That is, the calculated value corresponds to the case where the state S0 is at the time point k−1 and the state transition S3 is finally reached by the state transition S2 → S3 at the time point k. In response to the expression (23) not selecting a value, the output of the adder 58 is used as it is as the latest standardized path metric L3.

As described above, the path memory unit P according to SEL0 and SEL2 output from the ACS 21a
When the MU 23a operates, the recording information unit a
A decoded information unit a ′ (k) as the maximum likelihood decoded sequence corresponding to (k) is generated. The PMU 23a has two As to deal with the state transition between the four states shown in FIG.
It consists of a type path memory and two B type path memories.

The A-type path memory has two transitions to the state (ie, a transition from itself and a transition from another one), and two transitions starting from the state. It is configured to correspond to a state having a transition (ie, a transition leading to itself and a transition leading to another state). Accordingly, the A-type path memory has the structure shown in FIG.
These correspond to S0 and S2 among the individual states.

On the other hand, the B-type path memory is configured to cope with a state in which there is only one transition to the state and only one transition starting from the state. Therefore, the B-type path memory corresponds to S1 and S3 among the four states shown in FIG.

In order for these two A-type path memories and two B-type path memories to operate in accordance with the state transition diagram shown in FIG. 7, the PMU 23a must transfer the decoded information unit as shown in FIG. It is configured to be made. That is, the A-type path memory 24 corresponds to S0,
The mold path memory 26 corresponds to S2. The B-type path memory 25a corresponds to S1, and the B-type path memory 27a
Corresponds to S3.

With this structure, the state transitions that can occur starting from S0 are S0 → S0 and S0 → S1, and the state transitions occurring starting from S2 are S2 → S2 and S3 → S3. . Also, the only state transition that can occur starting from S1 is S1 → S2, and S3
Also coincides with the fact that the state transition that can occur starting from is only S3 → S0.

FIG. 12 shows a detailed configuration of the A-type path memory 24. The A-type path memory 24 includes a number of flip-flops and selectors corresponding to the path memory length,
They are connected alternately. FIG. 12 shows a configuration corresponding to a decoded data length of 14 bits. That is,
Those having fourteen selectors 31 ₁ to 31 ₁₄ and 15 flip-flops 30 ₀ - 30 _14. Each of the selectors 31 _{1 to} 31 ₁₄ receives two pieces of data and selectively supplies one of the pieces of data to a subsequent stage. Further, since the clock is supplied to the flip-flop 30 ₀ - 30 _14, the operation timing of the entire A type path memory 24 is combined.

As described above with reference to FIG. 7, the transition to the state S0 is S0 → S0, that is, the transition inherited from itself, and S3 → S0. As a configuration corresponding to such a situation, each selector includes a data supplied from the preceding flip-flop, that is, a decoded information unit corresponding to S0 → S0, and a B-type path memory 27 corresponding to state S3.
a, ie, the decoded information unit PM3 corresponding to S3 → S0.

Furthermore, each selector is supplied with SEL0 from the ACS 21a. Then, according to the polarity of SEL0, one of the two supplied decoded information units is supplied to the subsequent flip-flop. Also, like this
The decoding information unit supplied to the subsequent flip-flop is:
It is also supplied as PM0 to the B-type path memory 25a corresponding to the state S1.

[0116] That is, for example, the selector 31 _14, the data supplied from the preceding flip-flops 30 _13, B
And 14-bit data of the 14th bit position of PM3 supplied from the mold path memory 27a.
Then, the data selected as follows from these two data, and supplies the subsequent flip-flop 30 _14. As described above, SEL0 is set to 'Low' or 'High' according to the selection result.

[0117] When SEL0 is for example 'Low' is as data from the preceding flip-flop 30 ₁₃ is selected. When SEL0 is “High”, for example, PM
The data at the position of the 14th bit of No. 3 is selected. The selected data is supplied to the subsequent flip-flops 30 _14, and as data 14 th bit position of PM0, is supplied to the B type path memory 25a corresponding to the state S1.

Another selector 31 in the A-type path memory 24
Also in _{1-31 13,} depending on the polarity of the SEL, similar operations are performed. Therefore, as a whole, when SEL0 is, for example, “Low”, the A-type path memory 24 performs serial shift in the A-type path memory 24 in which each flip-flop inherits the data of the flip-flop located at the preceding stage. Do. When SEL0 is, for example, "High", parallel loading is performed to inherit the 14-bit decoded information unit PM3 supplied from the B-type path memory 27a. In any case, the inherited decryption information unit is B
14-bit decoded information unit PM0 is stored in the type path memory 25a.
Supplied as

[0119] In addition, the flip-flop 30 ₀ on the first stage, in synchronization with the clock, always '0' is input. Such an operation is a state transition S0 → S0 leading to S0.
7 and S3 → S0, the decoding information unit is “0” as shown in FIG. 7, so that the latest decoding information unit is always “0”.

As described above, the configuration of the A-type path memory 26 corresponding to S2 is the same as that of the A-type path memory 2.
4 is exactly the same. However, the selection signal input from the ACS 21a is SEL2. In addition, as shown in FIG. 7, transitions to the state S2 include S2 → S2, that is, transitions inherited from itself, and S1 → S2. Therefore, the PM data is stored in the B-type path memory 25a corresponding to the state S1.
1 is supplied. Further, since the state that can occur starting from the state S2 is S2, ie, itself, and S3, the P-type path memory 27a corresponding to the state S3 stores the P
Supply M2.

The A-type path memory 26 corresponding to S2
In this case, "0" is always input to the flip-flop serving as the first processing stage in synchronization with the clock. Such an operation is a state transition S2 → S2 and S1 → S2 leading to S2.
In any case, as shown in FIG. 7, since the decoded information unit is '0', the latest decoded information unit always corresponds to '0'.

On the other hand, FIG. 13 shows a detailed configuration of the B-type path memory 25a. B-type path memory 25a
Are connected to the number of flip-flops corresponding to the path memory length. FIG. 13 shows a configuration corresponding to a decoded data length of 14 bits. That is, it has 15 flip-flops 32 _{0 to} 32 ₁₄ . By supplying a clock to the flip-flops 32 _{0 to} 32 ₁₄ , the operation timing of the entire B-type path memory 25 a is adjusted.

Each of the flip-flops 32 _{1 to} 32 ₁₄ has
It is supplied as a 14-bit decoded information unit PM0 from the A-type path memory 2 corresponding to the state S0. For example, the first bit of PM0 is supplied to the flip-flop 32 ₁ . Each of the flip-flops 32 _{1 to} 32 ₁₄ holds the supplied value for one clock. Then, it outputs the 14-bit decoded information unit PM1 to the A-type path memory 26 corresponding to the state S2. For example, the flip-flop 32 ₁ outputs the second bit of PM1.

A similar operation is performed in the other flip-flops 32 _{1 to} 32 ₁₃ in the B-type path memory 25a. Accordingly, the entire B-type path memory 25a receives the 14-bit decoded information unit PM0 supplied from the A-type path memory 24, and supplies the A-type path memory 26 with the 14-bit decoded information unit PM1.

[0125] In addition, the flip-flop 32 _0, always in synchronization with the clock, '1' is input. In this operation, as shown in FIG. 7, the latest state transition is S0 → S1.
The case corresponds to that the decoding information unit is “1”.

As described above, the B-type path memory 27a corresponding to the state S3 also has the B-type path memory 25a.
The configuration is exactly the same as a. However, as shown in FIG. 7, since the transition to the state S3 is from S2 to S3, PM2 is supplied from the A-type path memory 26 corresponding to the state S2.
Further, in response to the state that can occur starting from the state S3 being S0, PM3 is supplied to the A-type path memory 24 corresponding to the state S0. Also in the B-type path memory 27a, "1" is always input to the flip-flop which is the first processing stage. This operation corresponds to the fact that the decoding information unit is “1” when the latest state transition is S2 → S3, as shown in FIG.

As described above, each of the four path memories in the PMU 23a generates a decoded information unit sequence in DEC_OUT. The four decoded information unit strings generated in this way will coincide with each other if an accurate Viterbi decoding operation is always performed. By the way, in an actual Viterbi decoding operation, a mismatch may occur between the four decoded information unit strings. Such inconsistency is caused by improper Viterbi decoding operation due to factors such as an error in detecting the above-described identification point due to the influence of noise included in the reproduction signal.

In general, the probability of occurrence of such inconsistency can be reduced by setting the number of stages of the path memory sufficiently large in accordance with the quality of the reproduced signal. That is, when the quality of the reproduction signal such as C / N is good, the probability of occurrence of mismatch between the decoded information unit columns is small even if the number of processing stages of the path memory is relatively small. On the other hand, when the quality of the reproduced signal is not good, it is necessary to increase the number of processing stages of the path memory in order to reduce the probability of occurrence of the above-described mismatch.

If the number of processing stages of the path memory is relatively small with respect to the quality of the reproduced signal and the probability of occurrence of a mismatch between the decoded information unit columns cannot be reduced sufficiently, for example, a majority decision is performed from the four decoded information unit columns. A configuration (not shown) for selecting a more appropriate one by the method such as
a is provided at the subsequent stage.

As to an example of a magneto-optical reproducing apparatus having a reproducing system for performing the above-mentioned Viterbi decoding method, an outline of the magneto-optical reproducing apparatus, an outline of the sector format of the recording medium, and an outline of the 4-value 4-state Viterbi decoding method, 4-state 4-state The outline of the configuration and operation of the 4-level 4-state Viterbi decoding means for realizing the Viterbi decoding method has been described.

Second, a block code using the same PR (1,2,1) partial response waveform equalization characteristic and the same sector format of a recording medium as described above and removing the above-mentioned restriction of the minimum value 1 is used. (2.A) The outline of the 5-value 4-state Viterbi decoding method and the outline of the configuration and operation of the 5-value 4-state Viterbi decoding means when used are described below. .
B) An embodiment of the information reproducing apparatus of the present invention will be described.

[(2.A) Outline of 5-Valued 4-State Viterbi Decoding Method] An outline of a 5-valued 4-state Viterbi decoding method will be described below with reference to FIG. As described in [(1.C) Overview of 4-value 4-state Viterbi decoding method], the RLL
In the case of the (1, 7) code, the number of '0's between' 1 'and' 1 'is restricted to at least one. That is, RLL (1,
7) In the recording information unit sequence channel-encoded by the code, as shown in the above equations (3) to (5),
｛A (k) = 1, a (k−1) = 1, a (k−2) =
1}, ｛a (k) = 1, a (k−1) = 1, a (k−
2) = 0, {a (k) = 0, a (k-1) = 1, a
There could not be a series where (k−2) = 1｝. However, if the constraint of the minimum value of the number of '0's is removed, a block code having higher coding efficiency can be selected.

The sequence of recording information units a (k) channel-encoded by the block code selected in this manner is a sequence of recording information unit sequences channel-encoded by the RLL (1,7) code. In addition, a sequence represented by the above-described equations (3) to (5) occurs. At this time, the state transition is a quinary 4 state, which will be described next.

The states S010 and S101 did not occur in the output b (k) which was channel-coded by the RLL (1,7) code and pre-coded by the equation (1). So, when we look at what happens,

"# 1" state S100, that is, $ b (k)
= 1, b (k-1) = 0, b (k-2) = 0}, {a (k + 1) = 1, a (k) = 1, a (k-1)
= 0}, a formula (1) expresses {b (k + 1) = 0, b (k) = 1, b (k-
Since 1) = 0, it is understood that a state transition from S100 to S010 occurs.

"# 2" state S011, that is, $ b (k)
= 1, b (k-1) = 1, b (k-2) = 0}, {a (k + 1) = 1, a (k) = 1, a (k-1)
When a recording information unit sequence of {= 0} occurs, {b (k + 1) = 1, b (k) = 0, b (k−
1) = 1}, it can be seen that a state transition from S011 to S101 occurs.

Next, the relationship between the state S101 and the state S100 generated by the above-mentioned item "# 2" will be examined.

In the "# 3" state S100, ｛a (k
+1) = 0, a (k) = 1, a (k-1) = 0} is generated, then {b
Since (k + 1) = 1, b (k) = 1, b (k-1) = 0, it is understood that a state transition from S100 to S110 occurs.

"# 4" Also, when in the state S101,
｛A (k + 1) = 0, a (k) = 1, a (k−1) =
When the recording information unit sequence of {1} is generated, {b (k + 1) = 1, b (k) = 1, b (k−1) by equation (1).
= 0}, it is understood that a state transition from S101 to S110 occurs.

"# 5" Furthermore, when in the state S101,
｛A (k + 1) = 1, a (k) = 1, a (k−1) =
When a recording information unit sequence of {1} is generated, {b (k + 1) = 0, b (k) = 1, b (k−1) by equation (1).
= 0}, it is understood that a state transition from S101 to S010 occurs.

"# 6" When the results of the preceding paragraphs "# 1" to "# 5" are combined, the state S101 can be obtained even in the state S100.
When a (k + 1) = 0, the state transits to the state S110, and when a (k + 1) = 1, the state transits to the state S010. Therefore, the state S101 and the state S100 can be considered as one state collectively. Since the state S100 is the state S1 as described in [(1.C) 4-value 4-state Viterbi decoding method overview], the state S101 and the state S101 are different.
100 will be collectively referred to as state S1.

"# 7" When examining the relationship between the state S010 and the state S011 generated by the preceding section "# 1", a (k + 1) = When 1, the state S
101, and when a (k + 1) = 0, state S0
It can be seen that the transition to 01 is made. Therefore, the state S010 and the state S011 can be considered as one state collectively. Since the state S011 is the state S3 as described in [(1.C) 4-value 4-state Viterbi decoding method overview], the state S010 and the state S011 are collectively referred to as state S3.

"# 8" The state transition between state S1 (including state S101 and state S100) and state S3 (including state S010 and state S011) is paraphrased as follows according to the preceding paragraphs "# 6" and "# 7". be able to. That is, in the state S1, if a (k + 1) = 1, the state transits to the state S3. If a (k + 1) = 0, the state S110, that is, [(1.C) 4-value 4-state Viterbi decoding method is used. To S2 as described above. When a (k + 1) = 1 in the state S3, the state transits to the state S1 and a
If (k + 1) = 0, the state transits to the state S0 as described above in [(1.C) Four-level four-state Viterbi decoding method overview].

The state S1 and the state S3 in the previous section "# 8"
Are generated by the transition between the state S101 and the state S010. At this time, the reproduced signal c (k +
When the value of 1) is calculated according to equation (2), the state S1
→ In the transition of the state S3, c (k + 1) = {B × b (k + 1) + 2 × A × b (k) + B × b (k−1)} − AB = {B × 0 + 2 × A × 1 + B × 0｝ −AB = AB (40) Similarly, in the transition from the state S3 to the state S1, c (k + 1) = {B × 1 + 2 × A × 0 + B × 1} −AB = BA (41) If A = B is selected in Expressions (40) and (41) (usually selected in this way), the value of c (k + 1) is 0. Hereinafter, it is assumed that A = B unless otherwise specified.

As described above, the information unit is “1”.
Is channel-encoded by a block code excluding the constraint of the minimum value of “0” between “1” and “1”, is pre-coded according to equation (1), and has a PR (1, 2, 1) partial response waveform, etc. If the conversion is performed, there is the following state transition difference as compared with the similar case of the information unit channel-coded by the RLL (1, 7) code.

That is, the state transition diagram in the case where the information unit is channel-encoded by a block code in which the restriction of the minimum value of the number of '0's between' 1 'and' 1 'has been removed is shown in FIG.
In the state transition diagram of the 4-level 4-state Viterbi decoding of FIG. 7 when the channel is coded by the L (1,7) code,
State S1 → state S3 and state S3 → state S1 are added, and state S1 → state S3 is also changed to state S3 →
The state S1 is also generated when a (k + 1) = 1, and the reproduced signal c (k + 1) at that time is 0 in any state transition. Accordingly, a state transition diagram of five values and four states is obtained as shown in FIG.

Next, the normalized path metric m (i, i,
When k) is calculated according to equations (20) to (23) in four values and four states, the following equations (42) to (45) are obtained. m (0, k) = min {m (0, k-1) + z (k), m (3, k-1) + α × z (k) -β} (42) m (1, k) = min {M (0, k-1) + α × z (k) −β, m (3, k−1) − (4/3) × β} (43) m (2, k) = min ｛m (2 , K−1) −z (k), m (1, k−1) −α × z (k) −β｝ (44) m (3, k) = min ｛m (2, k−1) − α × z (k) −β, m (1, k−1) − (4/3) × β｝ (45) where α and β are the same as in the case of the four-valued four-state, and the equations (24) and (25) ), A = B. The condition diagram of the state transition in the 4-value 4-state Viterbi decoding based on the normalized path metric as shown in FIG.
Although it can be created also in the case of the above-described quinary 4 state, in this case, as can be seen from the equations (42) to (45), 4 × 4 = 1
There are six conditions. The condition diagram of the state transition of the quinary four-state Viterbi decoding method is omitted because it can be easily analogized from FIG.

[(2.B) Outline of Configuration and Operation of 5-Valued 4-State Viterbi Decoding Means] Hereinafter, an outline of the configuration and operation of the 5-valued 4-state Viterbi decoding means will be described with reference to FIGS. . In the quinary 4-state Viterbi decoding method, the branch metric and BM0 described in [(1.D) Outline of Configuration and Operation of 4-State 4-State Viterbi Decoding Unit] are used.
The following branch metrics BM0 to BM4 are defined according to the equations (26) to (29) relating to .about.BM3. BM0 = z (k) (46) BM1 = α × z (k) −β (47) BM2 = −z (k) (48) BM3 = −α × z (k) −β (50) BM4 = − ( 4/3) × β (51)

The values of BM0 to BM4 are supplied to the ACS,
From the compression and latch circuit, the values of the normalized path metric one clock before (but compressed as described later) M0, M1, M2 and M3 are supplied.
The procedure of calculating the latest normalized path metric values L0, L1, L2 and L3 by adding M3 and BM0 to BM3 is as follows: [(1.D) Configuration and operation of 4-value 4-state Viterbi decoding means Overview] is the same as the procedure described above.

As a compression method at this time, for example, as shown below, the latest standardized path metrics L0 to L
3, the method of uniformly subtracting one of them, for example, L0, is also the same as described in [(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means]. . That is, M0 = L0-L0 (52) M1 = L1-L0 (53) M2 = L2-L0 (54) M3 = L3-L0 (55)

Next, differences between the configuration and operation of the ACS between the 5-valued 4-state Viterbi decoding and the 4-valued 4-state Viterbi decoding will be described. Compared to the ACS 21b used for 4-level 4-state Viterbi decoding shown in FIG. 11 with the ACS 21a used for 4-level 4-state Viterbi decoding shown in FIG. The units 61 and 62 are newly added, and the compressed standardized path metric values M0 to M3 one clock before remain unchanged, and the branch metric value BM4 corresponding to the standardized path metric is newly supplied. I have. Therefore, if these newly added ones are explained, the difference between the configuration and operation of the ACS between the 5-valued 4-state Viterbi decoding and the 4-valued 4-state Viterbi decoding becomes clear.

The adder 59 is supplied with M3 and BM4. The adder 59 adds these and calculates the following equation (5)
L31 as in 6) is calculated.

L31 = M3 + BM4 (56) When M3 reaches the state S3 at the time point k−1,
This is a compressed normalized path metric corresponding to the sum of state transitions that have passed through. Further, the BM 4 determines the aforementioned (5) based on the reproduction signal z (k) input at the time point k.
1) The one calculated according to the equation, that is, − (4 /
3) xβ. Therefore, the value of the equation (56) is calculated by using the value of m in the above-mentioned equation (43) under the effect of the above-described compression.
(3, k−1) − (4/3) × β. That is, at time k−1, the state is S3,
This is a calculated value corresponding to the case where the state transition S1 finally arrives at the time point k by the state transition S3 → S1.

On the other hand, from the adder 56, as described in [(1.D) 4-value 4-state Viterbi decoder, outline of configuration and operation], state S0 at time k-1 and state S at time k The calculated value corresponding to the case where the state transition S1 is finally reached by the transition S0 → S1 is L01 = M0 +
BM1 is obtained. This value is m (0,
k-1) + α × z (k) −β.

The aforementioned L01 and L31 are the comparator 61
Supplied to The comparator 61 compares the values of L01 and L31, and determines the smaller one as the latest standardized path metric L1.
In addition, the polarity of the selection signal SEL1 is switched according to the selection result as described above. Such a configuration,
In equation (43), this corresponds to the selection of the minimum value.

That is, when L31 <L01 (at this time, S3 → S1 is selected), L31 is output as L1 and SEL1 is set to, for example, “Low”. Also,
If L01 <L31 (in this case, S0 → S1 is selected), L01 is output as L1, and SEL is output.
1 is set to, for example, 'High'. SEL1 is supplied to the C-type path memory 25b corresponding to the state S1, as described later.

As described above, the adders 56 and 59 and the comparator 61 are the most likely state transitions at the time point k from S3.fwdarw.S1 and S0.fwdarw.S1 according to the above equation (43). Select Then, it outputs the latest standardized path metric L1 and the selection signal SEL1 according to the selection result.

Next, the adder 60 has M1 and BM4
Is supplied. The adder 60 adds these to calculate L13 as follows.

L13 = M1 + BM4 (57) When M1 reaches the state S1 at the time point k−1,
This is a compressed normalized path metric corresponding to the sum of state transitions that have passed through. Further, the BM 4 determines the aforementioned (5) based on the reproduction signal z (k) input at the time point k.
1) The one calculated according to the equation, that is, − (4 /
3) xβ. Therefore, the value of the equation (57) is calculated by using the value of m in the above-mentioned equation (45) under the action of the compression as described above.
(1, k−1) − (4/3) × β. That is, at time k−1, the state is S1;
This is a calculated value corresponding to a case where the state transition S3 finally arrives at the time point k by the state transition S1 → S3.

On the other hand, the adder 58 outputs the state S2 at the time point k-1 and the state S2 at the time point k, as described above in [(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means]. The calculated value corresponding to the case where the state transition S3 is finally reached by the transition S2 → S3 is L23 = M2 +
BM3 is obtained. This value is m (2,2) in the equation (45).
k−1) −α × z (k) −β.

The aforementioned L13 and L23 are provided by the comparator 62
Supplied to The comparator 62 compares the values of L13 and L23, and determines the smaller one as the latest standardized path metric L3.
Then, the polarity of the selection signal SEL3 is switched according to the selection result as described above. Such a configuration,
In equation (45), this corresponds to the selection of the minimum value.

That is, when L13 <L23 (in this case, S1 → S3 is selected), L13 is output as L3, and SEL3 is set to, for example, 'Low'. Also,
When L23 <L13 (in this case, S2 → S3 is selected), L23 is output as L3, and SEL is output.
3 is, for example, 'High'. SEL3 is supplied to the C-type path memory 27b corresponding to the state S3, as described later.

As described above, the adders 58 and 60 and the comparator 62 are the most likely state transitions at the time point k from S1.fwdarw.S3 and S2.fwdarw.S3 in accordance with the equation (45). Select Then, it outputs the latest standardized path metric L3 and the selection signal SEL3 according to the selection result.

Next, differences between the configuration and operation of the path memory unit and the PMU between the 5-valued 4-state Viterbi decoding and the 4-valued 4-state Viterbi decoding will be described. When comparing the PMU 23b used for the quinary 4-state Viterbi decoding shown in FIG. 15 with the PMU 23a used for the quaternary 4-state Viterbi decoding shown in FIG. 10, the C-type path memories 25b and C shown in bold frames in FIG. The B-type path memory 25a and the B-type path memory 27a shown in FIG. 10 are replaced by the type-path memory 27b, and SEL1 and SEL3 shown by bold lines in FIG. 15 are newly added, and PM1 and PM3 are shown by bold lines. As shown, the C-type path memory 27b and the C-type path memory 25b are respectively shown.
Has been added. Therefore, the newly added one and the one in which the B-type path memory is replaced with the C-type path memory will be described.
Differences in the configuration and operation of the PMU are evident with 4-value Viterbi decoding.

As described above in [(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means], the ACS2
1b outputs SEL0, SEL1, SEL2 and S
By operating the path memory unit PMU 23b according to EL3, a decoded information unit a ′ (k) as a maximum likelihood decoded sequence corresponding to the recording information unit a (k) is generated. The PMU 23b is composed of two A-type path memories and two C-type path memories in order to cope with the state transition between the four states of the quinary four-state Viterbi decoding shown in FIG.

As described above in [(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means], the A-type path memory includes the transition from itself, It is configured to have a transition from another one, and to correspond to a state having the transition as its starting point and a transition to itself and a transition to another one state.

The C-type path memory has transitions from the other two states as transitions to the state, and corresponds to a state having the transition from the state to the other two states. And a configuration for

In order for these two A-type path memories and two C-type path memories to perform an operation in accordance with the state transition of the quinary four-state Viterbi decoding in FIG.
The decoding information unit shown in FIG. That is, the A-type path memory 24 corresponds to S0, and the A-type path memory 26 corresponds to S2. Also C
The type path memory 25b corresponds to S1, and the C type path memory 27b corresponds to S3.

With this configuration, the state transitions that can occur starting from S0 are S0 → S0 and S0 → S1, and the state transitions starting from S2 are S2 → S2 and S2 → S3. . State transitions that can occur starting from S1 are S1 → S2 and S1 → S3.
And the state transition that can occur starting from S3 is S3 → S
0 and S3 → S1.

In the same manner as described above in [(1.D) Outline of Configuration and Operation of 4-Valued 4-State Viterbi Decoding Means], when SEL0 is, for example, 'Low',
In the A-type path memory 24, each flip-flop performs a serial shift that inherits the data of the flip-flop located at the preceding stage. If SEL0 is, for example, 'Hig
At the time of h ', parallel loading is performed to inherit the 14-bit decoded information unit PM3 supplied from the C-type path memory 27b. In either case, the inherited decoded information unit is supplied to the C-type path memory 25b as a 14-bit decoded information unit PM0.

[0171] In addition, the flip-flop 30 ₀ on the first stage, always in synchronization with the clock '0' is input. In this operation, since the decoding information unit is “0” as shown in FIG. 14 in any of the state transitions S0 → S0 and S3 → S0 leading to S0, the latest decoding information unit is always “0”. It is shown that.

The configuration of the A-type path memory 26 corresponding to S2 is exactly the same as that of the A-type path memory 24. However, the selection signal input from the ACS 21b is S
EL2. Further, as shown in FIG. 14, transitions to the state S2 include S2 → S2, that is, transitions inherited from itself, and state S1 → state S2. Therefore, PM1 is supplied from the C-type path memory 25b corresponding to the state S1. Further, since the state that can occur starting from the state S2 is S2, ie, itself, and S3, the PM2 is stored in the C-type path memory 27b corresponding to the state S3.
Supply.

The A-type path memory 26 corresponding to S2
In this case, "0" is always input to the flip-flop serving as the first processing stage in synchronization with the clock. Such an operation is a state transition S2 → S2 and S1 → S2 leading to S2.
In any case, as shown in FIG. 14, since the decoded information unit is '0', the latest decoded information unit always corresponds to '0'.

Next, as for the C-type path memories 25b and 27b, as shown in FIG.
b and the B-type path memories 25a and 27a in FIG.
That is, selectors 331 to 3314 drawn by a thick frame are added. FIG. 17 shows the C-type path memory 25b, but when SEL0 is, for example, "Low", parallel loading is performed to inherit the 14-bit decoded information unit PM0 supplied from the A-type path memory 24. Also, S
For example, when EL0 is “High”, the C-type path memory 27
14-bit decoded information unit PM supplied from b
Perform a parallel load that inherits # 3. The inherited decoded information unit is supplied to the C-type path memory 27b and the A-type path memory 26 as a 14-bit decoded information unit PM1.

The C-type path memory 25 corresponding to S1
b, the flip-flop 3 which is the first processing stage
A _value of “1” is always input to 20 in synchronization with the clock. Such an operation is a state transition S0 → S1 and S1 leading to S1.
In any of 3 → S1, as shown in FIG. 14, since the decoded information unit is “1”, the latest decoded information unit always corresponds to “1”.

The structure and operation of the C-type path memory 27b corresponding to S3 are exactly the same as those of the C-type path memory 25b. However, the selection signal input from the ACS 21b is SEL3. In addition, as shown in FIG.
The transition to state 3 is state S2 → state S3 and state S
1 → State S3. Therefore, A corresponding to state S2
PM2 is supplied from the type path memory 26, and PM1 is supplied from the C type path memory 25b corresponding to the state S1.
Furthermore, a state that can occur starting from state S3 is state S1.
And PM3 are supplied to the A-type path memory 24 corresponding to the state S0 and the C-type path memory 25b corresponding to the state S1.

The C-type path memory 27 corresponding to S3
Also in b, "1" is always input to the flip-flop as the first processing stage in synchronization with the clock. This operation is performed by the state transitions S1 → S3 and S2 → S3 leading to S3.
In any case, as shown in FIG. 14, since the decoded information unit is “1”, the latest decoded information unit always corresponds to “1”.

As described above, [(1.D) 4-value 4
Overview of Configuration and Operation of State Viterbi Decoding Means], the four path memories in PMU 23b each generate a decoded information unit. The four decoded information units generated in this way coincide with each other if an accurate Viterbi decoding operation is always performed.

When a mismatch occurs in the four decoded information units due to the influence of noise, for example, a method such as majority decision is used to
The configuration (not shown) that selects the more accurate one is PM
It is provided at the subsequent stage in U23b.

As described above, in the magneto-optical reproducing apparatus having the reproducing system for performing the Viterbi decoding method, the RLL (1,7) code is used,
Overview of (1.A) magneto-optical reproducing apparatus using R (1,2,1) type partial response waveform equalization characteristics, (1.
B) Outline of sector format of recording medium, (1.C)
Overview of the 4-value 4-state Viterbi decoding method (1.D) The configuration and operation of the 4-value 4-state Viterbi decoding means for realizing the 4-value 4-state Viterbi decoding method will be described. (2.A) 5-level 4-state Viterbi decoding method using a block code that uses the (1,2,1) type partial response waveform equalization characteristic and sector format and removes the constraint of the minimum value of 1 described above. And the outline of the configuration and operation of the (2.B) 5-value 4-state Viterbi decoding means have been described.

[(2.B) Embodiment of Information Reproducing Apparatus of the Present Invention] An embodiment of the information reproducing apparatus of the present invention will be described below with reference to FIGS. (1.D)
As described above in the outline of the configuration and operation of the four-level four-state Viterbi decoding means and the outline of the configuration and operation of (2.B) five-level four-state Viterbi decoding means, the four-level four-state Viterbi decoding means and the five-level four-state In the Viterbi decoding means, the ACS shown in FIG.
21 and ACS 21b in FIG. 16, and PMU 23a in FIG.
15, the PMU 23b in FIG. 15, the B-type path memories 25a, 27a in FIG. 13, and the C-type path memories 25b, 2 in FIG.
7b etc. can be understood by comparing the configuration and operation.
The portions indicated by the thick frames in FIGS. 15, 16 and 17 (hereinafter referred to as difference portions) correspond to FIGS. 11 and 1 respectively.
0, only different from FIG.

Therefore, if the above-mentioned difference is switched between the 4-level 4-state Viterbi decoding means and the 5-level 4-state Viterbi decoding means, both can be shared by the same means. In other words, it is possible to provide a four-level four-state Viterbi decoding unit by providing a five-level four-state Viterbi decoding unit in advance and switching the difference part as needed.

By the way, as described in (1.B) Outline of sector format of recording medium, VFO ₁ and VF
O ₂ and VFO ₃ are (hereinafter collectively referred to as VFO) four-valued four
A signal for performing the PLL synchronization of the state Viterbi decoding means is magnetically recorded or formed by embossing, and has a pattern (2T pattern) in which bits '0' and '1' which are channel-coded appear alternately. . Therefore, if the time corresponding to the one-bit length time is T, a reproduced signal c (k) whose level is inverted every 2T when a VFO field is reproduced is obtained.

When comparing the 2T pattern with the state transition diagram of the 4-level 4-state Viterbi decoding shown in FIG. 7, the state transition is as follows: state S0 → state S1 → state S2 → state S3 → state S
0, and the reproduction signal value is −
Since A → A → A → −A, this corresponds to a reproduced signal c (k) whose level is inverted every 2T.

On the other hand, in the state transition diagram of the 5-value 4-state Viterbi decoding shown in FIG. 14, the reproduced signal c (k) having a constant amplitude is obtained.
Investigation of the transition states in which is obtained, as in the case of four-valued four-state Viterbi decoding, transitions circulating in the order of state S0 → state S1 → state S2 → state S3 → state S0, and state S1 → state S
The transition goes from 3 to state S1. In the former case, the level A is inverted every 2T, whereas in the latter, the level is always “0” in the period T. Therefore, the latter transition is not suitable for PLL synchronization and is not suitable for 5 value 4-state Viterbi decoding.
The former 2T pattern is used similarly to the 4-state Viterbi decoding.

Next, consider the case where the 2T pattern reproduced from the VFO is decoded by the quinary 4-state Viterbi decoding means. If the recording medium has some scratches, the 2T pattern becomes When the pattern is partially changed to the T pattern, the reproduced signal c (k) becomes '0' only in the portion of the recording medium having the flaw.

The quinary 4-state Viterbi decoding means responds sensitively to the pattern of T. In the quinary 4-state Viterbi decoding state transition diagram of FIG. 14, the state S1 → state S3, state S3 →
A transition of state S1 occurs. That is, the decrypted VFO
The recording information unit is continuous "1" as can be seen from FIG.

As described above in (1.B) Outline of Sector Format of Recording Medium, VFO is 27 bytes, and 2T pattern is magnetically recorded. Therefore, when VFO is not decoded correctly, that is, continuous '1' If it is decoded as', the operation of the PLL unit 14 controlled by this decoded VFO will be unstable.

The above-mentioned inconvenience is caused by the use of quinary 4-state Viterbi decoding means for VFO decoding. Originally 2T
For the pattern, both the quinary 4-state Viterbi decoding means and the 4-level 4-state Viterbi decoding means state S0 → state S1 → state S2
Since it circulates on the state transition diagram as in → state S3 → state S0, the same decoded information unit should be obtained irrespective of the path metric regardless of which is used.

Therefore, when decoding the reproduced signal c (k) of the VFO, four-level four-state Viterbi decoding means is used, and when decoding the reproduced signal c (k) from the other sectors, five-level four-state Viterbi decoding is performed. If the decoding means is used, stable 5 values 4
State Viterbi decoding can be performed.

FIG. 18 shows an example of the configuration of an information reproducing apparatus having the above-described four-level four-state Viterbi decoding means and the five-level four-state Viterbi decoding means and capable of performing Viterbi decoding with stable synchronization. It is.

The BMC 20b and the PMU 23b are set to [(2.
B) Outline of Configuration and Operation of Five-Valued Four-State Viterbi Decoding Means]. The ACS 21c has an OR gate 63 and an OR gate 64 indicated by thick frames as shown in FIG.
Is newly added to the ACS 21b of FIG. A chg_state signal to be described later is added to these OR gates. When the chg_state signal becomes' Low ', all the output bits of the OR gate 63 become' Hig regardless of the value of L31.
h ′, that is, the highest value represented by the given number of bits. Since the comparator 61 always selects the smaller path,
The output of the comparator 61 is always L01. Also SEL1
At this time is always “High”, for example. Comparator 62
Similarly, L23 is always selected when the chg_state signal becomes 'Low', and SEL3 always becomes, for example, 'High' at this time.

L01 is always selected and SEL1 is always' H
igh ', L23 is always selected, and SEL3 is always'High'. This means that there is no transition between the state S1 and the state S3 in the state transition of 5-value 4-state Viterbi decoding. Equivalent to the state transition of 4-state Viterbi decoding. The fact that SEL1 and SEL3 are always “High” in the PMU 23b of FIG. 15 means that PM3 sent from the C-type path memory 27b to the C-type path memory 25b and the C-type path from the C-type path memory 25b indicated by bold lines. PM1 sent to the memory 27b is that it does not always selected by the selector 33 _to 333 ₁₄ in C-type path memory.

That is, the above-mentioned chg_state signal becomes “Low”.
BMC20b, ACS21c and PMU2
The 5-value 4-state Viterbi decoding means constituted by 3b is 4
It can be seen that the value has been switched to the 4-state Viterbi decoding means. On the contrary, it can be seen from the above description that the quinary-state Viterbi decoding means is used when the chg_state signal is 'High'. Therefore, the BMC 20b, AC in FIG.
The Viterbi decoding means constituted by S21c and PMU 23b is hereinafter referred to as variable Viterbi decoding means 99.

As described above, in order to perform quinary 4-state Viterbi decoding stably, 2T recorded on VFO3 in FIG.
The pattern may be decoded by the quaternary 4-state Viterbi decoding means, and the other sectors may be decoded by the quinary 4-state Viterbi decoding means.
The switching means of the state Viterbi decoding means (hereinafter referred to as mode switching means) will be described below. However, VFO ₁ ,
For VFO _2, VFO _3, is similar switching operation to be described below, it will be explained as a representative in the VFO _3.

[0196] As shown in FIG. 20, read Gate signal is a signal for detecting the first position P1 of the VFO _3, 27 byte on the basis of the read Gate signal, i.e., Sync starts from the time P2 , Followed by a data field and a buffer, and the sector ends. Also,
The chg_state signal is a signal for switching between quinary 4-state Viterbi decoding and quaternary 4-state Viterbi decoding. For example, as shown in FIG. 20, when the chg_state signal is "High", quinary 4-state Viterbi decoding and "Low" This is for switching the above-mentioned ACS 21c so that sometimes 4-level 4-state Viterbi decoding is performed.

In order to stably perform the mode switching at the time point P2, a desirable mode of the information reproducing apparatus of the present invention is to include the following mode switching means 96.

That is, the mode switching means 9 shown in FIG.
6, a mode switching means 9 from an external register or the like.
6, the parameters X1 and X2 for presetting the counting means 91 described later, and the counting means 9
A parameter CN for setting whether to count by 1 or not,
And a parameter md for setting a Viterbi decoding mode. This transfer is performed upon initial setting of the information reproducing apparatus of the present invention.

The parameter X1 is a numerical value represented by 1 bit, and the parameter X2 is a numerical value represented by, for example, 4 bits. The parameter CN is a numerical value represented by one bit. When the parameter CN is, for example, “High”, the preset unit 94 calculates the numerical value (27 × 8−X2) and the numerical value (27 × 8 + X2)
Is generated, and the counting means 91 described later is preset. That is, for example, when X1 is 'High', a numerical value (27 × 8−
X2), and when X1 is 'Low', a numerical value (27 × 8)
+ X2) is generated.

When the parameter CN is 'High',
The preset means 94 outputs "High" to the gate 90 so that the read clock DCK and the read gate signal can be passed from the gate 90.

The counting means 91 can preset the highest value to be counted, and is preset by the above-mentioned presetting means 94. That is, the highest value of the count is (27 × 8−
X2) and (27 × 8 + X2) can be variably set in the initial setting. The reason that the variable setting can be set in this way is at the time point P2, that is, VFO ₃ and Sy.
Since the boundary of nc and the boundary of mode switching change depending on the operating conditions of the recording medium and its driving device, this is for adjusting the timing of mode switching.

The counting means 91 and flip-flop 93 set as described above generate a read gate signal of, for example, 'Lo.
Time point when the signal changes from w to 'High'. At P1, the signal is reset by the read gate signal. At this time, the read clock DCK is input to the counting means through the gate 90 and counts up to a preset value. When the counting is completed, the flip-flop 93 is set to, for example, “High”.

On the other hand, as described later, when the parameter CN is, for example, “High”, the output of the gate 98 is “Low”.
, The output of the OR gate 92 becomes chg_state
Signal, that is, 'High'. The output of the OR gate 92 is the aforementioned chg_state signal.

On the other hand, the flip-flop 93 has a read gate
Since the signal is reset at the time point P1, the output is “Low” from the time point P1 to the time point P2, and the output of the OR gate 92 is “Low” for the same reason as described above.

That is, the chg_state signal is set to r at time P1.
'Hig' when the ead gate signal changes from 'Low' to 'High'
After the read clock DCK is counted up to the preset value by the counting means 91, the count changes from 'Low' to 'Hi'.
Return to gh '.

As described above, when the chg_state signal goes low, the BMC 20b, ACS 21c and PMU 23b
Is set to the 4-value 4-state Viterbi decoding means, and conversely, the chg_state signal is set to 'H
igh ', the mode is switched to the quinary 4-state Viterbi decoding means.
₃ can be decoded by the quaternary 4-state Viterbi decoding means, and the rest can be decoded by the quinary 4-state Viterbi decoding means. Therefore, as described above, even if the VFO ₃ has a flaw in the T pattern, it is not detected by the 4-value 4-state Viterbi decoding means, and the decoding is performed only on the 2T pattern, and the decoding is performed with stable synchronization. In addition, portions other than VFO ₃ can be decoded by the quinary 4-state Viterbi decoding means. The switching operation of the state transition of Viterbi decoding has been described above by taking VFO ₃ as an example. Viterbi decoding is also performed in the same manner for VFO ₁ and VFO ₂ in the four-value four-state switching.

As another desirable form of the information reproducing apparatus of the present invention, a mode switching means 96 capable of coping with an application of always fixing to one of the decoding means by initial setting without depending on the counting means 91. It is to have. Hereinafter, this will be described.

The gate 98 receives the parameter md and the parameter CN. The parameter md is for switching the mode of Viterbi decoding. For example, md
Is "High", the 4-level 4-state Viterbi decoding means, md is
In the case of "Low", the mode is switched so as to be a quinary 4-state Viterbi decoding unit.

When the parameter CN is “High”, the output of the gate 98 is always “Low”. Therefore, as described above, the output of the OR gate 92 becomes equal to the output of the flip-flop 93, but the parameter CN becomes “High”. In the case of "Low", the output of the gate 98 becomes equal to the parameter md.

On the other hand, when the parameter CN is 'Low',
Preset means 94 applies a 'Low' output to gate 90,
The gate 90 prevents the read clock DCK and the read gate signal from passing therethrough. Therefore, the flip-flop 93 is always reset and its output is always' Lo.
w '.

Therefore, when the parameter CN is “Low”, the output of the gate 92 is the output of the gate 98, that is,
This is the value of the parameter md. As a result, a mode switching unit capable of coping with an application in which decoding is always fixed to one of the decoding units by the initial setting becomes possible.

In the present embodiment, the magneto-optical reproducing device has been described as an example of the information reproducing device.
The present invention is not limited to this, and can be applied to a magnetic reproducing apparatus that reproduces information from a magnetic disk or a magnetic tape by using a magnetic head, or an optical reproducing apparatus that reproduces information from a layer change disk by using an optical pickup.

[0213]

According to the information reproducing apparatus of the present invention, by providing the variable Viterbi decoding means and the mode switching means, it is possible to Viterbi-decode the information channel-coded by a plurality of different block codes. The size and power consumption of the information reproducing apparatus can be reduced, and the mode of Viterbi decoding is switched between the area of the synchronization information recorded on the recording medium and the area of the information, so that stable synchronization with respect to noise can be achieved. Viterbi decoding can be performed on the basis.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an example of a magneto-optical reproducing apparatus that performs 4-level 4-state Viterbi decoding according to the present invention.

FIG. 2 is a schematic diagram for explaining a mark position recording method and a mark edge recording method.

FIG. 3 is a schematic diagram for explaining an example of a sector format of a magneto-optical disk according to the present invention.

FIG. 4 is a schematic diagram showing that the minimum magnetization reversal width is 2 in the RLL (1, 7) encoding method.

FIG. 5 shows a reproduction signal reproduced from a recording information unit recorded by a combination of an RLL (1, 7) code and a mark edge recording method, with a partial response characteristic PR.
FIG. 7 is a schematic diagram for explaining an eye pattern when waveform equalization is performed under (1, 2, 1).

FIG. 6 is a schematic diagram for explaining a process of creating a state transition diagram of the 4-value 4-state Viterbi decoding method.

FIG. 7 is a schematic diagram illustrating an example of a state transition diagram of a 4-value 4-state Viterbi decoding method.

FIG. 8 is a schematic diagram illustrating an example of a trellis diagram in a 4-level 4-state Viterbi decoding method.

FIG. 9 is a schematic diagram showing conditions of state transition based on a standardized metric in a four-value four-state Viterbi decoding method.

FIG. 10 is a block diagram illustrating an overall configuration of a Viterbi decoding unit that performs a 4-value 4-state Viterbi decoding method.

11 is a block diagram showing in detail the configuration of a part of the Viterbi decoding unit shown in FIG.

12 is a block diagram showing in detail the configuration of another part of the Viterbi decoding unit shown in FIG.

FIG. 13 is a block diagram showing in detail a configuration of still another part of the Viterbi decoding unit shown in FIG. 10;

FIG. 14 is a schematic diagram illustrating an example of a state transition diagram of a 5-value 4-state Viterbi decoding method.

FIG. 15 is a block diagram illustrating an overall configuration of a Viterbi decoding unit that performs a 5-value 4-state Viterbi decoding method.

16 is a block diagram showing in detail a configuration of a part of the Viterbi decoding unit shown in FIG.

FIG. 17 is a block diagram showing in detail the configuration of another part of the Viterbi decoding unit shown in FIG.

FIG. 18 is a block diagram illustrating an example of a configuration of an information reproducing apparatus according to the present invention.

19 is a block diagram showing a part of an example of the configuration of the information reproducing apparatus of the present invention shown in FIG.

FIG. 20 is a schematic diagram showing a relationship between a sector format and switching of Viterbi decoding means of the magneto-optical reproducing device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Host computer, 2 ... Controller, 6 ... Magneto-optical disk, 7 ... Optical pickup, 8, 9 ... Amplifier, 1
0: Sum signal / difference signal switch, 11: Filter section,
12 A / D converter, 13 Viterbi decoding means, 14 P
LL part, 20a, 20b ... BMC, 21a, 21b, 2
1c ... ACS, 23a, 23b ... PMU, 24, 26 ...
A type path memory, 25a, 27a ... B type path memory, 2
5b, 27b: C-type path memory, 51, 52, 53, 5
4, 56, 58, 59, 60 ... adders, 55, 57, 6
1, 62... Comparators, 30 ₀ to 30 ₁₄ , 32 _{0 to} 32 ₁₄ ,
93 ... Flip-flop, 31 _{1 to} 31 ₁₄ , 33 _{1 to} 3
3 ₁₄ selector, 99 variable Viterbi decoding means, 96 mode switching means, 63, 64, 90, 98 gate
91: counting means, 94: preset means, 95: storage means, 92: OR gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03M 13/12 H03M 13/12

Claims (4)

[Claims] The information is divided into a plurality of information units, at least the plurality of information units are encoded, and encoded synchronization information for synchronizing the phases of the information units is added, and the encoded information is encoded as a sector. From a recording medium on which information is recorded,
In an information reproducing apparatus for reproducing the sector and decoding the information by a Viterbi decoding unit, the synchronous information is recorded from the sector in order to decode and extract the synchronous information stable against noise. A mode switching unit for changing a state transition condition of the Viterbi decoding method between an area on the recording medium and an area on the recording medium on which the plurality of information units are recorded; and An information reproducing apparatus, comprising: a variable Viterbi decoding means that can change. 2. The mode switching means can control the mode switching timing in accordance with a reproduction condition by control information sent serially from the outside,
2. The information reproducing apparatus according to claim 1, wherein a state transition condition of a specific Viterbi decoding method can be fixedly selected. 3. The variable state Viterbi decoding means can vary state transition conditions by externally controlling means for comparing and selecting the likelihood of state transition.
An information reproducing apparatus according to claim 1. 4. The information reproducing apparatus according to claim 1, wherein said information reproducing apparatus is one of a magnetic reproducing apparatus and an optical reproducing apparatus.