JPH11339469A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a semiconductor memory device in which a refresh time can be apparently hidden and a bus occupation time in a system can be reduced. SOLUTION: This is a 2-bank 64Mbit SDRAM, which includes memory array banks of bank 0 and bank 1, row decoder, column decoder, sense amplifier & input / output bus, and refresh counter corresponding to each memory array bank. A refresh counter corresponding to each memory array bank is provided, including a common address buffer, an address counter, an input buffer, an output buffer, a control logic & timing generator, etc., and a bank hidden refresh in a test mode of the mode register set MRS. By selecting BHR, the read operation of the operation bank 0 specified by the active command ACT can be performed, and the refresh operation of the non-operation bank 1 not specified can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly to a semiconductor memory device such as a synchronous DRAM (SDRAM) having a plurality of banks and capable of responding to a demand for a high-speed memory such as a CPU. It relates to technology that is effective when applied to equipment.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in an SDRAM, since written data leaks and disappears with time due to the structure of a memory cell in which electric charges are stored in a capacitor and stored, A refresh operation for holding the storage information of the memory cell is required at regular time intervals.
AS only refresh, CBR (CAS be
For RAS) refresh, self-refresh, etc. are used.

In such a memory cell refresh operation, for example, the number of logical word lines is 409.
In the case of six lines and a maximum refresh time of 64 ms,
It is necessary to sequentially select 4096 word lines in accordance with a combination of external address signals within a period of 4 ms, and re-inject charges into the capacitors of the memory cells connected to the word lines. That is, the maximum refresh time of 64 ms
Must be refreshed for 4096 cycles.

[0004] As a technique relating to such a semiconductor memory device such as an SDRAM, for example, in 1994
"Advanced Electronics I-9 Ultra LSI Memory" published by Baifukan Co., Ltd. on January 5, P344-P3
48 and the like.

[0005]

In a semiconductor memory device such as the SDRAM as described above, the S
In order to occupy a bus of a system including a CPU together with a memory such as a DRAM at the time of a refresh operation, it is required to reduce the bus occupation time and respond to a demand for a high-speed memory by a high-speed CPU or the like. I have.

It is an object of the present invention to perform a refresh operation in parallel with a read operation or a write operation so that a refresh time can be apparently hidden and a bus occupation time in a system can be reduced. A storage device is provided.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor memory device according to the present invention comprises a row address buffer and a column address buffer, a plurality of row decoders and a plurality of column decoders for selecting an arbitrary memory cell in a plurality of memory array banks, and a plurality of memories. The array bank has a plurality of refresh counters for each arbitrarily divided memory array bank, which counts address signals for performing a refresh operation in a non-operation bank among the array banks.

This configuration has an operation mode in which a non-operation bank is refreshed (or a precharge operation or a mode register set operation) while a read operation or a write operation is performed in the operation bank. The selection is made in the test mode of the mode register set by the combination of the set command and the address, or the selection is made not by the test mode but by a normal mode register set command.

Therefore, according to the semiconductor memory device, the refresh time can be apparently hidden by the parallel operation of the read operation or the write operation and the refresh operation, and the occupation time of the bus in the system can be reduced. This is because during the operation of one bank, the other bank is automatically refreshed by the reverse operation, and it can be made to appear refresh-free. Further, a precharge operation and a mode register set operation can be automatically performed. In particular, an SDR having a plurality of memory array banks
The present invention can be applied to AM and RDRAM, and further to DRAM in general.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall block diagram showing a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 shows a case where a refresh operation is performed in parallel with a read operation in the semiconductor memory device of this embodiment. It is a timing chart.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 2-bank 64-Mbit SDRAM,
The memory array banks 1 and 2 of the bank 1 and the row decoders 3 and 4 corresponding to the memory array banks 1 and 2, the column decoders 5 and 6, the sense amplifier & input / output buses 7,
8, refresh counters 9, 10 and a common row address buffer 11, column address buffer 1
2, column address counter 13, input buffer 14,
It has a configuration such as an output buffer 15 and a control logic & timing generator 16, and is formed on one semiconductor chip by a well-known semiconductor manufacturing technique.

The SDRAM receives an address signal Ai from the outside, generates a row address signal XA and a column address signal YA, and inputs them to a row address buffer 11 and a column address buffer 12, respectively. An arbitrary memory cell in memory array banks 1 and 2 is selected via column decoders 5 and 6. The input / output data DIOi is input via the input buffer 14 during a write operation, and is supplied to the sense amplifier & input / output buses 7 and 8 and the output buffer 15 during a read operation.
Is output via.

The control signals include an external clock signal CLK, a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS,
A column address strobe signal / CAS, a write enable signal / WE, a data mask signal DQM, and the like are input from the outside, and a command and an internal control signal are generated by the control logic & timing generator 16 based on these control signals. The operation of the internal circuit is controlled by an internal control signal.

In particular, the present embodiment has an operation mode function of refreshing a non-operation bank while performing a read operation or a write operation in an operation bank. For this purpose, each memory array bank divided arbitrarily is provided. A plurality of refresh counters are provided. FIG.
In such a two-bank configuration, one refresh counter is normally shared, but in the present embodiment, refresh counters 9 and 10 are provided corresponding to the memory array banks 1 and 2, respectively.

Next, regarding the operation of the present embodiment, an outline of the basic operation of the SDRAM will be briefly described first.

All operations of the SDRAM are performed in synchronization with the internal clock signal, and each operation is controlled by a command. This command includes a chip select signal / CS, a column address strobe signal / CAS,
It is defined by a combination of control signals of a row address strobe signal / RAS and a write enable signal / WE.

That is, commands such as bank active, read, write, precharge, and refresh are defined by the high / low state of these control signals at the rising edge of the internal clock signal, and these commands are decoded and each command is decoded. Causes the circuit to execute an operation corresponding to the command.

For example, in a standby state of a read operation or a write operation, when a memory array bank designated by setting of a bank active command is selected to activate a designated word line, and a read command is set, Data can be read from the selected bank, and data can be written to the selected bank when a write command is set.

When a precharge command is set, a precharge operation of a specified memory array bank can be performed, and the precharge is automatically performed after a read operation or a write operation is completed. There are a read command with auto-precharge and a write command with auto-precharge for executing the operation.

Further, the refresh command includes, for example, an auto-refresh command and a self-refresh command. In setting the auto-refresh command, an address is generated internally and the refresh operation is automatically performed. This is performed for battery backup and the like, and after the self-refresh operation is completed, an auto-refresh operation is performed.

As described above, the basic operations of the bank active operation, the read operation, the write operation, the precharge operation, and the refresh operation of the SDRAM are executed. These basic operations are executed by, for example, starting the actual operation after precharging all the memory array banks, setting the mode register, and performing auto-refresh after power-on.

Next, an operation mode which is a feature of the present invention will be described.
Description will be made based on the timing chart of FIG.

This operation mode is a so-called "bank hidden refresh" in which a non-operation bank is refreshed while a read operation (or a write operation) is performed in the operation bank. The timing of this operation mode is performed in synchronization with the internal clock signal ICLK.

First, in the test mode of the mode register set MRS, the bank hidden refresh BHR is selected by a specific address code. This address code can be dealt with by adding a code such as A2 = 1, A1 = 0, A0 = 0 to a normal address ADD specification. After the selection of the bank hidden refresh BHR, an operation bank for performing a read operation (or a write operation) is designated by the bank select signal BS by the active command ACT as usual.

For example, in the case of a read operation, a read command READ is input, and an active command AC is input.
At T, the read operation of the operation bank (bank 0) specified by the bank select signal BS is performed. This read operation is performed in the same manner as the basic operation, and the read command R
Data is output after a CAS latency cycle of the EAD set cycle, and data having a length set by the burst length is output in synchronization with internal clock signal ICLK.

At the same time, a non-operating bank (bank 1) which is not specified performs a refresh operation using the refresh counter 10 corresponding to the bank 1 in parallel with the read operation. This refresh operation is performed in the same manner as the above-described basic operation by the refresh command REF. The refresh counter 10 is counted up to generate an internal address ADD. Refresh.

As described above, at the time of the bank hidden refresh BHR, by inputting the active command ACT and the read command READ, the read operation is performed by accessing the bank 0 which is the operation bank specified by the active command ACT. At the same time, the refresh operation of bank 1, which is a non-operating bank not specified, can be performed. Conversely, when the bank 1 is designated, the refresh operation of the bank 0 can be performed in parallel with the read operation of the bank 1.

Similarly, in the write operation, by inputting an active command ACT and a write command during the bank hidden refresh BHR, the refresh operation of the bank 1 is performed in parallel with the write operation of the bank 0 specified by the select signal BS. , Or conversely, when bank 1 is designated, the refresh operation of bank 0 can be performed in parallel with the write operation of bank 1.

Therefore, according to the semiconductor memory device of the present embodiment, the refresh counters 9 and 10 corresponding to the memory array banks 1 and 2 are provided, and the operation mode of the bank hidden refresh BHR in the test mode of the mode register set MRS is provided. , The other bank can be refreshed by the back operation during the read operation or the write operation of one bank, so that the refresh time can be apparently hidden.

Therefore, at the time of one-bank operation, it is possible to make the display look refresh-free. However, this cannot be applied to two-bank operation or continuous operation of the same row address. As a result, in a system including a CPU together with a memory such as the SDRAM, the occupation time of the bus in the system can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 1
The operation mode in which the other bank is refreshed at the time of the read operation or write operation of the bank has been described. However, the present invention is not limited to this. The precharge operation or the other bank is performed at the time of the read operation or write operation of one bank. Mode register set (MR
S) The present invention is also applicable to a case in which there is an operation mode for operating.

In the case of this precharge operation, by using a method such as generating a signal when the bank is switched, if another bank is accessed, the original bank can be automatically precharged. it can. MRS
The operation is similar, but in this case, it is necessary to set the mode register when the MRS command is automatically input. However, since the precharge operation or the MRS operation can be performed in one cycle, the above-described refresh operation is most effective.

Further, the setting of the operation mode is not the test mode, but the bank hidden refresh can be similarly selected by combining with a specific address code in a normal MRS command. This command can also be handled by adding it to an existing normal command specification.

Although the description has been given of the example of the 2-bank 64 Mbit SDRAM, the present invention is widely applied to, for example, 4 banks, 8 banks, and more banks, and to 256 Mbits and SDRAMs having a larger capacity. It is possible, and the effect of the present invention is further increased by adopting such a multi-bank, large-capacity configuration.

In the configuration of four banks, eight banks, etc., it is not always necessary to provide a refresh counter corresponding to each memory array bank. 1 in
By providing one refresh counter, the refresh operation,
A precharge operation or an MRS operation can be performed.

Also, the case where the present invention is applied to the SDRAM has been described.
The present invention can be applied to M and general DRAMs, and can be widely applied to a system including a CPU together with a memory such as the DRAM.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By having a plurality of refresh counters for each arbitrarily divided memory array bank, while performing a read operation or a write operation in the operation bank,
Since the inactive banks can be automatically refreshed in parallel, the refresh time can be apparently hidden.

(2) If there is an operation mode in which a non-operation bank performs a precharge operation or a mode register set operation while performing a read operation or a write operation in the operation bank, the precharge operation and the mode register set are performed in parallel. The operation can be performed automatically.

(3) When the operation mode is selected by the test mode of the mode register set or the normal mode register set command, it can be easily handled only by adding the address code and the command to the normal specification. Becomes possible.

(4) According to the above (1) to (3), SDRAM, RDRAM, DRAM having a plurality of memory array banks
In such a case, the refresh time can be apparently hidden to make it appear refresh-free, and further, in a system including a CPU and the like together with these memories, the bus occupation time in this system can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a case where a refresh operation is performed in parallel with a read operation in the semiconductor memory device according to the embodiment of the present invention;

[Explanation of symbols]

 1, 2 memory array bank 3, 4 row decoder 5, 6 column decoder 7, 8 sense amplifier & input / output bus 9, 10 refresh counter 11 row address buffer 12 column address buffer 13 column address counter 14 input buffer 15 output buffer 16 control Logic & timing generator

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hirohiko Yoshida 5-2-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Cho LSI Systems, Ltd. (72) Inventor Toshimitsu Agatsuma Tokyo 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ultra-SII Systems Co., Ltd. (72) Megumi Tsuchiya 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. (72) Inventor Yumiko Noguchi 5-2-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Systems

Claims (6)

[Claims] 1. A semiconductor memory device having a plurality of memory array banks, comprising: a row address buffer and a column address buffer for storing an externally input address signal; and output signals from the row address buffer and the column address buffer. A plurality of row decoders and a plurality of column decoders for selecting an arbitrary memory cell in the plurality of memory array banks by designating a row address and a column address, respectively, according to an address signal. A semiconductor memory device comprising: a plurality of arbitrarily divided refresh counters for each memory array bank for counting address signals for performing a refresh operation in an operation bank. 2. The semiconductor memory device according to claim 1, wherein a refresh operation is performed in a non-operation bank while a read operation or a write operation is performed in a selected operation bank among the plurality of memory array banks. A semiconductor memory device having a mode. 3. The semiconductor memory device according to claim 1, wherein a precharge operation or a mode is performed in a non-operation bank while performing a read operation or a write operation in a selected operation bank among the plurality of memory array banks. A semiconductor memory device having an operation mode for performing a register set operation. 4. The semiconductor memory device according to claim 2, wherein said operation mode is selected in a test mode of a mode register set based on a combination of a mode register set command and an address. Storage device. 5. The semiconductor memory device according to claim 2, wherein said operation mode is selected by a mode register set command. 6. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous DRAM.