JPH11330867A - Bias circuit for CMOS amplifier and method for adjusting channel length of MOS transistor in bias circuit - Google Patents

Abstract

(57) Abstract: Even if a power supply voltage is arbitrarily changed from 3 V to 5 V, a channel length of a transistor or the like constituting a bias circuit is selectively adjusted to provide a CMOS operational amplifier and a comparator. The performance of such analog / mixed mode circuits is kept constant. SOLUTION: A part directly driving an amplifier uses a transistor having a short channel length or the like, and the other part selectively uses a transistor or the like having a long channel to reduce a short channel effect. Almost constant performance can be obtained with respect to the change of.
The technique of adjusting the channel length of the transistor applied to the amplifier bias circuit reduces short channel effects, current mismatch, and the like, so that a bias current independent of the power supply voltage can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit for a CMOS amplifier, and more particularly to a CMO for selectively adjusting a channel length of a bias transistor constituting a bias circuit of a CMOS amplifier to improve an operation performance.
S amplifier bias circuit and MO in the bias circuit
The present invention relates to a method for adjusting the channel length of an S transistor.

[0002]

2. Description of the Related Art In general, CMOS amplifiers and comparators, which are one of the most basic basic blocks in a CMOS analog / mixed-mode circuit block, have an MO.
Various applications are possible by combining S transistors, capacitors and switches. At the same time, the CMOS amplifier has an A / D converter (analog / digital converter), a D /
PLL (Phase) including system input / output interface circuits such as A converter (digital / analog converter)
Locked Loop), filters, etc., have a very wide range of applications.

Accordingly, a CMOS amplifier capable of maintaining a constant performance even when the power supply voltage changes is implemented as follows.
It can be easily used for a cell library together with another digital block, and diversification of applications can be achieved. Recently, a demand for a hybrid mode circuit design in which a digital circuit and an analog circuit coexist on a single chip has been gradually increased due to the trend of miniaturization, low voltage, and low power due to the progress of the process and better performance. This, along with mobile communications equipment, notebooks, etc., has greatly increased the demand for low power systems.

In connection with this, various low power circuit design techniques and the like are currently being researched and developed in the digital and analog domains. For example, in a large-scale mixed mode integrated circuit system in which analog and digital circuits coexist, an analog circuit such as an amplifier or an operational amplifier can be used as a block with extremely high power consumption. Requires a low-power circuit design. As one of the methods for solving this from the aspect of the whole system, there is proposed a structure in which one operational amplifier is shared by adjacent ends in an existing pipelined A / D converter system composed of several stages. Have been.

[0005] This is because during the sampling of the signal voltage input to one end in an open-loop manner, an operational characteristic in which an amplifier is not used is used. By using it, the area and power consumption of the entire system are reduced.

However, the series resistance and the parasitic capacitance of many switches added for sharing the amplifier may adversely affect the settling time, and the layout becomes complicated when the system is designed. There is.

One of the most effective ways to reduce system power consumption without changing the circuit structure is one of the most effective methods.
On the other hand, low power supply voltages are often used, which is particularly advantageous for digital blocks. Using the same level of power supply voltage for the analog and digital blocks in the design of the analog / mixed mode circuit eliminates the need for an additional power supply voltage, thereby reducing overall system cost.

However, in existing cell libraries used for various multimedia systems, power supply voltages suitable for almost all operations have already been determined. Therefore, an analog block such as an amplifier is accompanied by a decrease in performance such that it is difficult to obtain a high voltage gain and a large output signal margin by using a low power supply voltage, unless otherwise considered in circuit design.

In particular, in the case of a bias circuit which may affect the performance of an amplifier, the use of a short channel effect due to the tendency of related elements and the like to become submicron due to recent factory development has led to the use of a short channel effect. The bias current due to the supplied power supply voltage changes very much.

The circuit block whose performance can be changed by the power supply voltage used in this manner must be redesigned in accordance with the power supply voltage used to maintain a constant performance. It is indispensable to design circuits so that the operation performance can be maintained almost independently of each other in order to diversify applications.

If a power supply voltage having a magnitude different from that at the time of design is used for the operational amplifier, the short channel effect, which is a weak point of the submicron process, and the resulting current mismatch, etc.
It is difficult to maintain constant performance. Current mirro
All MOS transistors and the like in a typical amplifier bias circuit composed of r) have been designed to have the same size channel length as much as possible in order to reduce the mismatch between bias currents.

However, when the power supply voltage increases or decreases, a change in output impedance due to the influence of the short channel effect causes a large current mismatch, which is caused by a change in performance of the operational amplifier such as a signal-to-noise ratio (SNR). Directly connected to

While such short channel effects can be reduced by the use of long channel length transistors, transistors that directly drive the amplifier, etc., must have the same channel length as the transistors used in the amplifier. On the other hand, the shorter the channel length of the transistor used in the amplifier, the more the voltage gain is ensured, the smaller the parasitic capacitance and the like, so that high-speed performance can be obtained.

FIG. 1 shows a general complementary differential cascode amplifier using MOS transistors or the like. The input of the amplifier is composed of six transistors (M1-M6), and the transistors (M2, M3) and transistors (M4, M5) of the complementary input pair to which the inputs are applied improve the matching of each input pair. In order to obtain a maximum signal bandwidth with a minimum size, a structure having a minimum channel length is usually used.

The signal bandwidth is directly proportional to the transconductance gm of the input pair, which gm
Is proportional to {W (channel width) / L (channel length)} ^1/2 which is the size ratio of the input to the MOS transistor. Can be used as small as necessary.

The output terminal has eight transistors (M7-M1).
4) The channel length of a transistor or the like uses a channel length longer than the minimum channel length in order to obtain a sufficiently high voltage gain and at the same time reduce parasitic capacitance. Determined by the structure.

The transistors (M7) and (M8) that supply current to the cascode output terminal and the transistors (M1) and (M6) that supply current to the two input pairs maintain a constant voltage ratio therebetween. Typically use the same channel length (L1). Because, in a circuit using MOS transistors, the current is W
This is because they flow exactly in proportion to the ratio of / L. The most effective but inexpensive way to maintain this current constant is to fix the channel length L and adjust only the channel width W to adjust the current magnitude.

When the minimum channel length is used in order to minimize erroneous effects such as an increase in parasitic capacitance and chip area, the channel width L is set to a value corresponding to the channel width for the same W / L ratio. There is also a positive aspect that it is possible to reduce the current change due to the drain voltage generated from the short channel process, that is, in order to minimize the short channel effect, the channel longer than the minimum channel length defined in the process Must be used.

That is, two input pairs (M2, M3) (M4, M
5) The transistors (M1, M6) that supply current to the current also maintain a constant current ratio between each other, and increase the chip area in proportion to the parasitic capacitance and the channel length to width ratio W / L. In order to minimize the effect, a channel as short as possible is used, but in the short channel process, a channel (L1) which is somewhat longer than the minimum channel length is used in consideration of a current change due to a drain voltage.
The channel length (L1) does not need to be the same for the PMOS and NMOS transistors, but the same value is used for convenience of design, and the principle of circuit design is the same even if different values are used.

The common mode feedback block (CMFB)
This is a circuit that maintains a common mode of a stable output voltage with a fully differential structure amplifier. A typical common mode feedback block (CMFB) is a static, non-clocked configuration that requires continuous current drive.
Dynamic mode with reduced electrode consumption using common mode feedback block (CMFB), capacitors and clocks
There are two types of (dynamic) common mode feedback blocks (CMFB), all of which can be used. FIG.
Circuit uses the structure of a dynamic common mode feedback block.

FIG. 2 shows a conventional bias circuit for supplying an operating current to the CMOS amplifier of FIG. The reference current supplied from the outside is indicated by IBSIN, and the current flowing through the MOS transistor that determines each bias voltage is indicated by IBS1 to IBS5. At the same time, the first and second bias voltages (BIAS2, BIAS
5) is a voltage that can sufficiently ensure an operation area of each MOS transistor and the like in the amplifier and an output margin of the amplifier. The fifth bias voltage (BIAS5) is for maintaining a common mode of the amplifier output. Voltage. The fifth bias voltage (BIAS5) is equal to the fourth bias voltage (BIAS5).
AS4) and a common common mode feedback block, which can share one bias voltage with each other but requires a repetitive switching operation by a clock, as well as a static common mode feedback block. Is used separately for more stable amplifier operation.

The first and fourth bias voltages (BIAS1) and (BIAS4) for supplying the necessary operating current to the amplifier are:
The direct drive of a current mirror transistor or the like that supplies current to the amplifier directly changes the performance of the amplifier. Therefore, the first bias current (IBS1) and the fourth bias current (IBS4) are particularly important in the design of the amplifier, and the current mismatch between the currents must be small.

On the other hand, as for the channel length of all the transistors constituting the current mirror used in the above bias circuit, the same length L1 as the channel length of the transistor used in the amplifier was used.

[0024]

Therefore, when the power supply voltages VDD and VSS change during the operation of the circuit, transistors and the like (MP2, MP3, MP6, MN1, MN) having gates and drains connected and operated by diodes.
4, MN5), compared to the current flowing through the transistor (M
The current flowing through P1, MP4, MP5, MN2, MN3) will cause a very large change due to the change in drain voltage due to the short channel effect. The change in voltage and current in such a bias circuit is immediately linked to the current repeater of the amplifier, and has a direct effect on the performance of the amplifier.

The influence of the bias and the current change of the amplifier circuit due to the change of the drain voltage of the bias circuit is as follows.
The channel length of all the transistors and the like of the bias circuit can be made much larger than L1, and can be fundamentally minimized. On the other hand, transistors and the like operated by diodes (MP2, MP3, MP6, MN1, MN
4, MN5) is directly connected to the amplifier, so that the channel length cannot be adjusted.

For example, the channel lengths of the NMOS transistors and the like (MN2, MN3, MN4) in FIG. 2 need to be the same for current matching, and the channel length of the transistor (MN4) for driving the amplifier is In order to reduce unwanted parasitic components on the amplifier side, a relatively short channel length such as L1 must be used.
In order to reduce the effect of the short channel length on the drain mode side of the transistors (MN2, MN3), a long channel must be used.

However, in the conventional bias circuit having the above-described structure, the channel length of all the transistors constituting the current mirror is the same as the channel length of the transistor used in the amplifier (L1). Sometimes, the performance of the amplifier is adversely affected, and the performance of the amplifier is degraded.

The present invention has been proposed in order to solve the above-mentioned various problems caused by the conventional bias circuit of the CMOS amplifier. Another object of the present invention is to provide a bias circuit for a CMOS amplifier and a method for adjusting the channel length of a MOS transistor in the bias circuit, which can maintain the performance of the amplifier substantially constant against a change in power supply voltage by a simple method. It is another object of the present invention to minimize the operating conditions and performance of operational amplifiers by minimizing the bias current mismatch that can occur when the power supply voltage applied to the bias circuit of a CMOS operational amplifier changes. CMO that can maintain various parameters and diversify its applications
S amplifier bias circuit and MO in the bias circuit
An object of the present invention is to provide a method for adjusting the channel length of an S transistor.

[0029]

According to the present invention, there is provided a bias circuit for a CMOS amplifier, comprising: a plurality of bias transistors for supplying a bias voltage to a transistor of the amplifier; It comprises a plurality of current mirror transistors forming a current mirror for providing a current to the bias transistor, and a plurality of current mirror driving transistors driving the plurality of current mirror transistors.

Further, the channel length of the plurality of bias transistors is the same as the channel length of the transistor constituting the amplifier receiving the bias voltage.

The channel length of the plurality of current mirror transistors is longer than the channel length of the plurality of bias transistors.

Further, the channel length of the plurality of current mirror transistors is long enough to prevent a short channel effect.

Further, according to the method of adjusting the channel length of a transistor constituting a bias circuit of a CMOS amplifier according to the present invention, the channel length of a large number of bias transistors for supplying a bias voltage to the amplifier is determined by controlling the supply of the bias voltage. The channel length of a large number of current mirror transistors constituting a current mirror for supplying current to the large number of bias transistors and the like is the same as the channel length of the transistors and the like of the amplifiers to be received. Formed from a long channel, transistors and the like for driving the large number of current mirror transistors are separately configured, and the channel length is
The current mirror transistor is formed to have the same channel length as the current mirror transistor.

The channel length of the current mirror transistor and the like and the transistor for driving the current mirror transistor and the like are characterized in that they are long enough to prevent a short channel effect.

That is, according to the present invention, the part for directly driving the amplifier uses a transistor or the like having a short channel length, and the other part selectively uses a transistor or the like having a relatively long channel length to selectively use a power supply voltage. To obtain almost constant performance with respect to changes in

Also, the selective channel length adjustment technique applied to the amplifier bias circuit reduces short channel effects, current mismatch, etc., so that a bias current independent of the power supply voltage can be obtained.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention based on the above-described technical concept will be described below in detail with reference to the accompanying drawings. FIG. 3 shows a bias circuit of a CMOS amplifier according to the present invention. Here, the reference current supplied from the outside is represented by IBSIN, and the current flowing through the MOS transistor that determines each bias voltage is represented by IBS31 to IBS35.
At the same time, the first and second bias voltages (BIAS2, BIAS2)
AS3) is a voltage that can sufficiently ensure the operation area of each MOS transistor and the like in the amplifier and the output margin of the amplifier. The fifth bias voltage (BIAS5) is for maintaining the common mode of the amplifier output. Voltage.

The fifth bias voltage (BIAS5) is the fourth bias voltage (BIAS5).
It has a voltage similar to the bias voltage (BIAS4) and can use one bias voltage in common with each other. However, not only a dynamic common mode feedback block that requires repetitive switching operation by a clock but also a static common mode feedback block When a mode feedback block is used, it is separately used for more stable amplifier operation.

The first and fourth bias voltages (BIAS1) (BIAS4) for supplying the necessary operating current to the amplifier are:
Directly driving a current mirror transistor or the like that supplies current to the amplifier directly changes the performance of the amplifier. Therefore, the first bias current (IBS1) and the fourth bias current (IBS4) are particularly important in the amplifier design, and the current mismatch between the currents must be small.

Therefore, in order to transfer a constant current, the present invention adds two MOS transistors (MNA, MPA) to a conventional bias circuit as shown in FIG. Implement a bias circuit. That is, two transistors (MN
A, MPA), without affecting the rest of the circuit, and adding the transistors (MNA) to the required degree.
For example, the channel length can be adjusted to L2 longer than L1.

Here, all the transistors (MN) operating as diodes excluding the transistor (MNA)
P32, MP33, MP36, MN31, MN34, M
Since N35) is directly connected to the amplifier and cannot adjust the channel length, the channel length is set to the same channel length L1 as the amplifier side to drive the amplifier.

Further, all the remaining transistors (MP31, MPA, MP34, M
The channel lengths of P35, MN32, MN33, and MNA (transistors within a circle in the drawing) are independently designed as L2 to minimize short channel effects and performance degradation of the amplifier due to a change in power supply voltage. it can.

Of course, transistors (MNA, MPA)
Should use a long channel length L2 at the same time, so a minimum design margin due to the voltage drop between the transistor gate and the source must be considered so that the transistor can operate in the saturation region even at the minimum possible voltage. .

In the bias circuit according to the present invention, the current repeaters (MP32, MP33, MN3
4, MN35), a MOS transistor having the same channel length L1 as the channel length of the transistor used in the amplifier is used, and the transistor (M
P31, MP34, MP35, MPA, MN32, MN
33, MN34, MN35), the channel length L2 longer than the channel length L1 is used to minimize the short channel effect even when the power supply voltage changes, and the change in current is minimized by the drain voltage. Thus, the current mismatch is reduced.

FIG. 4 shows a sample and hold amplifier to which the bias circuit according to the present invention is applied. The amplifier 41 includes the amplifier shown in FIG. 1 and its bias circuit. Here, the bias circuit according to the present invention is applied. For accurate sampling and holding operation of the analog signal, two non-overlapping clocks (Q1, Q2) are used as shown in FIGS. 5 (a) and 5 (b). At the phase of the first clock (Q1), the analog input signals are sampled into the two capacitors (C1, C2) through the transistors (M1-M4), and the transistors (M9, M10) connected to the capacitors (C1, C2). The first clock (Q1) is driven by a third clock (QIP) having a faster rolling edge than the first clock (Q1).
It is turned off earlier and goes into a high impedance mode, where the feedthrough error (feedthrou
gh error).

On the other hand, the transistors M5-M8 connected to the output terminal of the amplifier at the phase of the second clock Q2.
Accordingly, the capacitors (C1, C2) perform a holding operation of maintaining the input signal as output.

The simulation of the sample-and-hold circuit shown in FIG. 4 is performed using a 0.8 μm double-poly, double-metal n-well CMOS process variable. Channel length L used for amplifier 41
1 uses 1 μm to optimize the amplifier 41 to obtain sufficient voltage gain and bandwidth, and a relatively long channel length L2 defines the operating area of each transistor and the like used in the amplifier 41. At the same time, 2 μm, which is twice as large, is used so as to obtain a sufficient amplifier output range.

Transistors represented by circles (MP1, MP1
4, MP5, MPA, MN2, MN3, MN4, MN
The channel length of 5) can be longer than L2 to further reduce the current mismatch, but the size of the transistor used is smaller than the size of the additionally reduced current mismatch. Since the area of the entire chip increases rapidly, the length is set to 2 μm, which is a length sufficient to prove the effectiveness of the present invention.

The transistors (M2-M5) used for the complementary input pair of the operational amplifier in FIG. 1 have a minimum process length of 0.8 μm. A transistor (MN5) for supplying a bias voltage (BIAS3) to the amplifier shown in FIG.
Considering that the mismatch between the currents does not greatly affect the performance of the overall amplifier, to ensure that the output circuit of the amplifier can sufficiently operate in the saturation region,
Adjust the channel length to 1.2 μm.

Table 1 shows the specifications of all transistors and capacitors used in an embodiment of the sample and hold amplifier to which the present invention is applied. About 6 pF was used as a load at the output terminal, which is used when the sample-and-hold amplifier shown in FIG. 4 is applied to an actual system. This is a model of a parasitic capacitor. Although the specifications of the elements and the like shown in FIG. 1 including the channel lengths L1 and L2 of the used MOS transistors vary depending on the process used, the principle of the proposed path design technique is applied in the same manner.

[0051]

[Table 1]

As a result of experiments on this sample and hold amplifier circuit only when the power supply voltage was 3 V and 5 V, the change in current in the bias circuit for each case was summarized in Table 2. External input current IBS
When IN is applied at 50 μA, the conventional bias circuit as shown in FIG.
At 0% and 5V power supply voltage, the current increased to 80 μA at the maximum, indicating a current increase of 60%. On the other hand, in the bias circuit to which the method of adjusting the channel length according to the present invention proposed in FIG.
<5 V power supply voltage increases to 61 μA at the maximum, indicating a 20% current increase, so that it can be confirmed that the current mismatch is greatly reduced.

[0053]

[Table 2]

One of the specifications showing the performance of the designed SAH
One of them is ENOB (Effective Number Of Bits), which is an important index indicating the accuracy of the output maintained by the holding operation with respect to the analog input together with the SNR, and has the following relationship. ENOB = (SNR-1.76 dB) /6.02

Experiments were performed on each sample-and-hold amplifier circuit using an end input signal of 2 V _pp and a sampling clock of 42 MHz, and the output waveform of the sample-and-hold amplifier obtained through this experiment was converted to 128-pp.
SNR can be obtained by point FFT (Fast Fourier Transform), and ENOB is obtained through the above equation.

FIGS. 6A and 6B show the Nyquist of the sampling clock from the power supply voltages of 3 V and 5 V, respectively, for two sample-and-circuits using the existing bias circuit and the proposed bias circuit. (Nyquist)
FIG. 3 shows experimental results of ENOB for input signals of various frequencies up to a ratio. As shown in FIG. 6, the power supply voltage applied to the sample and hold circuit is changed from 3V to 5V.
, Regardless of the magnitude of the applied power supply voltage, even when the proposed bias circuit is used and when the conventional bias circuit is used, the ENOB at the 10-bit level which is almost the same is maintained. It can be confirmed that there is no performance loss in terms of degree.

However, in view of power consumption when the power supply voltage increases, the conventional sample-and-hold circuit using the bias circuit requires a bias current that is more than necessary due to a change in output impedance due to a short channel effect. However, since the sample and hold circuit using the proposed bias circuit is less affected by the output impedance, such a current mismatch is reduced, and consequently the power consumption is reduced. The rate of increase is reduced.

As can be seen from FIG. 7, when the power supply voltage is increased from 3 V to 5 V, the power consumption theoretically increases 5/3 times. However, when the conventional bias circuit is used, the power consumption increases. Attrition increased from 8.5 mW to 19.2 mW, an additional 35% over the expected 14.2 mW. On the other hand, when the proposed bias circuit is used, 15.0 mW is increased from 7.8 mW to 13.0 mW.
It can be seen that the increase rate is remarkably reduced because the increase is only 15% more than W.

[0059]

The above-described bias circuit according to the present invention is applicable to a bias circuit block for an analog / mixed mode circuit such as a CMOS operational amplifier, and is embodied in a mixed mode circuit using an amplifier. There is an effect that the cell library can be used with various power supply voltages while maintaining a constant performance. Also, there is an advantage that the designed circuit block can be variously applied to various semiconductor integrated circuits and systems without separate redesign.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a general complementary differential cascode (folded-cascode) amplifier using a MOS transistor or the like.

FIG. 2 is a conventional bias circuit diagram for supplying an operating current to the amplifier of FIG.

FIG. 3 is a bias circuit diagram of a CMOS amplifier according to the present invention.

FIG. 4 is a structural diagram of a sample and hold amplifier to which a bias circuit according to the present invention is applied.

5A and 5B are timing diagrams of non-superimposed clocks input to the transistors (M1), (M2), (M8), and (M9) in FIG. 4, respectively.

FIGS. 6A and 6B are graphs showing ENOB experimental results for input signals of various frequencies when using an existing bias circuit and a proposed bias circuit.

FIG. 7 is a graph showing a power consumption result with respect to a change in power supply voltage.

[Explanation of symbols]

 41: Amplifier.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Lee Seung-Isang 14-405 Rex Apartment, Namsan-dong, Yongsan-gu, Seoul, Republic of Korea Obayashi Apartment 207-606

Claims (6)

[Claims] 1. A bias circuit for a CMOS amplifier, comprising: a plurality of bias transistors for supplying a bias voltage to transistors and the like of the amplifier; and a plurality of current mirrors forming a current mirror for providing a current to the plurality of bias transistors. A bias circuit for a CMOS amplifier, comprising: a transistor; and a number of current mirror driving transistors for driving the number of current mirror transistors. 2. A bias circuit for a CMOS amplifier according to claim 1, wherein the channel length of said plurality of bias transistors is equal to the channel length of a transistor constituting the amplifier receiving the supply of the bias voltage. . 3. The CM according to claim 1, wherein a channel length of the plurality of current mirror transistors is longer than a channel length of the plurality of bias transistors.
OS amplifier bias circuit. 4. The CMOS according to claim 3, wherein the channel lengths of the plurality of current mirror transistors are long enough to prevent short channel effects.
Amplifier bias circuit. 5. A method of adjusting a channel length of a transistor constituting a bias circuit of a CMOS amplifier, comprising: determining a channel length of a number of bias transistors for supplying a bias voltage to the amplifier; The channel length of the multiple current mirror transistors constituting the current mirror that supplies the current to the multiple bias transistors and the like is the same as the channel length of the transistors and the like, and is formed from a channel longer than the channel length of the multiple bias transistors. A transistor and the like for driving the large number of current mirror transistors are separately formed, and a channel length thereof is formed to be the same as a channel length of the current mirror transistor. Transistor switches Channel length adjustment method. 6. The CMOS amplifier according to claim 5, wherein the channel lengths of the current mirror transistor and the like and the transistor for driving the transistor and the like are long enough to prevent a short channel effect. A method for adjusting the channel length of a MOS transistor in a bias circuit.