JPH11340330A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to bury a Cu wiring in a connection hole without increasing the contact resistance of the Cu wiring and diffusing Cu into an interlayer insulating film. A first interlayer insulating film (SiO ₂ film) 2 has a first C
A via hole 3 and a wiring groove 4 reaching the u wiring 1 are formed, and then a surface of the first interlayer insulating film 2 is irradiated with Ar ions to form a damaged layer 5 having O in dangling bonds. 1 Al is supplied to the surface of the interlayer insulating film 2 to selectively form a Cu diffusion barrier layer 6 made of a compound of Al and O on the surface of the interlayer insulating film. The second Cu wiring 8 is buried.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device characterized by a method of forming a diffusion barrier layer for suppressing diffusion of Si, particularly to a Si device.

[0002]

2. Description of the Related Art Cu wiring has the advantage of low RC delay due to low electrical resistance, and furthermore has high melting point and therefore has electromigration resistance (EM resistance).
It also has the advantage of high stress migration (SM resistance).

However, since Cu serves as a lifetime killer of a Si device and the diffusion rate of Cu in an oxide film is high, when Cu wiring is used, Cu diffuses into an interlayer insulating film and Cu Need to be reached.

Therefore, conventionally, as shown in FIG. 4, after forming a diffusion barrier layer 83 so as to cover the inner surface (bottom surface, side surface) of a via hole 82 opened in an interlayer insulating film 81,
The upper Cu wiring 85 that contacts the lower Cu wiring 84 was formed.

However, the method of forming such a diffusion barrier layer 83 has the following problems. That is, when an oxide film having a high barrier property (for example, an alumina film) is used as the diffusion barrier layer 83, the contact resistance between the lower Cu wiring 84 and the upper Cu wiring 85 due to the insulating property of the diffusion barrier layer 83 itself. And it becomes difficult to achieve conduction.

On the other hand, when a conductive oxide film is used as the diffusion barrier layer 83, a method using an oxygen gas as a film forming method (eg, a reactive physical vapor deposition method, a CVD method, etc.)
Is used, the surface of the lower layer Cu wiring 84 is oxidized, and thus, as in the case of using an oxide film having a high barrier property,
There is a problem that the contact resistance between the lower layer Cu wiring 84 and the upper layer Cu wiring 85 increases, and it becomes difficult to achieve conduction.

[0007]

As described above, when a Cu wiring is used, a diffusion barrier layer is formed so as to cover the inner surface of the via hole in order to prevent Cu from diffusing into the interlayer insulating film. , Upper layer C in contact with lower layer Cu wiring
u wiring was formed.

However, according to this conventional method, when an oxide film having a high barrier property is used as a diffusion barrier layer, it is difficult to use a conductive oxide film as a diffusion barrier layer due to the insulating properties of the diffusion barrier layer itself. Has a problem that the contact resistance between the lower Cu wiring and the upper Cu wiring is increased by oxidizing the surface of the lower Cu wiring because oxygen gas is used as the film forming method.

The present invention has been made in view of the above circumstances, and has as its object to increase the contact resistance of a Cu wiring and to prevent the diffusion of Cu into an interlayer insulating film without causing the Cu wiring to diffuse into the interlayer insulating film. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a Cu wiring can be embedded and formed.

[0010]

Means for Solving the Problems [0014] The gist of the present invention is to form a diffusion barrier layer on the surface of an interlayer insulating film by modifying the surface of the interlayer insulating film, and to form a diffusion barrier layer where no interlayer insulating film exists. It is to prevent a barrier layer from being formed.

That is, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1) includes a method of manufacturing a semiconductor device, comprising the steps of: Forming an interlayer insulating film containing the first constituent element of the first and second constituent elements constituting the Cu diffusion barrier layer, and Si bonded to the first constituent element; Forming a connection hole in the insulating film, the connecting hole being connected to the object; and forming the S on the surface of the interlayer insulating film.
i) dissociating the bond between the first constituent element and the first constituent element; and supplying the second constituent element to the surface of the interlayer insulating film, thereby selectively forming the diffusion barrier layer on the surface of the interlayer insulating film. And a step of burying and forming a Cu wiring electrically connected to the connected body in the connection hole.

In another method of manufacturing a semiconductor device according to the present invention (claim 2), a first Cu wiring electrically connected to the element is formed on a semiconductor substrate on which the element is integrated. Forming the first and second constituent elements constituting the Cu diffusion barrier layer and the interlayer insulating film containing Si bonded to the first constituent element by the first step; Forming on the semiconductor substrate so as to cover the Cu wiring, forming a connection hole connected to the first Cu wiring in the interlayer insulating film, and forming the Si and the first on the surface of the interlayer insulating film. Dissociating the bond with the constituent element, and selectively forming the diffusion barrier layer on the surface of the interlayer insulating film by supplying the second constituent element to the surface of the interlayer insulating film. And the first Cu wiring in the connection hole. Characterized by a step of the second Cu interconnection is buried for connecting.

Here, it is preferable to use, as the second constituent element, an element having a lower free energy of compound formation with the first constituent element than Si. Specifically, it is preferable to use O or N as the first constituent element and Al as the second constituent element.

Preferably, the bond between Si and the first constituent element is dissociated by irradiating the surface of the interlayer insulating film with ions. Here, it is preferable to use, as the ions, ions in an inert element plasma generated by turning an inert element gas into a plasma by RF power (claim 6).

In order to dissociate the bond between Si and the first constituent element, the energy of the ions is preferably 10 keV or more. In order to cause ions having energy necessary for dissociating the bond between Si and the first constituent element to collide with the interlayer insulating film, a bias voltage is applied to the semiconductor substrate to reduce the energy of the ions. It is preferable to control.

According to the present invention, after dissociating the bond between Si and the first constituent element on the surface of the interlayer insulating film, the second constituent element is supplied to the surface of the interlayer insulating film. The bonding between the first constituent element and the second constituent element selectively occurs on the surface of the interlayer insulating film, and a Cu diffusion barrier is selectively formed on the surface of the interlayer insulating film.

Therefore, according to the present invention, a diffusion barrier layer, which causes an increase in the contact resistance, is not formed on the surface of the body to be connected (the first Cu wiring). Cu wiring can be buried in the hole via the Cu diffusion barrier layer.

[0018]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a first Cu wiring 1 is formed on a silicon substrate (not shown). In the figure, the first Cu wiring 1 is a wiring of the first layer, but may be a wiring of any layer. The first Cu wiring 1 is electrically connected directly or via another wiring to an element integrated on the silicon substrate. Also, the first Cu wiring 1
Also, it is preferable to form them by the same method as the second Cu wiring described later.

[0020] Then, as shown in FIG. 6 (a), after forming the first interlayer insulating film 2 made of SiO ₂ so as to cover the first 1Cu wire 1 on a silicon substrate, a first interlayer insulating film 2 A via hole 3 having an opening diameter of 0.4 μm and an aspect ratio of 2 connected to the first Cu wiring 1 and a wiring groove 4 having a wiring width and depth of 0.4 μm are formed.

Next, as shown in FIG.
RF power of about 500 W is applied to a silicon substrate in an Ar gas atmosphere of × 10 ⁻³ Torr (approximately −
By applying 50 V), the damage layer 5 is formed, the natural oxide film formed on the surface of the first Cu wiring 1 is removed, and the surface of the first Cu wiring 1 is cleaned.

The damage layer 5 is formed by sputtering the surface of the first interlayer insulating film 2 with Ar ions, thereby dissociating the bond between oxygen and silicon on the surface of the first interlayer insulating film 2. Therefore, the damage layer 5
Is in a state where oxygen having dangling bonds is formed. The plasma damaged layer 5 'remains on the first Cu wiring 1, but is removed during the subsequent thermal history, so that there is no problem in resistance and EM resistance.

In order to dissociate the bond between oxygen and silicon, the energy of Ar ions is preferably 10 KeV or more. In order to obtain Ar ions having such energy, it is effective to apply a bias voltage to the silicon substrate while applying RF power to the plasma as in the present embodiment. With this method,
By controlling the bias voltage, Ar ions having desired energy can be easily obtained.

On the other hand, the natural oxide film and the like formed on the surface of the first Cu wiring 1 are removed by Ar ions passing through the via holes 3 to sputter the surface of the first Cu wiring 1. This can effectively prevent an increase in contact resistance between the first Cu wiring 1 and a second Cu wiring formed in a later step.

Next, as shown in FIG. 1C, the silicon substrate is introduced into the film forming chamber of the sputtering apparatus without breaking the vacuum,
Therefore, the surface of the Al target is sputtered with Ar ions to form an Al layer on the surfaces of the first interlayer insulating film 2 and the first Cu wiring 1.
By supplying (a main constituent element of the diffusion barrier layer), a 10 nm-thick C composed of a compound of Al and O such as alumina is used.
A diffusion barrier layer 6 of u is selectively formed on the surface of the first interlayer insulating film 2 and the first C
A thin Al film 7 is formed on the surface of the u wiring 1. At this time,
The degree of vacuum in the Al film forming chamber is, for example, 1 × 10 ⁻⁷ Torr, Ar
The pressure is set to, for example, 3 mTorr.

The reason that the diffusion barrier layer 6 is selectively formed on the surface of the first interlayer insulating film 2 is that oxygen having dangling bonds existing in the damaged layer 5 which is the surface of the first interlayer insulating film 2 is formed by A
The damage layer 5 reacts with the diffusion barrier layer 6
Because it changes to

Although a damage layer (not shown) is also formed on the surface of the first Cu wiring 1, the diffusion barrier layer 6 is not formed because the first Cu wiring 1 does not contain oxygen, and the Al film 7 is not formed.
Is formed.

As described above, according to the present embodiment, the first Cu
Oxygen that oxidizes the surface of the wiring 1 to cause an increase in contact resistance does not need to be supplied, thereby preventing the diffusion barrier layer 6 that causes an increase in contact resistance from being formed on the surface of the first Cu wiring 1. Only

An Al film 7 is formed on the surface of the first Cu wiring 1.
Is formed, but since the film thickness is sufficiently small, there is no problem of an increase in resistance. Next, as shown in FIG. 1D, a Cu film having a thickness of 400 nm is formed on the entire surface by a sputtering method in which the distance between the sputter target and the substrate is set long without heating the silicon substrate. The thickness is 40 by the sputtering method (reflow sputtering method) while heating to 40 ° C.
By forming a Cu film of 0 nm on the entire surface, the second C layer is formed so as to bury the inside of the via hole 3 and the wiring groove 4.
A Cu film 8 serving as a u wiring is formed on the entire surface.

Finally, as shown in FIG. 1E, the excess Cu film 8 outside the via hole 3 and the wiring groove 4 is removed by CM.
After the second Cu wiring 8 having a dual damascene structure is formed by polishing and removing by the P method, a second interlayer insulating film (passivation film) 9 is formed on the entire surface.

When an operation performance test was performed on the semiconductor device manufactured as described above, no operation abnormality due to Cu diffusion was found. When the total resistance of the via holes 3 and the wiring grooves 4 (contact portions) was measured using 10,000 via chains, no increase in resistance due to this process was observed. That is, even if Ar ion irradiation which was not performed by the conventional method was performed, no increase in resistance at the contact portion was observed.

Further, the silicon substrate taken out at the stage of the step of FIG.
SIMS analysis of the sample subjected to the heat treatment for 0 hours showed that the Cu concentration in the first interlayer insulating film 2 was below the detection limit. That is, it was confirmed that the diffusion barrier layer 6 formed by the method of the present embodiment had a sufficiently high ability to prevent the diffusion of Cu.

On the other hand, when the Cu wiring is formed without performing the process for forming the diffusion barrier layer 6, the semiconductor device does not operate normally, and the result of the SIMS analysis indicates that the first interlayer insulating film 2 It was confirmed that Cu was present therein.

Further, except that an insulating film having a laminated structure of SiO ₂ film (lower layer) / silicon nitride film (upper layer) is used as the first interlayer insulating film 2, the same as the one manufactured according to the same process as the present embodiment. Heat treatment was performed at 450 ° C. for 20 hours, and the evaluation was performed. As a result, it was confirmed that both the operating characteristics and the wiring resistance exhibited excellent results.

In this case, EDX results of cross-sectional TEM analysis revealed that aluminum nitride was selectively formed on the surface of the silicon nitride film and alumina was selectively formed on the surface of the SiO ₂ film.

Here, the surface of the silicon nitride film is coated with aluminum nitride.
The reason that the film was selectively formed is that the ion irradiation at the time of forming the damaged layer 5 dissociates the bond between Si and N on the surface of the silicon nitride film to form N having an unbonded bond. Al sputtered N with dangling bonds
This is because an Al nitride film is formed by combining with Al.

In this case, the surface of the first Cu wiring 1 is not nitrided by supplying nitrogen, which causes an increase in the contact resistance, thereby preventing the surface of the first Cu wiring 1 from being increased in the contact resistance. It is not necessary to form an Al nitride film (diffusion barrier layer).

In this embodiment, the case where Al is used as the main constituent element of the diffusion barrier layer 6 has been described.
Instead, it was confirmed that a similar effect can be obtained by using another element having a lower free energy of compound formation with oxygen than Si, in other words, using another element having a stronger bonding force with oxygen than Si.

Examples of such an element include Mg, T
i, V, Ta, Li, La, Nd, Sc, Y, Pr, H
o, Ba, Ce, Hf, Ce, Ba, Sr, Sm, T
h, Tb, Lu, Y, Ba, and Ca. (Second Embodiment) FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG.
1 are given the same reference numerals as in FIG. 1 and detailed description is omitted.

First, the steps up to the step of FIG. 1B of the first embodiment are performed, and then, as shown in FIG. 2A, Al is removed by sputtering using a long distance between the sputter target and the substrate. By depositing 50 nm, the diffusion barrier layer 6 is selectively formed on the surface of the first interlayer insulating film 2, and
An Al film 7 is formed on the entire surface.

In this embodiment, since the amount of Al deposited is large, not all of the Al supplied to the surface of the first interlayer insulating film 2 can serve as the diffusion barrier layer 6. An Al film 7 is formed.

Next, as shown in FIG. 2B, a second Cu is formed so as to fill the via holes 3 and the wiring grooves 4.
A 50 nm-thick Cu film 8 serving as a wiring is formed on the entire surface by using a plating method.

At this time, since the Al film 7 formed on the entire surface serves as a seed for plating, a Cu film 8 having a good shape can be easily formed inside the via hole 3 and the wiring groove 4. Finally, as shown in FIG.
The second Cu wiring 8 having a dual damascene structure is formed by polishing and removing the excess Cu film 8 outside the wiring groove 4 by the CMP method, and then the second interlayer insulating film 9 is formed on the entire surface.

When the semiconductor device manufactured as described above was evaluated, it was confirmed that the same effects as those of the first embodiment were obtained. On the other hand, it was confirmed that the semiconductor device manufactured by the same method as that of the present embodiment after the step of forming the Al film 7 without performing the process for forming the diffusion barrier layer 6 does not operate normally.

Further, a modification similar to that of the first embodiment is possible. Further, the following modifications are possible. That is, after the step of FIG. 2A, as shown in FIG. 3, the first interlayer insulating film 2 outside the via hole 3 and the wiring groove 4 is formed.
After the Al film 7 formed on the surface of the substrate is removed by CMP or wet etching, a Cu film 8 is formed by electroless plating.

At this time, since the Al film 7 exists only on the inner surface of the via hole 3 and the wiring groove 4, the Cu film 8 is selectively formed in the via hole 3 and the wiring groove 4 with a smooth shape. . Therefore, via hole 3
In addition, the effect of eliminating the step of removing the surplus Cu film 8 outside the wiring groove 4 or simplifying the step of removing the Cu film 8 can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the connection hole is a via hole and a wiring groove connected to the via hole has been described, but the present invention is also effective when only the via hole or only the wiring groove is used.

The method of forming the Cu film is not limited to the sputtering method or the plating method, but may be a CVD method or a method combining these methods. Further, the present invention relates to C
The present invention can be applied to any semiconductor device using u wiring, regardless of the type of semiconductor device such as LSI or LCD.

In this embodiment, the case where the connected object is a Cu wiring has been described. However, even when the connected object is, for example, an electrode having a laminated structure of a polycrystalline silicon film (lower layer) / W film (upper layer). The invention is valid. In addition, various modifications can be made without departing from the scope of the present invention.

[0050]

As described in detail above, according to the present invention, by forming a diffusion barrier layer by modifying the surface of an interlayer insulating film, a connected object (first Cu) having no interlayer insulating film can be formed. It is not necessary to form a diffusion barrier layer, which is a cause of an increase in contact resistance, on the surface of the (wiring), so that a Cu wiring can be buried in the connection hole without causing an increase in contact resistance. .

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining a modification of the second embodiment;

FIG. 4 is a cross-sectional view for explaining a conventional problem.

[Explanation of symbols]

1 ... The 1Cu wiring 2 ... first interlayer insulating film (SiO ₂ film) 3 ... via hole 4 ... wiring groove 5 ... damaged layer 6 ... diffusion barrier layer 7 ... Al film 8 ... second 2Cu wiring 9 ... second interlayer insulating film

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yukio Takahagi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Yokohama Office

Claims (6)

[Claims] 1. A first structure of a first and second constituent elements constituting a diffusion barrier layer of Cu on a semiconductor substrate having a connected body formed thereon so as to cover the connected body. element,
And a step of forming an interlayer insulating film containing Si bonded to the first constituent element; a step of forming a connection hole in the interlayer insulating film that is connected to the object; and a step of forming the Si on the surface of the interlayer insulating film. Dissociating the bond with the first constituent element; and supplying the second constituent element to the surface of the interlayer insulating film, thereby selectively disposing the diffusion barrier layer on the surface of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of burying and forming a Cu wiring electrically connected to the connected body in the connection hole. 2. A step of forming, on a semiconductor substrate on which an element is integratedly formed, a first Cu wiring electrically connected to the element, a first and a second arrangement forming a Cu diffusion barrier layer Forming a first constituent element of the elements and an interlayer insulating film containing Si bonded to the first constituent element on the semiconductor substrate so as to cover the first Cu wiring; Forming a connection hole connected to the first Cu wiring in the insulating film; dissociating the bond between the Si and the first constituent element on the surface of the interlayer insulating film; Selectively forming the diffusion barrier layer on the surface of the interlayer insulating film by supplying the second constituent element; and electrically connecting the first Cu wiring in the connection hole. Burying and forming a second Cu wiring. The method of manufacturing a semiconductor device according to claim Rukoto. 3. The method according to claim 1, wherein the second constituent element is an element having a lower free energy of compound formation with the first constituent element than the Si. A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein O or N is used as said first constituent element, and Al is used as said second constituent element. 5. The semiconductor according to claim 1, wherein a bond between said Si and said first constituent element is dissociated by irradiating ions to a surface of said interlayer insulating film. Device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 5, wherein ions in the inert element plasma generated by turning an inert element gas into plasma by RF power are used as the ions.