JPH1141223A - Data reproducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To early take bit synchronism to a degraded input signal. SOLUTION: When the repetition of bits in the input signal is detected by an S/P converter 6 for sampling the input signal with the rising edge of a reproducing clock provided by a digital control oscillator 3 without detecting the bit repetition of the input signal through an S/P converter 5 for sampling the input signal with the falling edge of the same reproducing clock, the reproducing clock is inverted by controlling the digital control oscillator 3 so that a normal bit synchronizing signal can be provided from the S/ P converter 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing circuit for reproducing input data by using a reproduced clock signal generated from an input bit synchronization signal.

[0002]

2. Description of the Related Art A selective calling signal is usually called POCSAG (Post Off
It is transmitted and received according to a digital signal protocol called ice Code Standardization Advisory Group). This selective calling signal is described in the document "POCSAG wireless paging system RCR STD-42" (Radio System Development Center, formulated on November 10, 1994).

In the POCSAG system, before transmitting an information signal, a repetition of at least 576 bits of 1,0 at a transmission bit rate is transmitted for bit synchronization. This is called a preamble. Then, an information signal is transmitted following the preamble. In a normal selective calling signal receiver (pager or the like), bit synchronization is performed while receiving this preamble.

FIG. 5 is a diagram showing a conventional data reproducing circuit for reproducing data with the above-mentioned bit synchronization. This circuit compares a phase of an input signal with a phase of an output clock (reproduced clock) of a digitally controlled oscillator 3 by a phase comparator 1 and passes the result through a loop filter 2 to a PLL loop so as to be input to the digitally controlled oscillator 3. It consists of. Then, the reproduced clock obtained by the digitally controlled oscillator 3 is input to an FF (flip-flop) circuit 4, and the input signal is sampled at the falling edge of the reproduced clock to reproduce the data. In this conventional data reproducing circuit, as shown in FIG. 6, if the duty of the input signal is 50%, the preamble can always be reproduced.

[0005]

However, in a selective call receiver, a preamble having a duty of 25% to 75% must be recognized as a preamble. However, as shown in FIG. If the reception is not possible due to lack of (shaded portion) and the duty is 50%, the preamble may not be able to be reproduced at the initial stage when synchronization is not fully achieved. This is because the timing at which data is taken in the FF circuit 4 is delayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to achieve high-speed data reproduction using both the rising edge and the falling edge of a reproduction clock. That is.

[0007]

According to a first aspect of the present invention, there is provided a data reproducing circuit for reproducing a digital signal including a synchronizing signal for bit synchronization comprising at least two repetitions of 1,0. A clock recovery means for generating a recovered clock having the same bit period as the synchronization signal; and a first means for sampling an input signal at one of rising and falling edges of the recovered clock.
Sampling means, a second sampling means for sampling an input signal at the other edge of the rising or falling edge of the reproduction clock, and a first sampling means for repeating the input signal by two or more bits of 1,0. And a determination means for controlling the clock recovery means to invert the recovered clock when the second sampling means detects the repetition, and the output data of the first sampling means. Is set as reproduction data. In a second aspect based on the first aspect, the clock recovery means is controlled by the determination means only during a period during which the synchronization signal is received, and thereafter holds the polarity of the recovered clock. According to a third aspect of the present invention, in a data reproduction circuit for reproducing a digital signal including a synchronization signal for bit synchronization consisting of at least two or more repetitions of 1, 0, a playback clock having the same bit period as the synchronization signal is generated. Clock recovery means, first sampling means for sampling an input signal at one rising or falling edge of the recovered clock, and second sampling for sampling the input signal at the other rising or falling edge of the recovered clock Sampling means, and the first and second sampling means,
And selecting means for selecting, as reproduction data, an output signal of the sampling means on the side where repetition of 1, 0 of 2 bits or more of the input signal is detected. 4th
According to a third aspect of the present invention, in the third aspect, the selection means operates only during the reception period of the synchronization signal, and thereafter keeps the selection state.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram of a data reproducing circuit according to a first embodiment of the present invention. The same components as those shown in FIG. 5 described above are denoted by the same reference numerals. Reference numerals 5 and 6 denote S / P (serial / parallel) converters for inputting serial data and outputting 3-bit parallel data. One of the S / P converters 5 receives an input signal at the falling edge of the reproduction clock. And sample the other S / P
The converter 6 samples the input signal at the rising edge of the recovered clock. Reference numeral 7 denotes an inverter for inverting the reproduction clock. Reference numeral 8 denotes a decision unit for comparing and comparing the 3-bit data of the S / P conversion circuits 5 and 6, and 9 denotes an AND circuit which opens the gate only when the preamble is received. You are typing. Note that the reproduced data is supplied to an S / P converter 5 which samples the input signal at the falling edge of the reproduced clock.
From the output of the first bit.

The operation will be described below with reference to FIG. The input signal is the same as the input signal shown in FIG. At times t1, t3, and t5 of the falling edge of the recovered clock obtained by the digital control transmitter 3, S / S
The sampling data of the P converter 5 is 0,0,0,
Time t2, t4, t of rising edge of reproduction clock
6, the sampling data of the S / P converter 6 is 1,
0,1.

As described above, S on the side from which reproduction data is taken out
When the bit string of the output data of the / P converter 5 is “000” and the bit string of the output data of the other S / P converter 6 is “101”, the determiner 8 sets “1” to the AND circuit 9.
To the digitally controlled oscillator 3. Therefore, the phase of the reproduced clock output from the digitally controlled oscillator 3 is inverted.

After the reproduction clock is inverted, the preamble can be normally reproduced from the first bit terminal of the S / P converter 5. Note that the digital control oscillator 3 is not affected by the determination result of the determiner 8 after the reception of the preamble since the AND circuit 9 closes the gate except during the reception of the preamble.

FIG. 3 is a diagram showing the contents of the judgment by the judgment unit 8. The determiner 8 outputs “000” to the output of the S / P converter 5 that captures data at the falling edge of the recovered clock.
Alternatively, when the same data continues as in “111” (the preamble cannot be received), the same as “101” or “010” is output to the output of the S / P converter 6 that captures the data at the rising edge of the reproduction clock. When data does not continue (preamble is received), it operates to output “1” and invert the reproduction clock. Also, S /
When the output data of the P converter 5 has a change in even one bit out of three bits, the preamble reception is enabled and the S / S
Regardless of the data of the P converter 6, the determiner 8 outputs "0".

As described above, even when the preamble portion of the input signal is deteriorated due to noise or the like and cannot be received at the duty of 50%, the bit synchronization signal synchronized with the preamble is reproduced early after the start of the reception of the input signal. can do.

[Second Embodiment] FIG. 4 is a diagram showing a data reproducing circuit according to a second embodiment. Here, FIG.
Is newly provided for the circuit shown in (1), and the selection unit 10 selects the output of the first bit of the S / P converter 5 or the S / P converter 6 and outputs it as reproduction data. Like that. In the decision unit 8, the selection unit 10 selects the bit string of “101” or “010”, that is, the output of the S / P converter on the side from which the preamble is obtained.
The selector 10 is controlled. Note that the digitally controlled oscillator 3 is not controlled. After the preamble reception is completed, the selection unit 10 holds the selected state.

Therefore, even in this embodiment, even if the preamble portion of the input signal is deteriorated due to noise or the like and cannot be received at a duty of 50%, it is synchronized with the preamble early after the start of the reception of the input signal. The bit synchronization signal can be reproduced.

[Other Embodiments] In the first embodiment, the output of the first bit of the S / P converter 5 is extracted as reproduction data. When the output of the first bit is used as reproduction data, the output of the S / P converter 6 is “000” or “111” and the S / P
When the output of the P converter 5 is “101” or “010”, the reproduced clock may be inverted.

The output data of the S / P converters 5 and 6 is not limited to 3 bits. For example, 4
In the case of bits, in the first embodiment, when one S / P converter 5 cannot detect the bit string of “1010” or “0101”, the other S / P converter 6
When this is detected, the recovered clock may be inverted. Similarly, no matter how many bits the output bit lengths of the S / P converters 5 and 6 are 2 bits or more, one of the S / P converters 5 may be “1010...” Or “0101.
. ”, The other S /
When the P converter 6 detects this, the reproduced clock may be inverted.

Further, one S / P converter 5 may sample the input signal at the rising edge of the reproduction clock, and the other S / P converter 6 may sample the input signal at the rising edge.

In the above description, the case where a call signal of the POCSAG system is received has been described.
The present invention can be applied to all devices that reproduce a signal including a bit synchronization signal consisting of repetitions of “0”.

[0020]

As described above, according to the present invention, even if the input signal is deteriorated due to noise or the like, the bit synchronization signal can be reproduced early after the start of the reception of the input signal, that is, at high speed. There are advantages.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data reproducing circuit according to a first embodiment.

FIG. 2 is an operation waveform diagram of the data reproduction circuit.

FIG. 3 is an explanatory diagram of judgment contents of a judgment unit of the data reproduction circuit.

FIG. 4 is a block diagram of a data reproduction circuit according to a second embodiment.

FIG. 5 is a block diagram of a conventional data reproducing circuit.

FIG. 6 is an operation waveform diagram at the time of receiving an input signal with a duty of 50% of a conventional data reproducing circuit.

FIG. 7 is an operation waveform diagram of the conventional data reproduction circuit when a deteriorated input signal is received.

Claims (4)

[Claims] 1. A data reproducing circuit for reproducing a digital signal including a synchronizing signal for bit synchronization comprising at least two or more repetitions of 1,0, wherein a clock for generating a reproducing clock having the same bit period as the synchronizing signal is provided. Reproduction means; first sampling means for sampling an input signal at one rising or falling edge of the reproduction clock; and second sampling for sampling the input signal at the other rising or falling edge of the reproduction clock. When the first sampling means does not detect the repetition of 1, 2 or more bits of the input signal and the second sampling means detects the repetition, the first sampling means controls the clock recovery means. Determining means for inverting the reproduced clock by using the first sampler. Data recovery circuit, characterized in that the reproduction data output data of the ring means. 2. The data reproducing circuit according to claim 1, wherein said clock reproducing means is controlled by said judging means only during a period during which said synchronization signal is received, and thereafter retains the polarity of a reproduced clock. 3. A data reproducing circuit for reproducing a digital signal including a synchronizing signal for bit synchronization comprising at least two repetitions of 1,0, wherein a clock for generating a reproducing clock having the same bit period as the synchronizing signal is provided. Reproducing means; first sampling means for sampling an input signal at one rising or falling edge of the reproduced clock; and second sampling for sampling an input signal at the other rising or falling edge of the reproduced clock. Means for selecting, as reproduction data, an output signal of the sampling means of the first and second sampling means that detects repetition of 1 or 0 of 2 bits or more of the input signal as reproduction data. A data reproducing circuit. 4. The data reproducing circuit according to claim 3, wherein said selecting means operates only during the reception period of said synchronization signal, and thereafter keeps a selected state.