JPH1153296A - Data output synchronous clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data output synchronous clock generator which supplies a clock that has a little attenuation of a signal and is synchronized with many devices. SOLUTION: A data clock which is generated by an synchronous DRAM device 14d that is arranged at the farthest end from a memory controller 12 is synchronizes with a command clock that is sent from a clock generator 11 to a command clock signal line 21a and is supplied front an output pin 22d to synchronous DRAM devices 14a to 14d through a data clock outputting signal line 23a. Data which are outputted from each of the devices 14a to 14d are synchronized with the data clock, transmitted through a data bus 25 from data input-output lines 24a to 24d in the same direction of the data clock and sent to the controller 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output synchronous clock generator, and more particularly to a data output synchronous clock generator used for a semiconductor memory having a synchronous clock and a module for writing and reading.

[0002]

2. Description of the Related Art Conventionally, in a synchronous semiconductor memory device using a dynamic random access memory (DRAM), various devices for high-speed operation have been devised. However, the system clock is 100MHz
In order to cope with a high-speed system exceeding (10 ns) or more, the conventional access time to the DRAM itself is a bottleneck, which hinders the performance improvement of the system. As a countermeasure, there is a synchronous semiconductor memory device that synchronizes with an external clock, and as one of them, there is a means for modularizing a DRAM.

In this technique, a plurality of DRAMs are modularized, and a circuit for controlling the DRAMs is provided.
The access to a plurality of DRAMs with a clock generated from the DRAM and the acquisition of data from an arbitrary DRAM are repeated to achieve a high speed operation.

As a system having the above-mentioned modularized synchronous semiconductor memory device, a synchronous bus system having a configuration as shown in FIG. 4 is conventionally known. The synchronous bus system 100 is disclosed in U.S. Pat. No. 5,432,823, and includes a master device 102, a slave device 104, and a clock signal source 132.

[0005] The synchronous bus system 100 is a bus system that eliminates the delay of clock data, and a synchronized clock is distributed inside each device. The master device 102 is connected to the slave device 104 via the data bus 120. Master device 10
2 is placed near the turn of the clock line. The slave device 104 is a high-speed DRAM and has an input / output (I / O) port.

When the master device 102 outputs access information and starts data exchange, the slave device 104
Receives the above access information and receives the slave device 104
And the type of access is determined. On the other hand, the clock supply system 130 has a mechanism for removing skew occurring between the clock and the data signal.

The clock supply system 130 includes a clock signal source 132 and a clock signal line 134. The clock signal source 132 is provided outside the master device 102 and the slave device 104 and is independent of them.
The clock signal source 132 is connected to an end of the clock signal line 134. The clock signal line 134 sends the clock generated by the clock signal source 132 to all devices on the synchronous bus system 100. Clock signal line 13
4 starts at the end of the data bus 120 and points 1
There are two components, a first component 136 up to 37 and a second component 138 starting at point 137 and going to the end of the data bus 120.

A clock signal is supplied from a clock signal source 132 via a first component 136 to the master device 102.
Head for. The clock signal at this time is transmitted in the same direction as the direction in which the data signal is sent from slave device 104 to master device 102. Master device 10
2 uses a clock signal passed through the first component 136, and is synchronized with this clock signal to
Receives the data sent to 0.

Next, the clock signal goes from the point 137 to the direction opposite to the direction of the data bus 120 via the second component 138. The data signal is the master device 10
2 to the slave device 104.
Slave device 104 receives the clock signal via second component 138. While the clock signal from its component 138 is active, the slave device 104
Receives a data signal from the master device 102 toward the slave device 104.

[0010]

In the above-mentioned synchronous bus system 100, since a single clock signal reciprocates between the master device 102 and the slave device 104, the clock signal return path increases as the load on the clock signal increases. Becomes extremely large, which is not suitable for the configuration of a device system having multiple modules.

[0011] The present invention has been made in view of the above points,
It is an object of the present invention to provide a data output synchronous clock generator capable of supplying a clock synchronized with data to many devices with little signal attenuation.

[0012]

According to the present invention, in order to achieve the above object, the present invention is commonly connected to a data bus, and at least receives data input via a data bus and a data input / output line based on a command clock. A plurality of synchronous random access memories for writing and reading data to a data bus via a data input / output line based on a data clock, and a command clock are generated and supplied to the plurality of random access memories. A memory controller for generating data synchronized with a command clock and supplying the data in parallel to a plurality of random access memories via a data bus and a data input / output line; and a memory among the plurality of random access memories. With random access memory located farthest from the controller, The data clock generated and output in synchronization with the command clock is input to the memory controller and branched to be input to each of the plurality of random access memories, and the plurality of random access memories are output in synchronization with the data clock. And control means for outputting the data read from the data input / output line via a data input / output line and a data bus.

According to the present invention, the data generated and output in synchronization with the command clock by the random access memory located at the farthest position from the memory controller among the plurality of random access memories. A clock is input to each of a plurality of random access memories, and data is read from the plurality of random access memories in synchronization with a data clock and sent to a memory controller. And the wiring length of the data clock can be reduced to about 1/2 of the conventional length.

Further, according to the present invention, a data clock generator is arranged at a position farthest from a memory controller than the plurality of synchronous random access memories described above, and a command clock is generated by the data clock generator. The data clock generated and output in synchronization with
The data is input to the memory controller and branched to be input to each of the plurality of random access memories, and the data read from the plurality of random access memories in synchronization with the data clock is transferred to a data input / output line and a data bus. Is output via the.

According to the present invention, a data clock generated and output by a data clock generator in synchronization with a command clock is input to a plurality of random access memories, and a plurality of random access memories are synchronized with the data clock. Since data is read from the access memory and sent to the memory controller, the clock line does not turn back as in the conventional device, and the wiring length of the data clock can be reduced to about 1/2 of the conventional length.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a data output synchronous clock generator according to the present invention. The data output synchronous clock generator 10 of this embodiment includes a memory controller 12 having a clock generator 11 for generating a clock, and a memory module 13.

The memory module 13 includes synchronous DRAM devices 14a, 14b, 14c and 14d having a chip ID, a command clock signal line 21a for outputting a clock from the clock generator 11, and a command clock signal line 21a. Synchronous DR clock
A command clock input line 21b for inputting to the AM devices 14a, 14b, 14c and 14d, and a chip I located at the farthest end with respect to the memory controller 12.
An output signal line 2 for transmitting the data clock output from the data clock output pin 22d of the synchronous DRAM device 14d whose D is 0 to the memory controller 12.
3a and the data clock on the output signal line 23a are synchronized with the synchronous DRAM devices 14a, 14b, 14c and 14d.
, The data clock input pins 22a, 22b and 22c of the synchronous DRAM devices 14a, 14b and 14c, the memory controller 12 and the synchronous DRAM devices 14a and 14c,
Data input / output lines 24a, 24b, 24c and 24d for exchanging data between 4b, 14c and 14d
And a data bus 25.

Next, this data clock output pin 22
d and data clock input pins 22a, 22b and 22
The operation of the data output synchronous clock generator 10 having a different c will be described. In synchronization with the command clock sent from the clock generator 11 to the command clock signal line 21a, the data output from the memory controller 12 is transmitted through the data bus 25 in the same direction as the command clock, so that the synchronous DRAM devices 14a, 14
b, 14c and 14d are connected to the data input / output lines 24a, 24
b, 24c and 24d. Note that the above command clock is supplied to the command clock input line 21b.
Through the synchronous DRAM devices 14a, 14b, 14
c and 14d.

In synchronization with the command clock sent from the clock generator 11 to the command clock signal line 21a, the data clock generated by the synchronous DRAM device 14d located farthest from the memory controller 12 is generated. Is output from the output pin 22d onto the data clock output signal line 23a. The data clock on the data clock output signal line 23a is:
From the data clock input line 23b to the memory module 13
All of the above synchronous DRAM devices 14a, 14b,
14c and 14d.

In synchronization with the data clock, a synchronous D
The data output from each of the RAM devices 14a, 14b, 14c and 14d is stored in a data input / output line 24a,
4b, 24c and 24d, the data bus 25 is transmitted in the same direction as the data clock,
Sent to 2.

The data clock supplied at this time is only from the synchronous DRAM 14d which is the farthest end device, and the data clock output pins 22a, 22b and 22c of the other synchronous DRAMs 14a to 14c are input / output. It is set to high impedance in order to suppress.

According to this embodiment, the synchronous DR located farthest from the memory controller 12
The data clock generated by the AM device 14d is transmitted to all the synchronous DRAMs on the memory module 13.
To devices 14a, 14b, 14c and 14d,
Since the data read from the synchronous DRAM devices 14a, 14b, 14c, and 14d is sent to the memory controller 12 in synchronization with the data clock, the wiring length of the data clock output signal line 23a is set to be equal to the length of the return of the clock line. About 1/2 compared to a certain conventional device
Therefore, signal attenuation can be suppressed to a small level.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the data output synchronous clock generator according to the present invention. The data output synchronous clock generator 40 of this embodiment
It comprises a memory controller 42 having a clock generator 41 for generating a clock, and a memory module 43.

The memory module 43 includes synchronous DRAM devices 44a, 44b, 44c and 44d each having a chip ID, a command clock signal line 51a for outputting a clock from the clock generator 41, and a command clock signal line 51a. Synchronous DR clock
A command clock input line 51b for inputting to the AM devices 44a, 44b, 44c and 44d, and a synchronous DR disposed farthest from the memory controller 42
Data clock input / output pin 52d of AM device 14d
Data clock output from the memory controller 4
2 and an output signal line 53
a synchronous DRAM device 44
a, 44b, 44c and 44d, a data clock input line 53b, and a synchronous DRAM device 44.
a, 44b and 44c data clock input / output pins 52
a, 52b and 52c, the memory controller 42 and the synchronous DRAM devices 44a, 44b, 44c and 44
Data input / output line 5 for exchanging data between d
4a, 54b, 54c and 54d and data bus 55
Consists of

Next, this data clock output pin 52
d and data clock input pins 52a, 52b and 52
The operation of the data output synchronous clock generator 40 having common c will be described. In synchronization with the command clock sent from the clock generator 41 to the command clock signal line 51a, the data output from the memory controller 42 is transmitted through the data bus 55 in the same direction as the command clock, so that the synchronous DRAM devices 44a, 44
b, 44c and 44d are connected to the data input / output lines 54a, 54
b, 54c and 54d. Note that the above command clock is supplied to the command clock input line 51b.
Through the synchronous DRAM devices 44a, 44b, 44
c and 44d.

In synchronization with the command clock sent from the clock generator 41 to the command clock signal line 51a, a data clock generated by the synchronous DRAM device 44d disposed farthest from the memory controller 42 is generated. Is output from the input / output pin 52d to the data clock output signal line 53a. The data clock on the data clock output signal line 53a is supplied from the data clock input line 53b to the synchronous DRAM devices 44a, 44b, 44c via the input / output pins 52a, 52b, 52c on the memory module 43.

In synchronization with the data clock, a synchronous D
The data output from each of the RAM devices 44a, 44b, 44c and 44d is applied to data input / output lines 54a,
4b, 54c and 54d, the data bus 55 is transmitted in the same direction as the data clock,
Sent to 2.

At this time, the input / output pin 52d of the synchronous DRAM device 14d, which is the farthest end device, functions as a data clock output pin, and the synchronous DRAM device 14d internally transfers the data clock. Therefore, the farthest end synchronous DRAM device 44
In d, the internal clock adjusted by the device 44d itself is used. The second embodiment also has the same effects as the first embodiment.

The difference between the first embodiment and the second embodiment is that in the first embodiment, the synchronous DR
The input pin and the output pin of the data clock of the AM device are separately provided, and the data clock output pin uses only the farthest end synchronous DRAM device (14d in FIG. 1) and the other synchronous DRAM devices (14a to 14a in FIG. 1). 14c), the data clock output pins are set to high impedance, respectively, whereas in the second embodiment, the input / output pins of all the synchronous DRAM devices are shared, and the farthest end synchronous DRAM is used. The point is that only the device (44d in FIG. 2) adjusts the data clock internally instead of inputting it from the outside via the input / output pins.

For this reason, in the second embodiment, it is necessary to provide an adjustment circuit internally, and the circuit area increases accordingly. On the other hand, in the first embodiment, the device
Although the adjustment circuit as in the embodiment is not necessary, it is necessary to devise a module for fixing the data clock output pin to high impedance except for the farthest end device when the number of pins is increased.

Next, a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing a third embodiment of the data output synchronous clock generator according to the present invention. The data output synchronous clock generator 70 of this embodiment
It comprises a memory controller 72 having a clock generator 71 for generating a clock, and a memory module 73.

The memory module 73 is a synchronous DRAM
A device 74a, 74b, 74c, and 74d, a data clock generator 75 disposed farthest from the memory controller 72, a command clock signal line 81a for outputting a clock from the clock generator 71, and a command clock The clock on the signal line 81a is transferred to the synchronous DRAM devices 74a, 74b, 74.
c and 74d, a command clock input line 81b, a data clock output pin 82 of the data clock generator 75, and a data clock output from the data clock output pin 82.
Signal line 83a for transmission to the output signal line 83a
The above data clock is transmitted to the synchronous DRAM device 74a,
A data clock input line 83b for inputting to the synchronous DRAM devices 74a, 74b, 74c and 74d;
Data clock input pins 8 for 74b, 74c and 74d
4a, 84b, 84c and 84d, a memory controller 72 and a synchronous DRAM device 74a, 74b, 74
It comprises data input / output lines 85a, 85b, 85c and 85d for exchanging data between c and 74d, and a data bus 86.

Next, the operation of the data output synchronous clock generator 70 will be described. In synchronization with the command clock sent from the clock generator 71 to the command clock signal line 81a, the data output from the memory controller 72 is transmitted through the data bus 86 in the same direction as the command clock, and the synchronous DRAM devices 74a, 74b, The data is input to the data input / output lines 85a, 85b, 85c, and 85d. The above command clock is supplied to the synchronous DRAM device 74 via the command clock input line 81b.
a, 74b, 74c and 74d, and to a data clock generator 75.

The data clock generator 75 is constituted by a phase locked loop (PLL) circuit or a buffer circuit. When the above-mentioned command clock is input, the data clock generator 75 generates a data clock synchronized with the command clock, and outputs the data clock. Data clock output pin 82
And outputs it to the data clock output signal line 83a. The data clock on the output signal line 83a is transmitted from the data clock input pins 82a, 82b, 82c and 82d via the data clock input signal line 83b of another device to all the synchronous D lines on the memory module 73.
It is supplied in parallel to RAM devices 74a, 74b, 74c and 74d.

Synchronous DRAM devices 74a, 74b,
74c and 74d output data in synchronization with the input data clock. This data is transmitted from data input / output lines 85a, 85b, 85c and 85d to data bus 86.
Is transmitted in the same direction as the data clock, and sent to the memory controller 72.

According to this embodiment, the data clock generated by the data clock generator 75 disposed farthest from the memory controller 72 is used for all the synchronous DRAMs on the memory module 73.
To devices 74a, 74b, 74c and 74d,
Since the data read from the synchronous DRAM devices 74a, 74b, 74c, and 74d is sent to the memory controller 72 in synchronization with the data clock, the wiring length of the data clock output signal line 83a is set to the value of the clock line wrap. About 1/2 compared to a certain conventional device
Therefore, signal attenuation can be suppressed to a small level.

[0037]

As described above, according to the present invention,
Of the plurality of random access memories, the data clock generated and output in synchronization with the command clock by the random access memory or the data clock generator arranged at the farthest end position with respect to the memory controller, By inputting data to a plurality of random access memories and reading data from the plurality of random access memories in synchronization with the data clock and sending the data to the memory controller, clock line wrapping unlike the conventional device is eliminated. Therefore, the wiring length of the data clock can be reduced to about 1/2 of the conventional length, and therefore, the attenuation of the clock signal is smaller than that of the conventional one, and the present invention can be applied to a memory module having more devices than the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of an example of the related art.

[Explanation of symbols]

10, 40, 70 Data output synchronous clock generator 11, 41, 71 Clock generator 12, 42, 72 Memory controller 13, 43, 73 Memory module 14a-14d, 44a-44d, 74a-74d Synchronous dynamic random access・ Memory (DR
AM) 21a, 51a, 81a Command clock signal line 21b, 51b, 81b Command clock input line 22a, 22b, 22c Data clock input pin 22d Data clock output pin 23a, 53a, 83a Data clock output signal line 23b, 53b, 83b Data Clock input signal line 24a-24d, 54a-54d, 85a-85d Data input / output line 25, 55, 86 Data bus 52a-52d Data clock input / output pin 75 Data clock generator 82 Data clock output pin 84a-84d Data clock input pin

Claims (4)

[Claims] A data bus for writing data input through the data bus and a data input / output line based on at least a command clock;
A plurality of synchronous random access memories for reading data to the data bus via the data input / output lines based on a data clock, and generating the command clock and supplying the command clock to the plurality of random access memories A memory controller that generates data synchronized with the command clock and supplies the data in parallel to the plurality of random access memories via the data bus and the data input / output lines; The data clock generated and output in synchronization with the command clock is input to the memory controller and branched by a random access memory arranged at a position farthest from the memory controller among the memories. To each of the plurality of random access memories. Control means for outputting data read from the plurality of random access memories in synchronization with the data clock via the data input / output lines and the data bus. Synchronous clock generator. 2. A random access memory, which is located at a farthest position from the memory controller among the plurality of random access memories, has a data clock output pin for outputting the data clock. And the remaining random access memory among the plurality of random access memories has a data clock input pin, and the control means controls the data output from the data clock output pin. 2. The data output synchronization according to claim 1, wherein a clock is supplied to each of the plurality of random access memories via a data clock input signal line, and each of the data clock input pins is set to high impedance. Clock generator. 3. The random access memory according to claim 1, wherein each of said plurality of random access memories has an input / output pin for a data clock, and said control means controls said memory controller among said plurality of random access memories. The data clock output from the data clock input / output pin of the random access memory arranged at the farthest end position is input to the data clock input / output pin of the remaining random access memory, and 2. The data output synchronous clock generator according to claim 1, wherein the random access memory arranged at the far end position uses an internal clock output to its own data clock input / output pin as the data clock. 4. A data bus, which is commonly connected to a data bus and writes data input via the data bus and a data input / output line based on at least a command clock;
A plurality of synchronous random access memories for reading data to the data bus via the data input / output lines based on a data clock; and A data clock generator disposed at a farthest end position, generating the command clock and supplying the command clock to the plurality of random access memories and the data clock generator, and generating data synchronized with the command clock; A memory controller that supplies the plurality of random access memories in parallel to the plurality of random access memories via the data bus and data input / output lines; and a data clock generated and output by the data clock generator in synchronization with the command clock. ,
The data is input to the memory controller and branched to be input to the plurality of random access memories, respectively, and the plurality of random access memories are synchronized with the data clock.
Control means for outputting data read from the access memory via the data input / output line and the data bus.