JPH1155099A - Digital circuit - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a digital circuit that has relatively small characteristic fluctuation, consumes low power, and does not generate relatively large noise. The present invention relates to an NchTrN1 and a PchTrP1 connected in series between a ground and a power supply, and a terminal point A for outputting a potential for driving the NchTrN1 according to an input potential IN.
And a terminal point B for outputting a potential for driving the PchTrP1. An output potential OUT4 is supplied to the gate, and a current path is connected in series between the point A and the power supply VCC.
6, P4 and an NchTr in which the output potential OUT4 is supplied to the gate and the current path is connected in series between the point B and the ground.
N6, N4 and having a slew rate circuit Inv4, Inv5,
When the output potential OUT4 changes according to the change of the input potential IN,
PchTrP4 and NchTrN4 become conductive with the change in the input potential, and PchTrP4 and NchTrN4 change with the change in the potential of the output potential OUT4.
chTrP6 and NchTrN6 become conductive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit and, more particularly, to an improvement in a circuit for a high current and high speed switch.

[0002]

2. Description of the Related Art FIG. 4A is a diagram showing a configuration of a conventional digital circuit, and FIG. 4B is a diagram showing a change in potential of each part of the circuit. FIG. 4C is a diagram showing a configuration of another conventional digital circuit, and FIGS. 4D and 4E are diagrams showing a change in potential of each part of the circuit.

As shown in FIG. 4A, an input potential IN is input to an inverting circuit (hereinafter referred to as an inverter) INV1 which is a slew rate circuit. The output potential of the inverter INV1 is supplied to each gate of an N-channel transistor (hereinafter, referred to as NchTr) N1 and a P-channel transistor (hereinafter, referred to as PchTr) P1 which constitute the buffer circuit BUFF. The source-drain (hereinafter referred to as a current path) of the NchTrN1 and the current path of the PchTrP1 are connected between a ground potential VGND and a power supply potential VC.
C and connected in series. The drains of the two transistors are connected together to form an output terminal. Note that a load capacitor C1 driven by the output of the buffer circuit BUFF is connected between the output terminal and the ground. The PchT constituting the inverter INV1
The channel length L, which is the length from the source end to the drain end of the channel of r and NchTr, is reduced.

In the digital circuit configured as described above, as shown in FIG. 4B, when the input potential IN changes from, for example, the power supply potential VCC to the ground potential VGND, the output potential OUT1 becomes the input potential. In response to the change of IN, the power supply potential VCC is changed to the ground potential VGN.
Change to D. FIG. 4B also shows the waveform of the through current I1. This through current is a current flowing through the circuit, and most of the through current flows through the PchTrP1, the NchT
This is the current flowing through rN1. As is apparent from the figure, the delay td1 of the output potential OUT1 with respect to the input potential IN.
Is small, and the peak value I1a of the through current I1 is large.

In another conventional circuit shown in FIG. 4C, the buffer circuit BUFF has the same configuration as that of FIG. 4A, but the configuration of the slew rate circuit 1 is different. That is, the slew rate circuit 1 includes two inverters INV2 and INV2 to which the input potential IN is input.
3 The output potentials of the inverters INV2 and INV3 are equal to two N in the buffer circuit BUFF.
It is supplied to the gates of chTrN1 and PchTrP1.
The PchTr included in the output stage of the inverter INV2
The channel length L of the NchTr included in the output stage of the inverter INV3 is also increased.

In the conventional circuit shown in FIG. 4C, when the input potential IN changes from, for example, the power supply potential VCC to the ground potential VGND and returns to the potential VCC, a change in the potential of the gates of NchTrN1 and PchTrP1 described later. 4D, the delay amount td2 of the output potential OUT2 of the output terminal is large, and the peak I2a of the through current I2 in the buffer circuit BUFF is small.

Further, as shown in FIG. 4E, when the input potential IN changes from the potential VCC to the ground potential VGND, the PchTr included in the output stage of the inverter INV2.
Is relatively slow to change from off to on,
Node of NchTrN1 gate (hereinafter referred to as point A)
Potential V1 slowly rises. On the other hand, the potential V2 of the gate node of the PchTrP1 (hereinafter referred to as a point B) sharply rises by the inverter INV3. Similarly, when the input potential IN changes from the ground potential VGND to the power supply potential VCC, the potential V1 at the point A sharply drops by the inverter INV2. Further, the speed at which the NchTr of the output stage of the inverter INV3 changes from the off state to the on state is relatively slow, and the potential V2 at the point B is relatively low.
Descends slowly.

FIG. 5A is a diagram showing a detailed configuration of the circuit shown in FIG. 4C. FIG. 5B shows the input potential I.
N, the change of the output potential OUT3 of the output terminal and the through current I
FIG. 5C shows an inverter INV2,
FIG. 9 is a diagram illustrating a change in the output potential of each circuit of INV3, that is, a change in potentials V3 and V4 at points A and B.

The inverter INV2 has a power supply potential VC.
NchTrN3, PchTrP4, NchT with current paths connected in series between C and ground potential VGND
rN2 and Pc whose current paths are connected in parallel to a series circuit of current paths of NchTrN3 and PchTrP4
hTrP5. PchTrP4, P5, Nch
The input potential IN is supplied to the gate of TrN2, and
The common connection point of PchTrP4, P5 and NchTrN2 is the output terminal of inverter INV2, that is, point A. Nc
The gate and drain of hTrN3 are connected, and are diode-connected.

The inverter INV3 has a power supply potential VC.
PchTrP2, NchTrN4, PchT with current paths connected in series between C and ground potential VGND
rP3 and Nc whose current paths are connected in parallel to a series circuit of current paths of NchTrN4 and PchTrP3
hTrN5. PchTrP2, NchTrN
4, the input potential IN is supplied to the gate of N5, and
The common connection point of PchTrP2, NchTrN4, and N5 is the output terminal of inverter INV3, that is, point B. Pc
hTrP3 is diode-connected.

Next, the operation of this circuit will be described. FIG.
As shown in (b), the case where the input potential IN changes from 1 level (for example, the power supply potential VCC) to 0 level (for example, the ground potential VGND) will be described.

The power supply potential VCC is supplied to the drain of the NchTrN3 in the inverter INV2.
Assuming that the voltage between the gate and the source when hTrN3 is on is VthN, the source (PchTrP4 side)
Does not become higher than the potential (VCC-VthN) regardless of the input potential. When the input potential IN changes from the 1 level to the 0 level, the PchTrP5 changes from the off state to the on state. At this time, simultaneously with PchTrP5 having a large channel length L and large on-resistance, PchTrP4 is also turned on and connected in parallel with PchTrP5, so that the resistance between power supply VCC and point A is reduced. Therefore, FIG.
As shown in (c), the potential V3 at the point A is equal to the potential VC of the power supply.
Intermediate potential VCC between C and ground potential VGND
A potential V3a of about 1 (hereinafter referred to as an intermediate potential VCC1)
Until relatively fast rise. The intermediate potential VCC1 is, for example, one of the sum of the power supply potential VCC and the ground potential VGND.
/ 2 potential.

As described above, the source of the NchTrN3 does not become higher than the potential (VCC-VthN).
The current flowing through chTrP4 is limited. When the limit starts to be applied and the potential at the point A exceeds the potential V3a, the potential at the point A slowly rises to the potential VCC of the power supply. Since the channel length L of the PchTrP5 is large, the drain potential V3 eventually reaches the power supply potential VCC relatively slowly as shown in FIG. 5C. Therefore,
The gate potential of the NchTrN1 in the buffer circuit BUFF slowly reaches the power supply potential VCC, and as a result,
The NchTrN1 changes from the off state to the on state relatively slowly.

On the other hand, the PchTr in the inverter INV3
P2 is turned on when the input potential changes from the 1 level to the 0 level, and the potential at the point B becomes 1 level. The buffer circuit B to which the one-level potential VCC is input
The PchTrP1 of the UFF is turned off. That is, P
Since the channel length L of the chTrP2 is small and the channel width W is large, the switching speed at which the PchTrP2 changes from the off state to the on state is high.
The speed at which 1 is turned off is fast.

Next, the case where the input potential changes from 0 level to 1 level will be described. Nc in inverter INV2
hTrN2 is turned on relatively quickly, and the potential at point A reaches the 0 level relatively quickly. The NchTrN1 in the buffer circuit BUFF to which the potential at the point A is input.
Also turns off relatively quickly.

On the other hand, the PchTrP of the inverter INV3
3 has a gate supplied with a ground potential VGND, and is in an on state. When a voltage between the gate and the source in this on state is VthP, the source (NchT
(rN4 side) is (VGND + Vth) regardless of the input potential.
It does not become lower than the potential of P). The input potential changes from the 0 level to the 1 level, the NchTrN4 is turned on at the same time as the NchTrN5 having a large channel length L and a large on-resistance, and the resistance between the ground VGND and the point B is reduced. As shown in FIG. 5C, V4 drops relatively quickly to a potential V4a of about the intermediate potential VCC1.

As described above, since the source of PchTrP3 does not become lower than the potential (VGND + VthP),
The current flowing through NchTrN4 is limited. When the limit starts to be applied and drops below the potential V4a, the point B
Changes slowly toward the ground potential VGND. Since the channel length L of the NchTrN5 is large, the potential V4 at the point B eventually reaches the ground potential VGND relatively slowly as shown in FIG. 5C. Accordingly, since the change in the gate potential of the PchTrP1 in the buffer circuit BUFF is also slow, the PchTrP1 changes relatively slowly from the off state to the on state.

[0018]

As described above, FIG.
In the conventional circuit shown in (a), NchTrN in inverters INV2 and INV3 for driving buffer circuit BUFF.
2. By reducing the channel length L of the PchTrP2 and increasing the channel width W, the NchTrN2, Pch
The TrP2 is quickly changed from the OFF state to the ON state, and the Nch TrN1 and Pch
The TrP1 is quickly changed from the ON state to the OFF state. And the NchTr of the buffer circuit BUFF
N1 and PchTrP1 are slowly changed from the off state to the on state. Therefore, PchTrP1, NchTrN
1 to suppress the peak value I3a of the through current I3 to some extent,
Further, the delay amount td3 of the output potential OUT3 with respect to the input potential IN is suppressed.

However, the above configuration has the following problems. The problem with this circuit is that the threshold potential of the ON / OFF state of this circuit is PchTrP
3 and the potential of each of the sources of NchTrN3 (VCC
−Vth) and (VGND + Vth), and therefore, the characteristic of the change of the output potential is greatly influenced by the Vth of each transistor. That is, Vt
The potential at which the current is limited changes due to the change in h,
There is a problem that characteristics when the output potential OUT3 changes greatly fluctuate. Also, Pc of the buffer circuit BUFF
Since the changes from the off state and the on state of hTrP1 and NchTrN1 to the vicinity of the intermediate potential VCC1 are almost the same, there is a problem that the through current does not decrease much. That is, since a large through current generates wiring noise of the power supply VCC and the ground VGND, there is a problem that the wiring noise is not reduced and the power consumption is not reduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital circuit which has relatively small fluctuations in characteristics, consumes low power, and does not generate relatively large noise.

[0020]

In order to solve the above-mentioned problems and achieve the object, the digital circuit of the present invention employs the following means. (1) The digital circuit of the present invention described in claim 1 is:
An input terminal, an output terminal, a first transistor of a first channel having a current path connected between the output terminal and the first power supply potential, and a current path between the output terminal and the second power supply potential. And a second transistor of a second channel connected to the second transistor. First and second terminals for outputting signals for driving the gates of the first and second transistors in response to input signals supplied to the input terminals, respectively, and a first terminal for supplying a signal of the output terminal to a gate. Third of two channels
A transistor, and at least one fourth transistor connected in series between the second power supply potential and the first terminal together with a current path of the third transistor and having the gate supplied with the input signal; The second terminal is brought to the second power supply potential in response to the input signal, the second transistor is turned off, and the first transistor is turned on, and the signal of the output terminal is turned on. When the power supply potential changes to 1, the fourth transistor is turned on in response to the input signal, and the gate of the third transistor is turned on in response to a change in the signal at the output terminal. A rate circuit.

In the above digital circuit of the present invention,
Since the fourth transistor is turned on in response to the input signal and the third transistor is turned on in response to the signal from the output terminal, the potential of the output terminal is positively fed back, so that the potential of the output terminal changes. In this case, the potential of the gate of the first transistor becomes an appropriate value, the through current is reduced, the power consumption is low, and relatively large noise is not generated.

According to a second aspect of the present invention, there is provided a digital circuit, comprising: an input terminal, an output terminal, and a first transistor of a first channel having a current path connected between the output terminal and a first power supply potential. And a current path between the output terminal and the second
And a second transistor of a second channel connected between the power supply potential and the second power supply potential. A connection terminal for outputting a signal for driving the gate of the first transistor in response to an input signal supplied to the input terminal; a signal supplied from the output terminal to the gate and one end of a current path connected to the second power supply potential; A third transistor of the second channel connected to the second transistor, a fourth transistor of the second channel connected to the connection terminal and the other end of the current path of the third transistor having the gate supplied with the input signal. A fifth transistor of a second channel whose gate is supplied with the input signal and whose current path is connected between the second power supply potential and the connection terminal, and whose gate is supplied with the input signal and whose current path is the third transistor. A first inversion circuit having a sixth transistor of a first channel connected between the first power supply potential and the connection terminal. A second inverting circuit is provided which supplies a signal having a logic level opposite to that of the input signal supplied to the input terminal to the gate of the second transistor to drive the second transistor.

In the above digital circuit of the present invention,
Since the signal at the output terminal is positively fed back through the third and fourth transistors, when the potential at the output terminal changes, the first
The potential of the gate of the transistor becomes an appropriate value, the through current is reduced, power consumption is low, and relatively large noise is not generated. Further, the conduction state of the third transistor is not affected by the voltage between the source and the drain, so that the variation in characteristics when the output potential changes is small.

According to a third aspect of the present invention, there is provided a digital circuit according to the first aspect, wherein a plurality of input terminals and an output terminal, and a current path is connected between the output terminal and the first power supply potential. A second transistor of a second channel having a transistor and a current path connected between the output terminal and a second power supply potential;
A transistor. A connection terminal for outputting a signal for driving the gate of the first transistor in response to an input signal supplied to the plurality of input terminals; A plurality of third transistors of a second channel connected to a second power supply potential connection terminal; and a plurality of input signals supplied to respective gates, and each current path includes a respective one of the connection terminal and the plurality of third transistors. A plurality of fourth transistors of a second channel connected to the other end of the current path;
A plurality of fifth transistors of a second channel, wherein each of the plurality of input signals is respectively supplied to each gate and each current path is connected between the second power supply potential and the connection terminal; A first logic circuit including a plurality of sixth transistors of a first channel, each of which is supplied with a plurality of input signals and whose current path is connected in series between the first power supply potential and the connection terminal; I have. A second logic circuit to which the plurality of input signals are supplied and which supplies a signal of the same logic level as that of the first logic circuit to the gate of the second transistor and drives the gate in accordance with each of the input signals; ing.

In the above digital circuit of the present invention,
When the first logic circuit operates as a NAND circuit or a NOR circuit, the potential of the output terminal is positively fed back through the third and fourth transistors, so that the potential of the gate of the first transistor has an appropriate value. Thus, the through current becomes small, the power consumption is low, and no relatively large noise is generated. Furthermore, there is no influence of the voltage between the source and the drain in the ON state of the third transistor, and the variation in the characteristics when the output potential changes is small.

According to a fourth aspect of the present invention, there is provided a digital circuit, comprising: a plurality of input terminals and an output terminal; and a first channel of a first channel having a current path connected between the output terminal and a first power supply potential. A second transistor of a second channel having a transistor and a current path connected between the output terminal and a second power supply potential;
A transistor. A connection terminal for outputting a signal for driving a gate of the second transistor in response to an input signal supplied to the plurality of input terminals, a signal supplied from the output terminal to a gate, and one end of a current path connected to the first terminal;
A plurality of input signals are supplied to the third transistor of the first channel connected to the power supply potential of the first channel and the respective gates, and the respective current paths are connected in series to form a first series circuit. A plurality of fourth transistors of a first channel connected between the connection terminal and the other end of the third transistor; a plurality of input signals supplied to each gate; Connected to form a second series circuit, the second series circuit comprising a plurality of fifth transistors of a first channel connected between the connection terminal and a first power supply potential; A first logic circuit having a plurality of sixth-channel transistors of a second channel connected in parallel between a second power supply potential and the connection terminal, to which an input signal is supplied, respectively, is provided. A second logic circuit that is supplied with the plurality of input signals and that supplies a signal having the same logic level as that of the first logic circuit to the gate of the first transistor in accordance with each of the input signals to drive the gate; ing.

In the above digital circuit of the present invention,
When the first logic circuit operates as a NAND circuit or a NOR circuit, the potential of the output terminal is positively fed back through the third and fourth transistors, so that the potential of the gate of the second transistor has an appropriate value. Thus, the through current becomes small, the power consumption is low, and no relatively large noise is generated. Furthermore, there is no influence of the voltage between the source and the drain in the ON state of the third transistor, and the variation in the characteristics when the output potential changes is small.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1A is a diagram showing a configuration of a digital circuit according to a first embodiment of the present invention.
FIG. 1B is a diagram showing changes in the input potential IN and the output potential OUT4 of the circuit in FIG. 1A and the through current I4. FIG. 1C is a diagram showing a change in potential of each node for explaining the operation of the circuit of FIG. 1A.

The digital circuit of this embodiment includes a buffer circuit BUFF composed of PchTrP1 and NchTrN1, and a Pc in this buffer circuit BUFF.
It has a slew rate circuit composed of inverting circuits (hereinafter referred to as inverters) INV4 and INV5 for driving the gates of hTrP1 and NchTrN1. The configuration of the buffer BUFF is the same as that of the conventional circuit shown in FIG.
As for INV5, only the parts different from FIG. 5A will be described.

In one inverter INV4, the Nc
PchTrP6 is provided instead of hTrN3.
That is, the current path of this PchTrP6 is
And PchTrP4, and the gate thereof is connected to the output terminal of the buffer circuit BUFF.

In the other inverter INV5, Pc
NchTrN6 is provided instead of hTrP3.
That is, the current path of the NchTrN6 is connected between the ground and the NchTrN4, and the gate is connected to the output terminal of the buffer circuit BUFF.

Next, the operation of the circuit configured as described above will be described. First, as shown in FIG. 1B, the input potential IN is changed from the power supply potential VCC to the ground potential VG, for example.
The case of changing to ND will be described.

When the input potential IN is the power supply potential VCC (initial state), the NchTrN2 in the inverter INV4
Is on, PchTrs P4, P5, and P6 are off, and the potential V5 at point A is the ground potential VGN.
D, and the NchTrN1 in the buffer circuit BUFF is off. On the other hand, Nch in the inverter INV5
TrN4, N5, and N6 are on, PchTrP2 is off, and the potential V6 at the point B is also the ground potential VGN.
D, and PchTrP1 in the buffer circuit BUFF is in the ON state. Therefore, the output potential OUT4 of the buffer circuit BUFF is the power supply potential VCC.

When the input potential IN changes from the power supply potential VCC to the ground potential VGND, the inverter INV5
Is turned on, the potential V6 at the point B sharply increases from the ground potential VGND toward the power supply potential VCC, and the buffer circuit BUFF
PchTrP1 is turned off relatively quickly.

On the other hand, when the input potential IN is the ground potential VG
After changing to ND, NchT in inverter INV4
rN2 is turned off, and PchTrP4, P5 are turned on. At this time, PchTrP6 is still off. Therefore, the only transistor that contributes to the charging of the point A is the PchTrP5, and the potential V5 relatively slowly increases from the ground potential VGND toward the power supply potential VCC. The potential V5 is N in the buffer circuit BUFF.
When the voltage exceeds the threshold voltage of chTrN1, for example, the potential V5a, the NchTrN1 is turned on and the output potential O
UT4 is shifted from the power supply potential VCC to the ground potential VGND.
Begins to fall towards. The output potential OUT4 is the potential VC
When the potential falls below the potential OUT4a near C1, the PchTrP6 in the inverter INV4 is turned on. That is, a series circuit of PchTrP6 and P4 and an on-state PchTrP5 connected in parallel with it.
The potential at the point A starts to rise due to the charging through the combined resistance with. Therefore, thereafter, the potential V5 rises sharply, the NchTrN1 in the buffer circuit BUFF is sufficiently turned on, and thereafter, the output potential OUT4 drops sharply toward the ground potential VGND.

That is, the input potential IN is equal to the power supply potential VCC.
When the output potential OUT4 of the buffer circuit BUFF changes from the inverter INV4 to the ground potential VGND.
Buffer circuit BUF via PchTr P6 and P4 in
It is fed back to F.

The output potential OUT4 is equal to the ground potential V.
While the voltage drops to GND, the NchTrN6 in the inverter INV5 changes from the on state to the off state. When the output potential OUT4 exceeds the potential OUT4a, PchT
Since rP6 changes to the on state, the input / output characteristics of the input potential IN and the output potential OUT4 change relatively steeply. Therefore, the time required for the output potential OUT4 to reach the potential OUT4a is substantially the same as that of the conventional circuit shown in FIG. However, after that, OUT4 becomes the ground potential VG.
The time required to reach ND is shortened, which is almost the same as that of the conventional circuit shown in FIG. Therefore, the total delay time td
4 is smaller than the conventional td2. In addition, PchTr
P1 is immediately turned off, and NchTrN1 is not sufficiently turned on at first. When NchTrN1 is sufficiently turned on, PchTrP1 is almost completely turned off. Therefore, the peak value I4 of the through current I4
a becomes smaller.

Next, a case where the input potential IN changes from, for example, the ground potential VGND to the power supply potential VCC will be described. When the input potential IN changes as described above,
When the NchTrN2 in the inverter INV4 is turned on, the potential V5 at the point A sharply drops from the power supply potential VCC to the ground potential VGND.
Then, the NchTrN1 of the buffer circuit BUFF is turned off relatively quickly.

On the other hand, after the input potential IN changes to the power supply potential VCC, the PchTrP2 in the inverter INV5
Are turned off, and NchTrs N4 and N5 are turned on. At this time, NchTrN6 is still off. Therefore, the transistor contributing to the discharge at point B is Nc
Only hTrN5 is present, and the potential V6 decreases relatively slowly from the power supply potential VCC to the ground potential VGND. The potential V6 is equal to Pch in the buffer circuit BUFF.
When the voltage exceeds the threshold voltage of TrP1, for example, the potential V6a,
This PchTrP1 is turned on, and the output potential OUT
4 starts to rise from the ground potential VGND toward the power supply potential VCC. The output potential OUT4 is equal to the potential VCC1.
Is higher than the potential OUT4b, which is a value close to the NchTrN6 in the inverter INV5, and the NchTrN6 in the inverter INV5 is turned on. The potential of B starts to decrease. Therefore, thereafter, the potential V6 drops sharply, and the buffer circuit B
The PchTrP1 in the UFF is sufficiently turned on, and thereafter, the output potential OUT4 sharply increases toward the power supply potential VCC.

That is, when the input potential IN is the ground potential V
When the potential changes from GND to the power supply potential VCC, the output potential OUT4 of the buffer circuit BUFF changes to the inverter INV5.
Buffer circuit BUF via NchTr N6 and N4
It is fed back to F.

The output potential OUT4 is equal to the power supply potential VCC.
While rising, the Pch in inverter INV4
TrP6 changes from the on state to the off state. When the output potential OUT4 exceeds the potential OUT4b, NchTrN6
Changes to the ON state, the input potential IN and the output potential O
The input / output characteristics of the UT 4 change relatively steeply. Therefore, the time required for the output potential OUT4 to reach OUT4b is substantially the same as that of the conventional circuit shown in FIG. However, thereafter, the time required for OUT4 to reach the potential VCC of the power supply is shortened, and is substantially the same as that of the conventional circuit of FIG. Therefore, the total delay time td4 is equal to the conventional delay time td4.
It becomes smaller than 2. Further, the NchTrN1 is immediately turned off, and the PchTrP1 is not sufficiently turned on at first. When PchTrP1 is sufficiently turned on, NchTrN1 is almost completely turned off. Therefore, the peak value I4a of the through current I4 decreases.

For example, as described above, the input potential I
When an input signal of N, that is, a change in potential between 1 level corresponding to the power supply potential VCC and 0 level corresponding to the ground potential VGND, is applied, the inverter INV4 outputs the output of the buffer circuit BUFF. Signal OU
When T4 drops from 1 level to 0 level, the delay time td4 for the input signal is not increased, and the peak value I4a of the through current I4 is reduced. Inverter INV5
Does not increase the delay time td4 with respect to the input signal when the output signal OUT4 of the buffer circuit BUFF rises from the 0 level to the 1 level, and increases the peak value I4a of the through current I4.
Is smaller. Therefore, the rise of the input signal IN,
If there is a demand to reduce the value of the through current without increasing the delay time only at one of the falling edges, one of the inverters INV4 and INV5 is provided, and the other is shown in FIG. Such conventional ones can also be used.

In the above embodiment, the PchTr
By positively feeding back the output potential OUT4 via P6, P4 or NchTr N6, N4, PchTr
P5 and PchTrP4, or NchTrN5 and Nc
Transistors NchTrN1, Pc by hTrN4
The potential of the gate of hTrP1 is set to an appropriate value. Therefore,
The drain current of either PchTrP1 or NchTrN1 at the point where the output potential OUT4 of the buffer circuit BUFF changes becomes smaller, and the peak value I4a of the through current I4 becomes smaller. Therefore, relatively large noise does not occur and power consumption is reduced. When the output potential OUT4 changes,
When the potential exceeds the potential OUT4a or OUT4b, the output potential OUT4 changes rapidly, so that the delay amount td4 from the change in the input potential IN to the change in the output potential OUT4 does not increase. Furthermore, PchTrP6, NchTr
Since the ON state of N6 is determined by the output potential OUT4, there is no influence of Vth of the transistor, and a change in characteristics when the output potential OUT4 changes is small. (Second Embodiment) FIG. 2 is a diagram showing a circuit configuration according to a second embodiment. Inverters INV4 and INV5 constituting the slew rate circuit of the first embodiment are connected to logic circuits. Example NAND circuits NAND1, NAND2
Is replaced with Note that the buffer circuits BUFF are the same, and hereinafter, NAND circuits NAND1, NAND1
2 will be described.

The NAND circuit NAND1 has Pch Trs P7, P8, Nc whose current paths are connected in series to the power supply in order.
It has hTrN7, N8, and PchTrP9 whose current path is connected in parallel with PchTrP8, P7.
Further, PchTrP10, PchTrP10 whose current paths are connected in series between the power supply potential VCC and the gate of NchTrN1.
11 and Pc having a current path connected to them in parallel.
It consists of hTrP12. One input potential IN1 is Nch
It is supplied to the gates of TrN8, PchTrP11 and P12. The other input potential IN2 is PchTrP8, P9,
It is supplied to the gate of NchTrN7. PchTrP
The common connection point of 8, P9, P11, P12 and NchTrN7 is the output terminal of the NAND circuit NAND1, that is, point A. The output potential OUT5 is supplied to the gates of the PchTrs P7 and P10 from the buffer circuit BUFF.

The NAND circuit NAND2 includes a PchTr N13 and an NchTr whose current paths are connected in series to a power supply in series.
N9, N10 and N11 are provided. Further, PchTrP14, Nc
hTrN12 and hTr13. One input potential IN1
Is supplied to the gates of PchTrP14, NchTrN10 and N13. The other input potential IN2 is PchTrP
13, is supplied to the gates of NchTr N9 and N12.
The common connection point of PchTrP13, P14, NchTrN9, N12 is the output terminal of NAND circuit NAND2, that is, point B. The output potential OUT5 is supplied from the buffer circuit BUFF to the gate of the NchTrN11.

Incidentally, as in the first embodiment, the NAND
Only one of the circuits NAND1 and NAND2 may have the circuit configuration according to the second embodiment, and the other may have the conventional circuit configuration.

In the second embodiment, the first
PchTrP7, P8, or PchTrP10, P11, or NchTrN
11, N10 and N9, the output potential OUT5 is positively fed back, so that the PchTrP in the buffer circuit BUFF
1. The potential of the gate of NchTrN1 can be set to an appropriate value,
The through current is reduced. Therefore, relatively large noise does not occur and power consumption is reduced. Further, when the output potential OUT5 exceeds a potential of about the intermediate potential VCC1, the output potential OUT1 changes rapidly, so that the delay amount from the change in the input potential IN to the change in the output potential OUT5 does not increase. Furthermore, PchT
Since the on-states of rP7, PchTrP10, and NchTrN11 are determined by the output potential OUT5, there is no influence of Vth of the transistor, and the variation in characteristics when the output potential OUT5 changes is small. (Third Embodiment) FIG. 3 is a diagram showing a configuration of a digital circuit according to a third embodiment. Inverters INV4 and INV constituting a slew rate circuit of the first embodiment are shown in FIG.
V5 is a NOR circuit NOR1, NOR which is an example of a logic circuit.
2 is replaced. The buffer circuit BUFF
Are the same, and hereinafter, a NOR circuit NOR which is a logic circuit
1. The configuration of NOR2 will be described.

The NOR circuit NOR1 includes Pch Trs P15, P16, and P1 having current paths connected in series to a power supply in order.
7, has NchTrN14. Further, PchTrP18, P1 whose current paths are connected in series to the power source in order.
9, NchTrN15. One input potential IN1
Are supplied to the gates of PchTrP16, P18 and NchTrN15. The other input potential IN2 is PchTrP
17, P19, and supplied to the gate of NchTrN14. PchTrP17, P19, NchTrN14, N
The 15 common connection points are output terminals of the NOR circuit NOR1, that is, point A. The output potential OUT6 is supplied from the buffer circuit BUFF to the gate of the PchTrP15.

The NOR circuit NOR2 includes Pch Trs P20, P21, and Nch whose current paths are connected in series to the power supply in order.
TrN16, N17 and NchTrN16, N17
And an NchTrN18 having a current path connected in parallel. Further, an NchTrN19 having a current path connected in series between the gate of the PchTrP1 and the ground,
N20 and NchTrN connected in parallel to them
21. One input potential IN1 is PchTrP2
1, supplied to the gates of NchTrs N16 and N18.
The other input potential IN2 is PchTrP20, NchTr
It is supplied to the gates of N19 and N21. PchTrP2
1, the common connection point of NchTrs N16, N18, N19, and N21 is the output terminal of NOR circuit NOR2, that is, point B. The output potential OUT6 is supplied to the gates of the NchTrs N17 and N20 from the buffer circuit BUFF.

As in the first embodiment, only one of the NOR circuits NOR1 and NOR2 is connected to the third circuit.
In the circuit configuration according to the embodiment, the other may be a conventional circuit configuration.

In the third embodiment, the first embodiment
PchTrP15, P16, PchTrP
17, or NchTrN17, N16, or N
Since the output potential OUT6 is positively fed back via the chTrN20 and N19, the PchT in the buffer circuit BUFF is
The potentials of the gates of rP1 and NchTrN1 can be set to appropriate values, and the through current decreases. Therefore, relatively large noise does not occur and power consumption is reduced. Also, the output potential OUT
6 changes rapidly when the potential exceeds about the intermediate potential VCC1, the delay amount from the change in the input potential IN to the change in the output potential OUT6 does not increase. Furthermore, Pc
Since the on-state of hTrP15, NchTrN17 and NchTrN20 is determined by the output potential OUT6, there is no influence of Vth of the transistor, and the output potential OUT5
The change in the characteristic when the change in the value is small.

[0052]

As described above, according to the present invention, it is possible to provide a digital circuit which has a relatively small variation in characteristics, low power consumption and does not generate relatively large noise.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a digital circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a digital circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a digital circuit according to a third embodiment of the present invention.

FIG. 4 illustrates an example of a conventional digital circuit.

FIG. 5 illustrates an example of a conventional digital circuit.

[Explanation of symbols]

P1 to P21: P-channel transistor, N1 to N21: N-channel transistor, INV1 to INV5: Inverter (slew rate circuit), NAND1, NAND2: NAND circuit (slew rate circuit), NOR1, NOR2 ... NOR circuit (slew rate circuit) IN: input potential; V1, V3, V5: potential at point A; V2, V4, V6: potential at point B; OUT1 to OUT6: output potential.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shoji Horie 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. Toshiba Microelectronics Corporation

Claims (4)

[Claims] An input terminal and an output terminal; a current path connected between the output terminal and a first power supply potential; a first transistor of a first channel connected between the output terminal and a first power supply potential; A second transistor of a second channel connected between the power supply potential and a first transistor for outputting a signal for driving each gate of the first and second transistors according to an input signal supplied to the input terminal; , A second terminal, a third transistor of a second channel having a gate supplied with the signal of the output terminal, and a current path between the second power supply potential and the first terminal together with a current path of the third transistor. And at least one fourth transistor, the gate of which is supplied with the input signal, wherein the second terminal is brought to the second power supply potential in response to the input signal. Is not And when the first transistor is turned on and the signal at the output terminal changes to the first power supply potential, the fourth transistor is turned on in response to the input signal, and A digital circuit, comprising: a slew rate circuit that turns on a gate of the third transistor in accordance with a change in a signal at the output terminal. 2. An input terminal and an output terminal; a first transistor of a first channel having a current path connected between the output terminal and a first power supply potential; and a current path having a current path between the output terminal and a second power supply potential. A second transistor of a second channel connected to a power supply potential; a connection terminal for outputting a signal for driving a gate of the first transistor in response to an input signal supplied to the input terminal; A third transistor of a second channel, to which a signal from an output terminal is supplied and one end of a current path is connected to the second power supply potential, a gate to which the input signal is supplied and the current path is connected to the connection terminal and the third transistor A fourth transistor of a second channel connected to the other end of the current path of the second channel;
A fifth transistor of a second channel connected between the power supply potential of the second channel and the connection terminal; a gate to which the input signal is supplied; and a current path connected between the first power supply potential and the connection terminal. A first inverting circuit having a sixth transistor of the first channel, and a second driving circuit that supplies a signal of a logic level opposite to the input signal supplied to the input terminal to the gate of the second transistor to drive the signal. And a reversing circuit. 3. A first transistor of a first channel having a plurality of input terminals and an output terminal, a current path connected between the output terminal and a first power supply potential, and a current path connected to the output terminal. A second transistor of a second channel connected between the second power supply potential and a connection terminal for outputting a signal for driving a gate of the first transistor in accordance with an input signal supplied to the plurality of input terminals; A plurality of third transistors of a second channel, each of which receives a signal of the output terminal at each gate and one end of a current path is connected to the second power supply potential; and a plurality of input signals at each gate. A plurality of fourth transistors of a second channel connected to the connection terminal and the other end of each of the plurality of current paths of the plurality of third transistors; and a plurality of input signals to each gate. Fifth plurality of second channels respectively connected between each current path are supplied respectively to the second power supply potential and the connection terminal
A first transistor comprising: a transistor; and a plurality of sixth transistors of a first channel, each of which has the plurality of input signals supplied to its gate, and a current path connected in series between the first power supply potential and the connection terminal. A plurality of input signals are supplied, and in response to each of the input signals, a signal of the same logic level as that of the first logic circuit is supplied to the gate of the second transistor to drive the second transistor. A digital circuit, comprising: a logic circuit. 4. A first transistor of a first channel having a plurality of input terminals and an output terminal, a current path connected between the output terminal and a first power supply potential, and a current path connected to the output terminal and the first transistor. A second transistor connected between the second power supply potential and a second power supply potential; a connection terminal for outputting a signal for driving a gate of the second transistor in accordance with an input signal supplied to the plurality of input terminals; A third transistor of a first channel having a gate to which the signal of the output terminal is supplied and one end of a current path connected to the first power supply potential; A plurality of fourth transistors of a first channel connected between the connection terminal and the other end of the third transistor, the paths being connected in series to form a first series circuit; Said plurality of input signals are respectively supplied to the gate, the second series circuit is formed each current path are connected in series, the second
A plurality of fifth transistors of a first channel connected in series between the connection terminal and the first power supply potential; a plurality of input signals supplied to respective gates; A first logic circuit having a plurality of sixth transistors of a second channel connected in parallel between the first input terminal and the connection terminal; and the plurality of input signals being supplied. A second logic circuit for supplying a signal of the same logic level as the first logic circuit to the gate of the first transistor to drive the same.