JPH1167583A - Laminated type electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated type electronic component capable of improving the mounting density. SOLUTION: In a laminated layer type chip capacitor 1, in which dielectric layers 2 made of sintered ceramic bodies and electrode layers 3 made by baking conductive paste, the electrode layer 3 is exposed to a section of the laminated layer, this electrode layer 3 works as a terminal electrode for connecting to a circuit substrate 10, this electrode layer 3 can be placed on lands 11a and 11b attached to the surface of the circuit substrate 10 and then mounting is possible by soldering. In this case, the lands 11a and 11b during mounting can be mounted as long as the width is larger than the thickness of the electrode layer 3 of the laminated chip capacitor 1. Thus, a solder fillet formed from the lands 11a, 11b to the electrode layer 3 can be made smaller, so that the interval of a plurality of laminated layer chip capacitor 1 can be made smaller, mounted on the circuit substrate 10, and soldered for mounting. By doing this, the mounting density can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer electronic component represented by a multilayer chip capacitor and a multilayer chip inductor.

[0002]

2. Description of the Related Art FIG. 11 shows a multilayer chip capacitor which is an example of a conventional multilayer electronic component. FIG. 11 is an exploded perspective view of the multilayer chip capacitor.

In FIG. 1, reference numeral 101 denotes a multilayer chip capacitor, which is a substantially rectangular parallelepiped element 104 formed by alternately laminating dielectric layers 102 and internal electrodes 103, and the internal electrodes 103 are alternately provided at both ends of the element 104. And a pair of external electrodes 105 connected in parallel.

The internal electrode 103 is composed of an internal electrode piece 103a provided near the central region of the dielectric layer 102 and an internal electrode lead portion 103b provided along the external electrode 105 and connected to the external electrode 105. And internal electrode piece 1
03a is the external electrode 10 via the internal electrode extraction portion 103b.
5 is electrically connected.

[0005] The dielectric layer 102 is formed of a rectangular sheet-shaped ceramic sintered body, and the ceramic sintered body is formed of a dielectric ceramic material whose main component is, for example, magnesium titanate.

The internal electrode 103 is made of a metal thin film obtained by sintering a metal paste. As the metal paste, one containing a metal material such as Pd or Pd-Ag as a main component is used. From 40% by weight to 80% by weight.

The external electrode 105 is formed from the end face of the element body 104 to the side surface adjacent thereto so as to cover the internal electrode lead portions 103b exposed on both end faces of the element body 104. The external electrode 105 is connected to the internal electrode 1.
It is formed of the same material as that of No. 03, and its surface is plated with solder to improve solder wettability.

In order to mount the multilayer chip capacitor 101 on a circuit board, a predetermined amount of solder paste is printed on a land made of a conductor provided on the surface of the circuit board, and external electrodes 105 are formed on the solder paste. After the multilayer chip capacitor 101 is mounted so as to be arranged, the solder paste is reflowed.

Further, chip resistors and chip inductors, which are examples of other multilayer electronic components, have external appearances in which terminal electrodes are provided at both ends of a rectangular parallelepiped like the multilayer chip capacitor 101. I have.

[0010]

However, when the multilayer chip capacitor 101 is mounted on a land of a circuit board, a solder fillet having at least the width of the external electrode 105 is formed at both ends of the element body 104. When the capacitor 101 is mounted, the capacitor 101 is mounted on a circuit board with a certain interval between them to prevent a short circuit of the solder fillet, that is, the pitch between the external electrodes 105 as the terminal electrodes is set to a certain value or more. Needed. Therefore, it has been difficult to improve the mounting density of the multilayer chip capacitor 101 by a certain level or more. As described above, since the appearance of other multilayer electronic components such as a chip inductor is the same, it is difficult to improve the mounting density of these components to a certain level or more.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer electronic component capable of improving a mounting density.

[0012]

In order to achieve the above object, according to the first aspect of the present invention, a laminated body formed by alternately laminating a plurality of ceramic sheets and conductor patterns is cut to a predetermined size. In a laminated electronic component having a substantially rectangular parallelepiped shape in which one laminated cross section is mounted to face a circuit board, the conductor pattern is exposed on the laminated cross section of the laminated electronic component as a terminal electrode for connection with the circuit board. Features.

According to the present invention, the conductor pattern exposed on the laminated section of the multilayer electronic component is directly used as the connection terminal electrode with the circuit board. It can be mounted on a land provided on the surface of the substrate and soldered for mounting. In this mounting, the land can be mounted if it has a width equal to or larger than the thickness of the conductor pattern of the multilayer electronic component.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer chip capacitor according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is an exploded perspective view of the multilayer chip capacitor.

Referring to FIG. 1, reference numeral 1 denotes a multilayer chip capacitor in which the outermost layer is a dielectric layer 2 and dielectric layers 2 and electrode layers 3 are alternately laminated. The electrode layer 3 is built in.

The dielectric layer 2 is formed of a rectangular sheet-shaped ceramic sintered body, and the sintered body is formed of, for example, a dielectric ceramic material formed by firing a green sheet containing barium titanate as a main component. As specific dimensions, the width is 0.5
mm, length 1.0 mm, thickness 20 μm.

The electrode layers 3 adjacent via the dielectric layer 2 are
The width and length are the same as the dielectric layer 2 and the thickness is 25
μm. The electrode layer 3 is formed of a metal thin film obtained by sintering a conductive paste containing palladium as a main component. As the conductive paste, a palladium powder having an average particle size of 1.5 μm, ethyl cellulose, and the dielectric layer 2 are formed. A powder obtained by dissolving the same ceramic sintered body powder in butyl carbitol as used is used. Here, the ceramic powder is mixed to strengthen the bond with the dielectric layer 2, and the ceramic powder and the palladium powder are mixed at a ratio of 15:85.

The multilayer chip capacitor 1 is connected to the circuit board 1
The method of mounting the information on the "0" will be described with reference to FIGS. FIG. 2 is a plan view of the circuit board, and FIG. 3 is a schematic perspective view for explaining a method of mounting the multilayer electronic component on the circuit board. In the drawing, reference numeral 11 denotes a conductor provided on the surface of the circuit board 10. Is a land.

Land 1 provided on the surface of circuit board 10
Reference numeral 1 denotes a conductive material having a width at least equal to or greater than the thickness of the electrode layer 3. The electrode layer 3, which is exposed on the laminated cross section of the multilayer chip capacitor 1 when the multilayer chip capacitor 1 is mounted, is laminated. The chip capacitors 1 are arranged on the left and right sides so as to be connected alternately at both ends. That is, the odd-numbered one of the plurality of electrode layers 3 is
The lands 11a1 to 11a5 are arranged so as to be connected at one end, and the lands 11b1 to 11b5 are arranged so as to connect an even-numbered electrode layer 3 at the other end.
The lands 11a1 to 11a5 are electrically connected to each other, and similarly, the lands 11b1 to 11b5 are electrically connected to each other.

In order to mount the multilayer chip capacitor 1 on the circuit board 10, as shown in FIG.
0, and the electrode layer 3 exposed in the lamination section is arranged on the land 11 to which the solder paste has been applied in advance. In order to ensure adhesion to the circuit board 10, a non-conductive adhesive may be interposed between the circuit board 10 and the multilayer chip capacitor 1.

When the multilayer chip capacitor 1 is mounted on the circuit board 10 as described above, a capacitor having a predetermined capacitance is mounted between the lands 11a and 11b.

Next, a method of manufacturing the multilayer chip capacitor 1 will be described. First, an organic binder is added to the dielectric raw material powder in an amount of 15% by weight, water is further added in an amount of 50% by weight, and these are put in a ball mill and sufficiently mixed to prepare a slurry of the dielectric ceramic material.

Next, the slurry is placed in a vacuum defoamer to remove bubbles, and then placed in a reverse roll coater to form a thin film of the slurry on a polyester film.
This thin film is dried by heating to 100 ° C. on a polyester film, punched out, and 10 cm square, about 2 mm thick.
A green sheet of 5 μm is obtained.

On the other hand, 51 g of palladium powder having an average particle size of 1.5 μm and ceramic powder 9 having an average particle size of 2.0 μm
g and 0.9 g of ethylcellulose dissolved in 9.1 g of butyl carbitol are placed in a stirrer and stirred for 10 hours to obtain a conductive paste for the electrode layer 3.

Thereafter, the conductive paste is applied to the entire surface of one side of the green sheet, and after drying, a plurality of green sheets are laminated with the application side facing up. The green sheets to which the paste is not applied are laminated. Next, the laminate is pressed at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. Thereafter, the laminate is cut into a lattice to obtain about 50 laminated chips.

Next, the laminated chip is placed in a furnace that can be fired in an atmosphere, and heated to 600 ° C. in the air to fire the organic binder. From 600 ° C. to a firing temperature of 1150 ° C. (maximum temperature) and hold for 3 hours. Thereafter, the temperature is lowered to 600 ° C. at a rate of 100 ° C./hour and cooled to room temperature to obtain a sintered body chip.

Lastly, the sintered chip is made to have a particle size of 0.5 m.
After barrel polishing is performed for about 10 minutes using zirconia of about m as a medium, the electrode layer 3 exposed in the lamination cross section is subjected to solder plating to obtain the multilayer chip capacitor 1.

According to the multilayer chip capacitor 1, the electrode layer 3 is exposed on the laminated cross section of the multilayer chip capacitor 1 formed by laminating the dielectric layer 2 and the electrode layer 3, and the electrode layer 3 is used as it is on the circuit board 10. It can be mounted on the land 11. At the time of this mounting, the land 11 is
If the width is equal to or more than the thickness, mounting becomes possible. For this reason, the solder fillet formed from the land 11 to the electrode layer 3 can be made extremely small, so that when mounting a plurality of multilayer chip capacitors 1, the interval between them can be reduced. In particular, when the multilayer chip capacitors 1 are juxtaposed in the laminating direction, they can be mounted on the circuit board 10 without any gap or with a slight gap. Thereby, the mounting density on the circuit board 10 can be improved.

In this embodiment, the lands 11a1 to 11a5 as shown in FIG. 2 are provided when the multilayer chip capacitor 1 is mounted on the circuit board 10. However, the lands 11a1 to 11a1 11a5, land 11b
1 to b5, that is, by connecting the lands 11 only to arbitrarily selected ones of the electrode layers 3 of the multilayer chip capacitor 1, the lands 1
The capacitance generated between 1a and 11b can be adjusted.

In this embodiment, the land 11a1
To 11a5 and the lands 11b1 to 11b5 are conductively connected to each other to implement a single capacitor having a predetermined capacitance between the lands 11a and 11b. For example, as shown in FIG. And land 11a1
11a3, 11b1 to 11b3, 11c1 to 11c
2, 11d1 to 11d2 may be electrically connected. In this case, it can be mounted and used as a first capacitor having the lands 11a and 11b as terminals and a second capacitor having the lands 11c and 11d as terminals. That is, it can be used as a capacitor array having a plurality of built-in capacitors depending on the arrangement and connection of each land 11. In this case, it is preferable that the layer 2a to be interposed between the first capacitor and the second capacitor is an insulator layer having a lower dielectric constant than the other dielectric layers 2 because crosstalk is suppressed.

Further, in the present embodiment, the electrode layer 3 is formed to have the same width and length as the dielectric layer 2 and is exposed in four laminated cross sections of the multilayer chip capacitor 1. As shown, only a part of the laminated section may be exposed.
In FIG. 5, the electrode layer 3 includes a first electrode piece 3a and a second electrode piece 3b. The first electrode piece 3a has a rectangular shape that is slightly smaller than the width and length of the dielectric layer 2 and is not exposed to the lamination section. The second electrode piece 3b is a rectangular one provided at two corners adjacent to the first electrode piece 3a, and its peripheral portion is exposed alternately in the laminated cross section of the multilayer chip capacitor 1. The method of mounting the multilayer chip capacitor 1 on the circuit board 10 is the same as that described above, but as shown in FIG. 6, the land width is increased because the electrode layer 3 is not exposed between adjacent lands. Circuit board 10
It is easy to mount on

Next, a multilayer chip capacitor according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is an exploded perspective view of the multilayer chip capacitor.

In the figure, reference numeral 21 denotes a multilayer chip capacitor, wherein the outermost layer is a dielectric layer 22 and a dielectric layer 22 is provided.
And the electrode layers 23 and 24 are alternately laminated.

The dielectric layer 22 is formed of a rectangular sheet-shaped ceramic sintered body, and the sintered body is formed of, for example, a dielectric ceramic material formed by firing a green sheet mainly containing barium titanate. As specific dimensions, the width is 0.
5 mm, length 1.0 mm, thickness 20 μm.

Each of the pair of electrode layers 23 has the same width and length as the dielectric layer 22, and has a thickness of 25 μm. The pair of electrode layers 23 is formed through the dielectric layer 22 through the electrode layers 24.
And is disposed so as to sandwich a laminate composed of the dielectric layer 22 and the electrode layer 24. As a result, the electrode layers 23 are exposed in the four cross sections of the multilayer chip capacitor 21.

The electrode layers 24 adjacent to each other via the dielectric layer 22
Are arranged so as to be sandwiched between a pair of dielectric layers 23 via the dielectric layer 22. The thickness of the electrode layer 24 is smaller than that of the electrode layer 23 and is set to 5 μm. The electrode layer 24 is located at a position slightly shifted from the central region of the dielectric layer 22 and has a slightly smaller area than the dielectric layer 22 and a second electrode piece 24a for forming the through hole H. Of electrode pieces 24b. A through hole H is formed in the first electrode piece 24a, and is electrically connected to a through hole H formed in the second electrode piece 24b of the adjacent electrode layer 24 via the dielectric layer 22. Further, the through hole H formed in the second electrode piece 24b of the outermost electrode layer 24 is electrically connected to the through hole H provided in the electrode layer 23 adjacent to the second electrode piece 24b. That is, “the electrode layer 23 -the second electrode piece 24b -the first electrode piece 24b-(approximately)-the first electrode piece 24b" in the stacking direction via the through hole H.
To the first electrode piece 24a- in the same direction.
Second electrode piece 24b -... (abbreviated)--Second electrode piece 24b
-Electrode layer 23 ".

The electrode layer 23 is made of a metal thin film obtained by sintering a conductive paste containing palladium as a main component. Examples of the conductive paste include palladium powder having an average particle size of 1.5 μm, ethyl cellulose, and the dielectric layer. A powder obtained by dissolving the same powder of the ceramic sintered body as that forming 22 in butyl carbitol is used. Here, the ceramic powder is mixed to strengthen the bond with the dielectric layer 2, and the ceramic powder and the palladium powder are mixed at a ratio of 15:85. The electrode layer 24 is also made of a metal thin film obtained by sintering a conductive paste containing palladium as a main component. As the conductive paste, palladium powder having an average particle size of 1.5 μm and ethyl cellulose dissolved in butyl carbitol. Things are used.

A method for mounting the multilayer chip capacitor 21 on the circuit board 10 will be described with reference to FIG. FIG. 8 is a schematic perspective view for explaining the mounting of the multilayer electronic component on a circuit board.
Is a land made of a conductive material attached to the surface of the substrate.

Land 1 provided on the surface of circuit board 10
Reference numeral 1 denotes a conductive material having a width at least equal to or greater than the thickness of the electrode layer 23, and is electrically connected to the electrode layer 23 exposed in the laminated cross section of the multilayer chip capacitor 21 when the multilayer chip capacitor 21 is mounted. So that it is arranged on one side of the multilayer chip capacitor 21. Land 11
Correspond to the land 11 a so as to correspond to the pair of electrode layers 23.
And 11b.

In order to mount the multilayer chip capacitor 21 on the circuit board 10, a multilayer cross section of the multilayer chip capacitor 21 having a large area is opposed to the circuit board 10,
The electrode layer 23 exposed in the lamination section is arranged on the land 11 to which the solder paste has been applied in advance. In order to ensure adhesion to the circuit board 10, a non-conductive adhesive may be interposed between the circuit board 10 and the multilayer chip capacitor 21.

Next, a method of manufacturing the multilayer chip capacitor 21 will be described. First, 15% by weight of an organic binder was added to the dielectric material powder, and 50% by weight of water was further added.
Are added to a ball mill and mixed well to form a slurry of the dielectric ceramic material.

Next, the slurry was placed in a vacuum defoamer to remove bubbles, and then placed in a reverse roll coater to form a thin film of the slurry on a polyester film.
This thin film is dried by heating to 100 ° C. on a polyester film, punched out, and 10 cm square, about 2 mm thick.
A green sheet of 5 μm is obtained. Next, through holes are made in predetermined positions of the green sheet by using a laser.

On the other hand, 51 g of palladium powder having an average particle size of 1.5 μm and ceramic powder 9 having an average particle size of 2.0 μm
g and 0.9 g of ethylcellulose dissolved in 9.1 g of butyl carbitol are placed in a stirrer and stirred for 10 hours to obtain a first conductive paste for the electrode layer 24.

Further, 10 g of palladium powder having an average particle size of 1.5 μm and 0.9 g of ethyl cellulose dissolved in 9.1 g of butyl carbitol were placed in a stirrer.
By stirring for 10 hours, a second conductive paste for the electrode layer 23 is obtained.

Thereafter, the first conductive paste is applied to one entire surface of the green sheet and dried. on the other hand,
Applying the second conductive paste to one surface of another green sheet so as to form a pattern of the electrode layer 24;
dry. Next, a plurality of green sheets to which the second conductive paste has been applied are stacked with the application surface facing upward, and a first green sheet having the first conductive paste applied to both upper and lower surfaces of the laminate, and A green sheet to which the conductive paste is not applied is laminated on the outside.
The laminate is then heated at a temperature of about 50 ° C. in the thickness direction for about 4 hours.
A pressure of 0 tons is applied for crimping. Thereafter, the laminate is cut into a lattice to obtain about 50 laminated chips.

Next, the laminated chip is placed in a furnace that can be fired in an atmosphere, and heated to 600 ° C. in the air to fire the organic binder. From 600 ° C. to a firing temperature of 1150 ° C. (maximum temperature) and hold for 3 hours. Thereafter, the temperature is lowered to 600 ° C. at a rate of 100 ° C./hour and cooled to room temperature to obtain a sintered body chip.

Lastly, the sintered chip was made to have a particle size of 0.5 m.
After performing barrel polishing for about 10 minutes using zirconia of about m as a medium, the electrode layer 23 exposed in the lamination section is subjected to solder plating to obtain a multilayer chip capacitor 21.

According to the multilayer chip capacitor 21,
The electrode layer 23 is exposed on the laminated cross section of the multilayer chip capacitor 21, and the electrode layer 23 can be directly mounted on the land 11 of the circuit board 10. In this mounting, the land 11 can be mounted if it has a width equal to or greater than the thickness of the electrode layer 23. For this reason, the solder fillet formed from the land 11 to the electrode layer 23 can be made extremely small, so that when mounting a plurality of multilayer chip capacitors 21, the interval between them can be reduced. In particular, when the multilayer chip capacitors 21 are juxtaposed in the laminating direction, they can be mounted on the circuit board 10 without any gap or with a slight gap. Therefore, the mounting density on the circuit board 10 can be improved. Further, since the multilayer chip capacitor 21 does not use the electrode layer 24 as a connection terminal electrode, it is not necessary to form the electrode layer 24 thick for the purpose of improving strength. This allows
Since the number of layers can be increased by reducing the thickness, the capacitance can be increased.

In this embodiment, a multilayer chip capacitor is exemplified. However, a multilayer chip inductor can be manufactured by forming the electrode layer 34 in a pattern as shown in FIG. 9, for example. That is, the pattern of the electrode layer 34 is formed so that the coil is formed in the laminating direction, and the electrode chip 34 is connected between the electrode layers 34 and the electrode layer 33 exposed in the lamination cross section by the through hole H, thereby forming the multilayer chip inductor. 31 can be manufactured.

The multilayer electronic component according to the present invention has been described as the first and second embodiments. As shown in FIG. 10, a resistance layer is provided on the outermost layer of the multilayer electronic component. A CR array or the like can also be configured. In FIG. 10, reference numeral 41 denotes a CR array 41, which further includes a resistive film R on the outer surface of the outermost dielectric layer 2 of the multilayer chip capacitor 1 according to the first embodiment. Is attached. The resistive film R is formed by applying a resistive paste containing a metal powder such as ruthenium oxide, SiO ₂ , Zno, TaN or the like as a main component by screen printing and then baking. This CR
The array 41 has the lands 12a and 12a on the circuit board 10 in addition to the function as the multilayer chip capacitor 1 described above.
b, and functions as a predetermined resistor between the lands 13a and 13b. According to the CR array 41, the mounting density of electronic components can be further improved. The resistance film R may be formed by screen printing, or may be formed by pressing or attaching a sheet-shaped resistance sheet to the multilayer chip capacitor 1.

[0051]

As described in detail above, according to the present invention,
Since the conductor pattern exposed on the laminated cross section of the multilayer electronic component is directly used as a terminal electrode for connection to the circuit board, one laminated cross section is on a land provided on the surface of the circuit board facing the circuit board. , And can be mounted by soldering. In this mounting, the land is
If the width is equal to or larger than the thickness of the conductor pattern of the multilayer electronic component, mounting becomes possible, so that a solder fillet formed from the land to the conductor pattern can be made smaller. Thereby, when mounting a plurality of multilayer electronic components, the component interval can be reduced. In particular, when a plurality of multilayer electronic components are mounted with their side surfaces where the conductor patterns are not exposed to face each other, that is, when mounted side by side in the lamination direction, the multilayer electronic components are mounted. They can be arranged without gaps or with small gaps. Thereby, the mounting density on the circuit board can be improved.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a multilayer chip capacitor according to a first embodiment.

FIG. 2 is a plan view illustrating a mounting method of the multilayer chip capacitor according to the first embodiment.

FIG. 3 is a schematic perspective view illustrating a mounting method of the multilayer chip capacitor according to the first embodiment.

FIG. 4 is a plan view illustrating another mounting method of the multilayer chip capacitor according to the first embodiment.

FIG. 5 is an exploded perspective view of another multilayer chip capacitor according to the first embodiment.

FIG. 6 is a schematic perspective view illustrating a mounting method of another multilayer chip capacitor according to the first embodiment.

FIG. 7 is an exploded perspective view of a multilayer chip capacitor according to a second embodiment.

FIG. 8 is a schematic perspective view illustrating a mounting method of the multilayer chip capacitor according to the second embodiment.

FIG. 9 is an exploded perspective view of the multilayer chip inductor according to the second embodiment.

FIG. 10 is a schematic perspective view of a CR array according to the first embodiment.

FIG. 11 is an exploded perspective view of a conventional multilayer chip capacitor.

[Explanation of symbols]

1, 21: multilayer chip capacitor; 2, 22, 32: dielectric layer; 3, 23, 24: electrode layer; 10: circuit board;
Reference numeral 1 represents a land and 31 represents a multilayer chip inductor.

Claims (1)

[Claims] 1. A substantially rectangular parallelepiped laminating body manufactured by cutting a laminated body formed by alternately laminating a plurality of ceramic sheets and conductor patterns into predetermined dimensions, and mounting one laminating cross section to face a circuit board. In the electronic component, the conductive pattern is exposed as a terminal electrode for connection to a circuit board in a laminated cross section of the multilayer electronic component.