JPH1167965A - Manufacture of multilayered interconnection board for mounting semiconductor element - Google Patents
Manufacture of multilayered interconnection board for mounting semiconductor elementInfo
- Publication number
- JPH1167965A JPH1167965A JP9230074A JP23007497A JPH1167965A JP H1167965 A JPH1167965 A JP H1167965A JP 9230074 A JP9230074 A JP 9230074A JP 23007497 A JP23007497 A JP 23007497A JP H1167965 A JPH1167965 A JP H1167965A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- resin
- semiconductor element
- board
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 31
- 239000000853 adhesive Substances 0.000 claims abstract description 30
- 230000001070 adhesive effect Effects 0.000 claims abstract description 30
- 239000011256 inorganic filler Substances 0.000 claims abstract description 11
- 229910003475 inorganic filler Inorganic materials 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 abstract description 11
- 239000000843 powder Substances 0.000 description 6
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 5
- -1 polyethylene Polymers 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 229920001169 thermoplastic Polymers 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004416 thermosoftening plastic Substances 0.000 description 3
- 239000002966 varnish Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- BVYPJEBKDLFIDL-UHFFFAOYSA-N 3-(2-phenylimidazol-1-yl)propanenitrile Chemical compound N#CCCN1C=CN=C1C1=CC=CC=C1 BVYPJEBKDLFIDL-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- MXRIRQGCELJRSN-UHFFFAOYSA-N O.O.O.[Al] Chemical compound O.O.O.[Al] MXRIRQGCELJRSN-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子搭載用
多層配線板の製造方法に関する。The present invention relates to a method for manufacturing a multilayer wiring board for mounting a semiconductor element.
【０００２】[0002]
【従来の技術】一般に、キャビティー仕様ＢＧＡ又はキ
ャビティー仕様ＰＧＡといわれている半導体素子搭載用
パッケージは、半導体素子を搭載するためのキャビティ
ー２２を有する多層配線板２１である（図２参照）。こ
のようなキャビティー２２を有する多層配線板２１は、
ベース配線板１１の上に、キャビティー用穴１２を設け
た２枚の穴あき配線板１３を、同じくキャビティー用穴
１４を設けた接着シート１５を介して重ね、２枚の鏡板
１６の間に挿んで加熱加圧することにより積層成形して
製造されていた。（図１参照） なお、図１及び図２は、穴あき配線板１３を２枚重ねと
して、ワイヤボンディング用の段部２３を形成した例を
示す。キャビティー２２内には、半導体素子と回路配線
とを接続するための端子となる回路が露出している。こ
のため、接着シート１５としては、加熱加圧するとき、
樹脂がキャビティー２２内に流出しないように、樹脂流
れが小さいローフロープリプレグが使用されていた。2. Description of the Related Art A package for mounting a semiconductor element, which is generally called a cavity specification BGA or a cavity specification PGA, is a multilayer wiring board 21 having a cavity 22 for mounting a semiconductor element (see FIG. 2). . The multilayer wiring board 21 having such a cavity 22 is
On the base wiring board 11, two perforated wiring boards 13 provided with holes 12 for cavities are laminated via an adhesive sheet 15 also provided with holes 14 for cavities. It was manufactured by laminating and molding by inserting and heating and pressing. FIGS. 1 and 2 show an example in which two perforated wiring boards 13 are stacked to form a step 23 for wire bonding. In the cavity 22, a circuit serving as a terminal for connecting the semiconductor element and the circuit wiring is exposed. For this reason, when the adhesive sheet 15 is heated and pressed,
In order to prevent the resin from flowing into the cavity 22, a low-flow prepreg having a small resin flow has been used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うに樹脂流れの小さいローフロープリプレグを用いて
も、キャビティー２２内への樹脂流出を皆無とすること
はできなかった。キャビティー２２内に樹脂が流出する
と、キャビティー２２内に露出している回路の一部を覆
ってしまい、その部分については、半導体素子との接続
に使用することができない。このため、従来は、樹脂流
出をある程度見込んでキャビティー２２の寸法を半導体
素子の搭載に必要な大きさより大きめにする必要があ
り、小型化の障害となっていた。本発明は、ベース配線
板と穴あき配線板とを接着シートを介して鏡板の間に挿
んで加熱加圧する半導体素子搭載用多層配線板の製造方
法において、接着シートからの樹脂流出を極力小さくす
ることを課題とするものである。However, even if such a low-flow prepreg having a small resin flow is used, it has not been possible to eliminate resin outflow into the cavity 22 at all. When the resin flows into the cavity 22, it covers a part of the circuit exposed in the cavity 22, and the part cannot be used for connection with the semiconductor element. For this reason, conventionally, it is necessary to make the size of the cavity 22 larger than the size required for mounting the semiconductor element in consideration of resin outflow to some extent, which has been an obstacle to miniaturization. An object of the present invention is to provide a method for manufacturing a multilayer wiring board for mounting a semiconductor element, in which a base wiring board and a perforated wiring board are inserted between end plates via an adhesive sheet and heated and pressed, in which resin outflow from the adhesive sheet is minimized. Is the subject.
【０００４】[0004]
【課題を解決するための手段】本発明は、ベース配線板
１１及び半導体素子搭載用のキャビティー用穴１２を設
けた穴あき配線板１３を、キャビティー用穴１４を設け
た接着シート１５を介して重ね、加熱加圧して積層する
半導体素子搭載用多層配線板の製造方法において、加熱
加圧して積層したときに樹脂がキャビティー用穴内に流
れ出ない量の無機フィラーを樹脂に含有させた接着シー
トを用いることを特徴とする半導体素子搭載用多層配線
板の製造方法である。According to the present invention, a perforated wiring board 13 provided with a base wiring board 11 and a cavity hole 12 for mounting a semiconductor element, and an adhesive sheet 15 provided with a cavity hole 14 are provided. In a method for manufacturing a multilayer wiring board for mounting semiconductor elements, which is laminated by heating and pressurizing, the resin contains an inorganic filler in an amount such that the resin does not flow into the cavity hole when laminated by heating and pressurizing. A method for manufacturing a multilayer wiring board for mounting a semiconductor element, comprising using a sheet.
【０００５】[0005]
【発明の実施の形態】ベース配線板１１、穴あき配線板
１３としては、ガラス布を基材としこれに熱硬化性樹脂
ワニスを含浸乾燥して得られるプリプレグと、金属はく
例えば銅はくとを積層し、硬化させて金属張り積層板を
得、この金属張り積層板に回路加工や穴あけ加工したも
のが使用される。熱硬化性樹脂としては、エポキシ樹脂
が電気的特性や価格の面から好ましい。耐熱性など特に
必要があるときには、ポリイミド樹脂、ビスマレイミド
−トリアジン樹脂などの熱硬化性樹脂も使用することが
できる。DESCRIPTION OF THE PREFERRED EMBODIMENTS As a base wiring board 11 and a perforated wiring board 13, a prepreg obtained by impregnating and drying a glass cloth as a base material with a thermosetting resin varnish, and a metal foil such as a copper foil are used. Are laminated and cured to obtain a metal-clad laminate, and the metal-clad laminate is subjected to circuit processing and drilling. As the thermosetting resin, an epoxy resin is preferable in terms of electrical characteristics and cost. When heat resistance is particularly necessary, a thermosetting resin such as a polyimide resin or a bismaleimide-triazine resin can also be used.
【０００６】接着シート１５としては、前記ベース配線
板１１又は穴あき配線板１３の製造に用いたプリプレグ
又は、エポキシ樹脂にＮＢＲ等のゴム、アクリル樹脂、
ポリビニルブチラール、フェノール樹脂等を配合してフ
ィルム状に製膜して得られるフィルム状接着剤を使用す
ることができる。The adhesive sheet 15 may be a prepreg used for manufacturing the base wiring board 11 or the perforated wiring board 13 or a rubber such as NBR, an acrylic resin, or an epoxy resin.
A film-like adhesive obtained by blending polyvinyl butyral, a phenolic resin and the like to form a film can be used.
【０００７】接着シート１５の樹脂に含有させる無機フ
ィラーとしては、チョップドストランド、シリカ粉、酸
化チタン粉、マイカ粉、水酸化アルミニウム粉など、電
気絶縁性の良好な粉末材料が挙げられる。加熱加圧して
積層したときに樹脂がキャビティー用穴内に流れ出ない
ようにするためには、樹脂と無機フィラーとの合計量に
対して、無機フィラーを７５体積％以上含有させるのが
好ましい。無機フィラーの含有量が多くなると、接着シ
ート１５を加熱加圧たときの樹脂流れが小さくなるから
である。無機フィラーの含有量の上限はシート形成の観
点から制限されるがおよそ９５体積％である。無機フィ
ラーの含有量の最適値は、樹脂の組成、成形条件等によ
っても異なり、最適な条件は実験等によって定められ
る。このように多量の無機フィラーを含有させることか
ら、無機フィラーとしては粒径が１〜５０μｍで長径／
短径の比が５以下であるのが好ましい。粒径が１μｍ未
満であると混合が困難となり、５０μｍを超えると均一
に分散させることが困難となる傾向にある。また、長径
／短径の比が５を超えると、多量に含有させることが困
難となる傾向にある。Examples of the inorganic filler to be contained in the resin of the adhesive sheet 15 include powder materials having good electrical insulation such as chopped strands, silica powder, titanium oxide powder, mica powder, and aluminum hydroxide powder. In order to prevent the resin from flowing into the cavity hole when laminating by heating and pressing, it is preferable to contain the inorganic filler in an amount of 75% by volume or more based on the total amount of the resin and the inorganic filler. This is because when the content of the inorganic filler increases, the resin flow when the adhesive sheet 15 is heated and pressed decreases. The upper limit of the content of the inorganic filler is limited from the viewpoint of sheet formation, but is about 95% by volume. The optimum value of the content of the inorganic filler varies depending on the composition of the resin, molding conditions, and the like, and the optimum conditions are determined by experiments and the like. Since such a large amount of inorganic filler is contained, the inorganic filler has a particle diameter of 1 to 50 μm and a long diameter /
The ratio of the minor axis is preferably 5 or less. If the particle size is less than 1 μm, mixing tends to be difficult, and if it exceeds 50 μm, it tends to be difficult to disperse uniformly. On the other hand, if the ratio of major axis / minor axis exceeds 5, it tends to be difficult to incorporate a large amount.
【０００８】ベース配線板１１及び半導体素子搭載用の
キャビティー用穴１２を設けた穴あき配線板１３を、キ
ャビティー用穴１４を設けた接着シート１５を介して重
ね、加熱加圧するときの条件は、温度１５０〜１８０
℃、圧力３〜２０ＭＰａの範囲とされるのが好ましい。
温度が１５０℃未満であると、接着強度が不足し、１８
０℃を超えると樹脂がキャビティー用穴内に流れ出す傾
向が大となる傾向にある。また、圧力が３ＭＰａ未満で
あると接着強度が不足し、２０ＭＰａを超えると接着シ
ートが破断する傾向にある。このことから、温度１６０
〜１７５０℃、圧力１０〜１８ＭＰａの範囲とされるの
がより好ましい。Conditions for laminating a base wiring board 11 and a perforated wiring board 13 provided with a cavity hole 12 for mounting a semiconductor element via an adhesive sheet 15 provided with a cavity hole 14 and heating and pressurizing. Is the temperature of 150 to 180
C. and a pressure in the range of 3 to 20 MPa are preferable.
When the temperature is lower than 150 ° C., the adhesive strength becomes insufficient,
If the temperature exceeds 0 ° C., the resin tends to flow out into the cavity holes. When the pressure is less than 3 MPa, the adhesive strength is insufficient, and when it exceeds 20 MPa, the adhesive sheet tends to break. From this, the temperature 160
It is more preferable that the pressure is in the range of 1 to 1750 ° C and the pressure is 10 to 18 MPa.
【０００９】ベース配線板１１及び半導体素子搭載用の
キャビティー用穴１２を設けた穴あき配線板１３を、キ
ャビティー用穴１４を設けた接着シート１５を介して重
ね、加熱加圧するとき、これらの構成材料を２枚の鏡板
の間に挿むが、この鏡板としては、配線板分野の積層成
形で使用されているものがそのまま用いられ、例えば、
厚さ０．５〜５ｍｍの金属板が使用される。金属板とし
ては、耐食性の観点から、ステンレス板が好適に用いら
れる。When a base wiring board 11 and a perforated wiring board 13 provided with a cavity hole 12 for mounting a semiconductor element are stacked via an adhesive sheet 15 provided with a cavity hole 14, and these are heated and pressed, Is inserted between two end plates. As the end plate, those used in laminate molding in the field of wiring boards are used as they are, for example,
A metal plate having a thickness of 0.5 to 5 mm is used. As the metal plate, a stainless steel plate is preferably used from the viewpoint of corrosion resistance.
【００１０】さらに、鏡板と穴あき配線板１３との間に
は、クッション材１９としてポリエチレンシートのよう
な熱可塑性シート１７を、三フッ化ポリエチレンフィル
ム１８で包んで配置するのが好ましい。成形時に熱可塑
性シート１７が溶融流動してキャビティー２２の内部を
埋めてキャビティー２２内への圧力伝達を良好にするか
らである。Furthermore, it is preferable that a thermoplastic sheet 17 such as a polyethylene sheet is wrapped with a polyethylene trifluoride film 18 as a cushion member 19 between the mirror plate and the perforated wiring board 13. This is because the thermoplastic sheet 17 melts and flows at the time of molding and fills the inside of the cavity 22 to improve the pressure transmission into the cavity 22.
【００１１】[0011]
実施例１ 接着シートの作製 ビスフェノールＡノボラック型エポキシ樹脂（大日本イ
ンキ化学工業株式会社製、エピクロンＮ−８６８（商品
名）を使用した）５０部（重量部、以下同じ）ビスフェ
ノールＡノボラック樹脂（油化シェルエポキシ株式会
社、ＹＬＨ−１２９（商品名）を使用した）４０部、ブ
ロム化ビスフェノールＡ型エポキシ樹脂（住友化学工業
株式会社、ＥＳＢ−４００（商品名）を使用した）５０
部及び１−シアノエチル−２−フェニルイミダゾール１
部をメチルエチルケトン９０部に溶解してワニスを調製
した。このワニスに、フィラメント径５μｍのガラス繊
維を平均粒径１０μｍになるように粉砕して得られたガ
ラスパウダーを、樹脂固形分とガラスパウダーとの合計
量に対して８５体積％混合し分散させた。これをＭＩＬ
＃１０８０のガラスクロスに固形付着分が６０重量％と
なるように含浸乾燥させ、接着シート材料を作製した。
この接着シート材料を１００ｍｍ×１００ｍｍにカット
し、中央に１０ｍｍ×１０ｍｍのキャビティー用穴を打
ち抜き加工により形成して接着シートＡを作製した。同
様にして中央に１５ｍｍ×１５ｍｍのキャビティー用穴
を打ち抜き加工により形成して接着シートＢを作製し
た。Example 1 Preparation of Adhesive Sheet Bisphenol A novolak type epoxy resin (using Epicron N-868 (trade name) manufactured by Dainippon Ink and Chemicals, Inc.) 50 parts (parts by weight, the same applies hereinafter) bisphenol A novolak resin (oil) Shell Epoxy Co., Ltd., YLH-129 (trade name) 40 parts, brominated bisphenol A type epoxy resin (Sumitomo Chemical Co., Ltd., ESB-400 (trade name)) 50
Part and 1-cyanoethyl-2-phenylimidazole 1
Was dissolved in 90 parts of methyl ethyl ketone to prepare a varnish. A glass powder obtained by pulverizing glass fiber having a filament diameter of 5 μm so as to have an average particle diameter of 10 μm was mixed and dispersed in the varnish with 85% by volume based on the total amount of the resin solid content and the glass powder. . This is MIL
The # 1080 glass cloth was impregnated and dried so that the solid content was 60% by weight to prepare an adhesive sheet material.
This adhesive sheet material was cut into 100 mm × 100 mm, and a hole for cavity of 10 mm × 10 mm was formed in the center by punching to prepare an adhesive sheet A. In the same manner, a 15 mm × 15 mm cavity hole was formed in the center by punching to produce an adhesive sheet B.
【００１２】ベース配線板及び穴あき配線板の作製 銅はく厚さが１８μｍのガラス繊維布基材エポキシ樹脂
両面銅張積層板（日立化成工業株式会社製のＭＣＬ Ｅ
−６７（商品名）を使用した）に回路加工を行い、１０
０ｍｍ×１００ｍｍにカットしてベース配線板を作製し
た。ベース配線板と同じ両面銅張積層板に回路加工を行
い、１００ｍｍ×１００ｍｍにカットし、中央に１０ｍ
ｍに×１０ｍｍのキャビティー用穴を打ち抜き加工によ
り形成して、穴あき配線板Ａを作製した。同様にしてキ
ャビティー用穴の寸法が、１５ｍｍ×１５ｍｍの穴あき
配線板Ｂを作製した。Production of Base Wiring Board and Perforated Wiring Board Copper-foiled double-sided copper-clad laminate of glass fiber cloth base material with a copper foil thickness of 18 μm (MCLE manufactured by Hitachi Chemical Co., Ltd.)
-67 (trade name) was used, and the circuit was processed.
The substrate was cut into 0 mm x 100 mm to produce a base wiring board. Circuit processing is performed on the same double-sided copper-clad laminate as the base wiring board, cut into 100 mm x 100 mm, and 10 m in the center.
A hole for cavity having a size of 10 mm was formed in the m by punching, and a perforated wiring board A was produced. Similarly, a perforated wiring board B having a cavity size of 15 mm × 15 mm was prepared.
【００１３】半導体素子搭載用多層配線板の作製 厚さ２ｍｍのステンレス鏡板の上に、ベース配線板、接
着シートＡ、穴あき配線板Ａ、接着シートＢ、穴あき配
線板Ｂ、の順に重ね、その上にクッション材を介して厚
さ２ｍｍのステンレス鏡板を重ね、温度１７０℃、圧力
１７ＭＰａで、９０分間加熱加圧して半導体素子搭載用
多層配線板を作製した。なお、クッション材は、厚さ１
００μｍの三フッ化ポリエチレンフィルム２枚の間に、
厚さ１．０ｍｍのポリエチレンシートを挿んで用いた。Preparation of a Multilayer Wiring Board for Mounting a Semiconductor Element A base wiring board, an adhesive sheet A, a perforated wiring board A, an adhesive sheet B, and a perforated wiring board B are stacked on a stainless steel mirror plate having a thickness of 2 mm in this order. A stainless steel end plate having a thickness of 2 mm was stacked thereon via a cushion material, and heated and pressed at a temperature of 170 ° C. and a pressure of 17 MPa for 90 minutes to produce a multilayer wiring board for mounting a semiconductor element. The cushion material has a thickness of 1
Between two 00 μm polyethylene fluoride films,
A polyethylene sheet having a thickness of 1.0 mm was inserted and used.
【００１４】得られた半導体素子搭載用多層配線板につ
いて、キャビティー内への樹脂流出を測定したところは
１５０μｍであり、半導体素子の搭載及びワイヤボンデ
イングによる半導体素子と回路配線との接続を支障なく
行うことができた。With respect to the obtained multilayer wiring board for mounting a semiconductor element, the outflow of the resin into the cavity was measured to be 150 μm, and the mounting of the semiconductor element and the connection between the semiconductor element and the circuit wiring by wire bonding were not hindered. Could be done.
【００１５】比較例 接着シート材料として、基材厚さが０．０５ｍｍ、付着
樹脂量６５重量％、樹脂流れ（ＪＩＳ Ｃ ６５２１に
規定される）が１０％のローフロープリプレグ（日立化
成工業株式会社製、ＧＥＡ−６７Ｎ（商品名）を使用し
た）を用いたほかは、実施例１と同様にして半導体素子
搭載用多層配線板を作製した。COMPARATIVE EXAMPLE As an adhesive sheet material, a low-flow prepreg having a base material thickness of 0.05 mm, an attached resin amount of 65% by weight, and a resin flow (defined by JIS C 6521) of 10% (Hitachi Chemical Industries, Ltd.) And GEA-67N (trade name) was used in the same manner as in Example 1 to produce a multilayer wiring board for mounting semiconductor elements.
【００１６】得られた半導体素子搭載用多層配線板につ
いて、キャビティー内への樹脂流出を測定したところは
３００μｍであり、半導体素子の搭載及びワイヤボンデ
イングによる半導体素子と回路配線との接続が不可能で
あった。With respect to the obtained multilayer wiring board for mounting a semiconductor element, the outflow of the resin into the cavity was measured to be 300 μm, and it was impossible to mount the semiconductor element and connect the semiconductor element to the circuit wiring by wire bonding. Met.
【００１７】[0017]
【発明の効果】本発明の製造方法によれば、接着シート
からキャビティー内への樹脂流出が小さい半導体素子搭
載用多層配線板を得ることができる。According to the manufacturing method of the present invention, it is possible to obtain a multilayer wiring board for mounting a semiconductor element, in which a small amount of resin flows out of the adhesive sheet into the cavity.
【図１】本発明の一実施例に関する断面図である。FIG. 1 is a cross-sectional view related to one embodiment of the present invention.
【図２】半導体素子搭載用多層配線板の一例を示す断面
図である。FIG. 2 is a cross-sectional view illustrating an example of a multilayer wiring board for mounting a semiconductor element.
１１ ベース配線板 １２ キャビティー用穴 １３ 穴あき配線板 １４ キャビティー用穴 １５ 接着シート １６ 鏡板 １７ 熱可塑性シート １８ 三フッ化ポリエチレンフィルム １９ クッション材 ２１ 多層配線板 ２２ キャビティー ２３ ワイヤボンディング用の段部 DESCRIPTION OF SYMBOLS 11 Base wiring board 12 Cavity hole 13 Perforated wiring board 14 Cavity hole 15 Adhesive sheet 16 Mirror plate 17 Thermoplastic sheet 18 Polyethylene trifluoride film 19 Cushion material 21 Multilayer wiring board 22 Cavity 23 Wire bonding step Department
Claims (1)
ャビティー用穴を設けた穴あき配線板を、キャビティー
用穴を設けた接着シートを介して重ね、加熱加圧して積
層する半導体素子搭載用多層配線板の製造方法におい
て、加熱加圧して積層したときに樹脂がキャビティー用
穴内に流れ出ない量の無機フィラーを樹脂に含有させた
接着シートを用いることを特徴とする半導体素子搭載用
多層配線板の製造方法。1. A semiconductor element mounting wherein a base wiring board and a perforated wiring board provided with a cavity hole for mounting a semiconductor element are laminated via an adhesive sheet provided with a cavity hole, and heated and pressed to be laminated. A method for manufacturing a multilayer wiring board for use, comprising: using an adhesive sheet containing an inorganic filler in the resin in such an amount that the resin does not flow into the cavity hole when laminated by heating and pressurizing. Manufacturing method of wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9230074A JPH1167965A (en) | 1997-08-26 | 1997-08-26 | Manufacture of multilayered interconnection board for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9230074A JPH1167965A (en) | 1997-08-26 | 1997-08-26 | Manufacture of multilayered interconnection board for mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1167965A true JPH1167965A (en) | 1999-03-09 |
Family
ID=16902146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9230074A Pending JPH1167965A (en) | 1997-08-26 | 1997-08-26 | Manufacture of multilayered interconnection board for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1167965A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100367729B1 (en) * | 2000-02-17 | 2003-01-10 | 주식회사 글로텍 | Multiple line grid array package |
| KR100385709B1 (en) * | 2001-07-12 | 2003-05-27 | 삼성전기주식회사 | Sheet type resin for filling and preparing method of multilayer printed circuit board using the same |
| JP2009060017A (en) * | 2007-09-03 | 2009-03-19 | Panasonic Corp | 3D printed circuit board |
| JPWO2008146487A1 (en) * | 2007-05-29 | 2010-08-19 | パナソニック株式会社 | Circuit board and manufacturing method thereof |
| US8253033B2 (en) | 2007-09-03 | 2012-08-28 | Panasonic Corporation | Circuit board with connection layer with fillet |
-
1997
- 1997-08-26 JP JP9230074A patent/JPH1167965A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100367729B1 (en) * | 2000-02-17 | 2003-01-10 | 주식회사 글로텍 | Multiple line grid array package |
| KR100385709B1 (en) * | 2001-07-12 | 2003-05-27 | 삼성전기주식회사 | Sheet type resin for filling and preparing method of multilayer printed circuit board using the same |
| JPWO2008146487A1 (en) * | 2007-05-29 | 2010-08-19 | パナソニック株式会社 | Circuit board and manufacturing method thereof |
| JP4935823B2 (en) * | 2007-05-29 | 2012-05-23 | パナソニック株式会社 | Circuit board and manufacturing method thereof |
| US8446736B2 (en) | 2007-05-29 | 2013-05-21 | Panasonic Corporation | Circuit board and manufacturing method thereof |
| JP2009060017A (en) * | 2007-09-03 | 2009-03-19 | Panasonic Corp | 3D printed circuit board |
| US8253033B2 (en) | 2007-09-03 | 2012-08-28 | Panasonic Corporation | Circuit board with connection layer with fillet |
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