JPH1185119A - Multi-sync circuit of monitor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the capacity of a frame memory to the absolute minimum. SOLUTION: This multi-sync circuit converts a signal so that an input video signal having resolution of H1 ×V1 (H1 : the number of columns of a screen, V1 : the number of rows) is displayed by keeping resolution of the input video signal at almost the center of a dot matrix display having resolution of H2 ×V2 (H2 >=H1 m V2 >=V1 ). A FIFO(first in first out) memory of a dual port is used as a frame memory 1 storing temporarily the input video signal, reading out the signal, and sending out it to a display. The capacity N is selected to N>=V1 (1-V1 /V2 ) H1 ab (when color display is used, a=3, when monochrome display is used, a=1, b: the number of bits of data of one pixel). A control circuit resets a write-address pointer to a zero address for each X=V1 (1-V1 /V2 ) row of a signal written in the memory 1, a read-cycle is started at the time of writing data of X rows in the memory 1, a read-address pointer is reset to a zero address whenever data of X rows is read out from the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In recent years, LCDs have been increasingly used simply as monitors, unlike laptop computers. When used as a monitor, there are various resolutions used by the user, such as VGA and SVGA, which do not always match the resolution of the LCD panel. Therefore, the resolution of the input signal
A so-called multi-sync circuit for converting a signal to match the resolution of the panel is required.

[0002] There are roughly two types of display conversion methods using the multi-sync circuit. One of them is
This is a method of expanding the input signal to the entire effective display area of the LCD panel (EXPAND mode), and the other is a method of displaying the input signal near the center of the LCD panel at the same resolution. For example, if the input signal is VGA (dot configuration is 640 columns x 480 rows) and the LCD is XGA (dot configuration is 1024 columns x 768 rows), the VGA is enlarged and displayed 1.6 times vertically and horizontally. Is the EXPAND mode, and 640 × 480 at the center of 1024 × 768 dots
The display in the dot area is the NON-EXPAND mode (FIG. 5).

In the EXPAND mode, a frame memory is not required, but in the NON-EXPAND mode, a frame memory is required. However, since the frame memory is expensive, it is important to reduce this number. The present invention relates to N
The present invention relates to a multi-sync circuit having a minimum necessary frame memory in an ON-EXPAND mode.

[0004]

2. Description of the Related Art Conventionally, one frame of an input signal is
All data has been written to the frame memory (write cycle), and after the writing is completed, data of the n-th frame is read (read cycle) in the (n + 1) -th frame. The memory used is mainly a dual port FIFO (First InFirst Ou).
t) A memory which has both a write port and a read port and can be read simultaneously while writing. That is, while reading the data of the n-th frame, the data of the (n + 1) -th frame can be written at the same time.

For example, when an XGA LCD panel is used as a monitor, the input signal is VGA or SVGA (8
In the case of (00 × 600), all the data is written to the frame memory. Therefore, the data of one dot is R
The capacity N of the frame memory in the case of 8 bits for each color of GB is N = 800 × 600 × 8 × 3 = 11520000 bits (=
1.37 Mbyte) When N is expressed in bytes, it is 11520000
/ 8 = 1440000 bytes. Divide it by 2 ¹⁰ = 1024 to convert it to cabit and get 1440000/10
24 = 1406.25 kbytes. Furthermore, when converted to megabytes, it becomes 1406.25 / 1024 = 1.37 Mbytes. Therefore, 512 kB as a frame memory
Three (kebyte) FIFO memories are required.

[0006]

Since the frame memory is expensive, the present invention seeks to minimize its capacity.

[0007]

[Means for Solving the Problems]

 (1) In the invention of claim 1, the resolution is H₁× V₁(H₁Is
Number of columns in one screen, V₁Is the number of lines) of the input video signal
Is H_Two× V_Two(But H_Two≧ H₁, V_Two≧ V ₁Toss
Near the center of the dot matrix display screen
Signal to be displayed at the resolution of the input video signal.
A multi-sync circuit of a monitor device. In claim 1
In particular, it temporarily stores the input video signal, and
Is read out and sent to the display as a frame memory.
And a dual-port FIFO (First In F
first Out) memory and its FIFO memory
The capacity N of N ≧ V₁(1-V₁/ V_Two) H₁ab
A = 3 for color display and a = for monochrome display
1 and b is the number of data bits per pixel)
I do.

(2) In the second aspect of the present invention, in (1), X = X of the input video signal to be written into the frame memory.
The read cycle is started when the write address pointer is reset to a zero address for each V ₁ (1-V ₁ / V ₂ ) row and the data for X rows is written to the frame memory. A control circuit is provided for resetting the read address pointer to a zero address each time data is read.

(3) In the invention according to claim 3, the resolution is H₁×
V₁Input video signal with resolution H _Two× V_Two(However,
H_Two≧ H₁, V_Two≧ V₁Dot matrix table
Near the center of the display screen, keep the resolution of the input video signal
A multi-synth monitor that converts signals to display
Circuit. In claim 3, the input video signal is
Time, and read the stored signal to the display.
As the frame memory to be sent, the single port
1. Using the second FIFO memory, the first FIFO memory
Capacity N₁To N₁≧ V₁ ^Two(V_Two-V₁) H₁ab / (V
_Two ^Two+ V₁V_Two-V ₁ ^Two), The capacity N of the second FIFO memory
_TwoTo N_Two≧ V₁V_Two(V_Two-V₁) H₁ab / (V_Two ^Two
+ V₁V_Two-V₁ ^Two).

(4) The invention according to claim 4 is characterized in that (3)
In the first cycle, the video signal is stored in the first FIFO memory.
X = V₁ ^Two(V_Two-V₁) / (V_Two ^Two+ V₁V_Two-V₁ ^Two)
The data for the row is written, and in the second cycle, the second FIFO
Video signal Y = V in O memory ₁V_Two(V_Two-V₁) /
(V_Two ^Two+ V₁V_Two-V₁ ^Two) When writing data for a row,
Then, data of X rows in the first FIFO memory is read out,
In the third cycle, data for Y rows of the second FIFO memory
And Y (V) is stored in the first FIFO memory. ₁/ V
_Two) Write the data for the row, and in the fourth cycle,
Y (V₁/ V_Two) Read the data for the row
At the same time, Y (V ₁/ V_Two)^Two
The data for the row is written, and similarly, the first and second FI
A control circuit for writing / reading the FO memory is provided.
You.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) When using a dual-port FIFO memory as the frame memory (A1) Basic concept Since the dual-port FIFO memory can be read at the same time as writing, reading must be started before writing all data for one frame is completed. There is no problem in operation. Therefore, after writing data to some extent, reading is started, and previously written data is read while writing new data. Once the data is read, the data becomes unnecessary. Therefore, even if the data is rewritten, the display is not affected. With such control, the capacity of the frame memory can be reduced (FIG. 3). However, even in such control, the reading must be started at a timing at which the read address pointer does not pass the write address pointer. Next, an example of displaying an input signal of the VGA on the LCD of the XGA will be described.

A normal VGA signal has a vertical synchronization frequency of 60.
Hz, horizontal synchronization frequency 32 kHz, dot clock 25
It is a signal of 640 dots horizontally and 480 dots vertically in MHz. This is converted into an XGA signal, that is, a signal of 1024 horizontal dots and 768 vertical dots at a vertical synchronization frequency of 60 Hz, a horizontal synchronization frequency of 50 kHz, and a dot clock of 65 MHz.

In the write cycle of the frame memory 1 shown in FIG. 1, data of coordinates (0, 0) in the input dot data is written to the memory at the write address 0, and thereafter, 25 MHz
Each time one dot clock is input, the write address is increased by one and data is written one after another. A write address pointer indicates where the write address is at a certain time.

Similarly, in the read cycle, the data at the coordinates (0, 0) in the output dot data is read from the memory at the read address 0, and thereafter, every time a 65 MHz dot clock is input, the read address is increased by one and the read address is increased one after another. Read the data. A read address pointer indicates where the read address is at a certain time. However, if 640 addresses are advanced in one horizontal period instead of reading continuously at 65 MHz, the read address pointer stops until the beginning of the next horizontal period.

It is assumed that the write address pointer is at the XW address at a certain time T1 during the writing of the (n + 1) th frame. At this time, data of the (n + 1) th frame has already been written to an address smaller than the XW address, but data of the nth frame still remains at an address larger than the XW address. At this time, the read address pointer is set to the address X smaller than the XW address.
Assume that you are at the R address.

At time T2, if the read address pointer overtakes the write address pointer, the data read at that time is the data of the n-th frame. That is, the read data is initially n +
After reading the data of one frame, the data of the n-th frame is read after the read address pointer overtakes the write address pointer. Therefore, the read address pointer is not allowed to overtake the write address pointer. Since the read address pointer is faster than the write address pointer, it is not necessary to consider that the write address pointer overtakes the read address pointer. (A2) Calculation of Memory Capacity Here, the minimum necessary memory capacity of the frame memory is calculated based on the concept described in the preceding section.

First, the resolution of the input signal is set to H ₁ column × V
_One row, the resolution of the LCD panel is H ₂ columns × V ₂ rows.
However, it is assumed that H ₁ <H ₂ and V ₁ <V ₂ . At this time, the horizontal synchronization signal to be output is V ₂ / V of the input horizontal synchronization signal.
It becomes ₁ time frequency. Since the NON-EXPAND mode data of one line input is displayed on one line of the LCD panel, the data of V ₂ rows are read out in the time to write V ₁ line in the frame memory 1. Therefore, reading is started after writing data for X rows in the frame memory 1, and immediately after writing of H ₁ × V ₁ data is completed, H
_It is sufficient to finish reading ₁ × V ₁ data (FIG. 1B).

The value of X at this time is obtained. Light cycling
Since X lines of data have been written in₁−
X rows. This V₁-Same time as writing X rows
And V ₁Read a row. Time T for writing one line_wRead in
V is out_Two/ V₁Rows can be read. Therefore,
The time to read one row is T_w・ V₁/ V_TwoAnd V ₁
−X row write time ≦ V₁Is the row read time
(V₁−X) T_w≤V₁T_w× V₁/ V_Two Therefore, equation (1) holds.

(V ₁ −X) V ₂ / V ₁ ≦ V ₁ (1) By solving this, the equation (2) is obtained. X ≧ V ₁ (1−V ₁ / V ₂ ) (2) An address of H ₁ × a (a = 3 for color display, a = 1 for monochrome display) is required to write one row of data. Therefore, the total capacity N required for the memory is given by the following equation (3), where b is the number of data bits of each dot of R, G, and B.

N ≧ V ₁ (1−V ₁ / V ₂ ) H ₁ ab (3) Therefore, the minimum necessary memory amount is N = V ₁ (1−V ₁ / V ₂ ) H ₁ ab (4) ). If this N is calculated in the same manner as in the conventional example with a = 3 and b = 8, in the case of VGA: X = 480 × (1-480 / 768) = 180 N = XH ₁ ab = 180 × 640 × 8 × 3 = 2764800bit (=
337.5 kbyte) In case of SVGA: X = 600 × (1−600 / 768) = 131.25 N = XH ₁ ab = 131.25 × 800 × 8 × 3 = 2520000 bits
(= 307.6 kbyte), which is only required to be 1/4 of the memory conventionally required. (A3) Control Timing of Memory FIG. 1B shows the timing of controlling the memory 1 of FIG. 1A as discussed in the previous section. Since the total capacity of the memory is equal to the data amount of X rows, it is sufficient to return to the address 0 every X rows and repeat the writing operation.

The reading from the memory may be started after the writing of the data for X rows is completed, the address is returned to the 0 address for every X rows, and the reading operation may be repeated. However, the value of X described here is given by the equal sign of the equation (2). (B) When a single-port FIFO memory is used for the frame memory Until now, it has been considered that a dual-port FIFO memory that can simultaneously write and read the frame memory 1 is used. However, a single-port FIFO memory that cannot simultaneously write and read is used. It may be used. The memory capacity at this time is obtained below. At this time, since reading / writing cannot be performed at the same time, two FIFO memories are required as shown in FIG. 2, so the respective values of the two memories are calculated. (B1) Memory control timing As in (A2), the resolution of the input signal is H ₁ × V ₁ ,
Consider the memory control timing with the resolution of the LCD panel as H ₂ × V ₂ .

Since the memory is a single port, it can only write or read. Therefore, two memories are used so that one is written and the other is read. The two memories are memory 1-1, memory 1-2, and memory 1.
The number of lines that can be written to -1 is X, and the number of lines that can be written to the memory 1-2 is Y.

[0023] X rows write to (A ₁ cycle) memory 1-1, a memory 1-2 is not nothing. (A _2-cycle) After writing X rows in the memory 1-1,
The writing for the Y rows is started in the memory 1-2. Memory 1
At the same time as writing the data for the Y row to −2, reading the data for the X row from the memory 1-1 is completed.

[0024] (A ₃ cycles) memory 1-1 When you have finished reading the X rows, memory 1-1 to start writing. At the same time, reading of Y rows from the memory 1-2 is started. (A ₄ cycles) memory 1-2 starts to read simultaneously from the memory 1-1 After completing the reading of Y rows, the memory 1-2 to start writing. In this way, the cycle of switching read / write after one has finished reading is repeated. However, V ₁ because V ₁ / V ₂ times the time T _w required for the writing of the time is one row of data required to read at this time one line of data, the number of lines that can be written in either of the memory in each cycle / V ₂ times. (B2) Calculation of Memory Capacity The values of X and Y when the control as in (B1) is repeated are calculated. Since after the memory 1-2 has finished first write the number of rows that can be written for each read / write switches is being _doubled V ₁ / V, rows that can be written in the A _n-th cycle The number is Y (V ₁ /
A V ^{_{2) n-2}} line.

Therefore, the sum M of the number of rows written up to the end of the _An cycle is given by the following equation (4). ^{_{M = X + YΣ 0 n-}} 2 (V 1 / V 2) n-2 ... (4) since it is Kakikomere ₁ line V in total by repeating this cycle indefinitely, (4) is transformed into equation (5) it can.

V ₁ ≦ X + Y + Y (V ₁ / V ₂ ) + Y (V ₁ / V ₂ ) ² + Y (V ₁ / V ₂ ) ³ +... = X + YV ₂ / (V ₂ −V ₁ ) (5) The expression (5) is further modified into the expression (6). Y ≧ V ₁ (V ₂ −V ₁ ) / V ₂ − (V ₂ −V ₁ ) X / V ₂ (6) Further, A ₃ for reading out the data for the Y row first written in the memory 1-2. During the cycle, Y is stored in the memory 1-1.
Since (V ₁ / V ₂₎ must be written row of data, the total number of rows X memory 1-1 must be A ₃ line number Y (V ₁ / V ₂₎ is written in cycles or more. That is, X ≧ Y (V ₁ / V ₂ ). Therefore, equation (7) holds.

Y ≦ X (V ₂ / V ₁ ) (7) X and Y that simultaneously satisfy the equations (6) and (7) are shaded areas in FIG. Given the A ₂ cycle, the memory 1
X must be read in the memory 1-1 within the time for writing the data for the Y row into the memory 2. Therefore, if the time for writing the input signal for one row is T _w , then XT _w (V ₁ / V ₂ ) ≦ YT _w ＹY ≧ X (V ₁ / V ₂ ) (8) A region satisfying the equations (6), (7) and (8) at the same time is shown in FIG.
This is the area indicated by the dotted line.

X and Y are determined so that X + Y is minimized. When a straight line X + Y = K (constant) is drawn in FIG.
A straight line like a broken line is drawn. There are countless such straight lines depending on the value of K. Among them, the straight line with the minimum K is a straight line passing through the point A. Therefore, the values of X and Y to be obtained can be obtained by solving simultaneous equations using equations (6) and (7) as equations. Equations (6) and (7) are equivalent to equations (9) and (1).
0) is obtained.

Y = V ₁ (V ₂ −V ₁ ) / V ₂ − (V ₂ −V ₁ ) X / V ₂ (9) Y = X (V ₂ / V ₁ ) (10) Equations (11) and (12) are obtained. ^{_{X = V 1 2 (V 2}} -V 1) / (V 2 2 + V 1 V 2 -V 1 2) ... (11) Y = V 1 V 2 (V 2 -V 1) / (V 2 2 + V 1 ^{_{V 2 -V 1 2) ... (}} 12) Therefore capacity N ₁ necessary for memory 1-1, capacity N ₂ required memory 1-2, respectively (13), is given by equation (14).

[0030] ^{_{N 1 = V 1 2 (V}} 2 -V 1) H 1 ab / (V 2 2 + V 1 V 2 -V 1 2) ... (13) N 2 = V 1 V 2 (V 2 -V 1 _{) H 1 ab / (V 2} 2 + V 1 V 2 -V 1 2) ... (14) calculates the amount of memory as a = 3, b = 8.

In the case of a VGA: X = 480 ² × (768-480) / (768 ² + 768 × 480-480 ² ) = 91.1388 N ₁ = XH ₁ ab = 91.1388 × 640 × 3 × 8 = 1399893b
it (= 170.9kB) Y = 480 × 768 × (768-480) / (768 ² + 768 × 480-480 ² ) = 14
5.8 N ₂ = YH ₁ ab = 145.8 × 640 × 3 × 8 = 2239488 bits
(= 273.3kB) In case of SVGA: X = 600 ² × (768-600) / (768 ² + 768 × 600-600 ² ) = 87.5731 N ₁ = XH ₁ ab = 87.5731 × 800 × 3 × 8 = 1681404b
it (= 205.2kB) Y = 600 × 768 × (768-600) / (768 ² + 768 × 600-600 ² ) = 11
_{2.093 N 2 = YH 1 ab =} 112.093 × 800 × 3 × 8 = 2152197b
it (= 262.7kB).

From this result, in order to enable both VGA and SVGA, 205.2 is stored in the memory 1-1.
It seems that 273.3 KkB is required for kB and the memory 1-2, but actually, the memory 1-1 has 205.2 kB.
B, the memory 1-2 may be 262.7 kB. The reason is that the memory 1-1 has 205.2 kB, so the VGA 10
9.44 rows can be read and written, and the memory 1-2 has 26
Since it is 2.7 kB, 140.11 rows of VGA can be read and written. This value is X = 109.44, Y = 140.
11, when V ₁ = 480 and V ₂ = 768 (6),
This is because the expressions (7) and (8) are satisfied. (C) Others By performing control as we have thought so far, (A),
(B) Regardless of the memory used, the memory usage can be minimized. However, in reality, the memory capacity is 1 Mbit
Or 512 kbit, which is represented by ^2N .
At that time, a memory having a value larger than the value represented by the expression (4), (13), or (14) and having the closest value may be selected.
Also, for example, 256 kB is stored in the memory 1-1,
If 256 kB is also used for -2, the parameters of VGA and SVGA are substituted into the equations (6), (7) and (8), and this holds true. Only one-third the memory of the prior art is required.

The LCD has been described above as an example, but it goes without saying that the present invention is not limited to the LCD, and may be a dot matrix display such as a plasma display or an electroluminescence.

[0034]

According to the present invention, a dual-port FIFO memory or a single-port first and second FIFO memory is used as a frame memory, and their capacity can be suppressed to the minimum necessary. As a result, for example, about 〜 to １ ／ of the conventionally required memory capacity is sufficient,
Significant economy can be achieved.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an embodiment of claim 1, and FIG. 1B is a timing chart of input / output signals of A.

2A is a block diagram showing a third embodiment of the present invention, and FIG. 2B is a timing chart of A input / output signals.

FIG. 3 is a timing chart of write data and read data of a frame memory for explaining the concept of the invention of claim 1;

FIG. 4 is a graph showing the relationship between the numbers X and Y of rows of video signals written in the frame memories 1-1 and 1-2 in FIG. 2;

FIG. 5 shows an EXPAND mode and NON of the liquid crystal monitor device.
FIG. 9 is a diagram for explaining an EXPAND mode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/36 G09G 3/36

Claims (4)

[Claims] 1. An input video signal having a resolution of H ₁ × V ₁ (H ₁ is the number of columns of one screen and V ₁ is the number of rows) is converted to a resolution of H ₂ × V 1.
₂ (However, it is assumed that H ₂ ≧ H ₁ , V ₂ ≧ V ₁ ) A multi-sync of a monitor device that converts signals near the center of the screen of the dot matrix display so that the signals are displayed at the resolution of the input video signal In the circuit, a dual-port FIFO (First In First) is used as a frame memory for temporarily storing an input video signal, reading out the stored signal, and sending the signal to the display.
Out) memory, and the capacity N of the FIFO memory is set as N ≧ V ₁ (1−V ₁ / V
₂ ) A multi-sync of a monitor device characterized by selecting H ₁ ab (however, a = 3 for color display, a = 1 for monochrome display, and b is the number of bits of data of one pixel). circuit. 2. The apparatus according to claim 1, wherein X = V ₁ (1−V ₁ / V ₂ ) of the input video signal to be written into the frame memory.
The write address pointer is reset to a zero address for each row, a read cycle is started when the X rows of data are written to the frame memory, and a read is performed every time the X rows of data are read from the frame memory. A multi-sync circuit for a monitor device, comprising a control circuit for resetting an address pointer to a zero address. 3. The resolution is H₁× V₁Input video signal
Resolution is H_Two× V_Two(But H_Two≧ H₁, V_Two≧ V₁
Near the center of the screen of the dot matrix display
Signal so that it is displayed at the resolution of the input video signal.
The input video signal is temporarily stored in the multi-sync circuit of the monitor device to be converted, and the stored signal is read out.
As a frame memory to be sent to the display
Using the first and second FIFO memories of a single port, the capacity N of the first FIFO memory₁To N₁≧ V₁ ^Two(V_Two−
V₁) H₁ab / (V _Two ^Two+ V₁V_Two-V₁ ^Two), The second floor
IFO memory capacity N_TwoTo N_Two≧ V₁V_Two(V_Two-V
₁) H₁ab / (V_Two ^Two+ V₁V_Two-V₁ ^Two)
Multi-sync operation of a monitor device characterized by
Road. 4. The method according to claim 3, wherein in the first cycle, X = X of the video signal is stored in the first FIFO memory.
^{_{V 1 2 (V 2 -V 1}} ) / (V 2 2 + V 1 V 2 -V 1 2) write a line of data, in the second cycle, the video signal to the 2FIFO memory Y =
_{V 1 V 2 (V 2 -V} 1) / (V 2 2 + V 1 V 2 -V 1 2) writes the rows of data, reading out the X rows of data of the 1FIFO memory, in the third cycle , The data of Y rows in the second FIFO memory are read, and Y (V ₁ / V
₂ ) Write data for a row, and in the fourth cycle, write Y (V ₁ / V
₂ ) A control circuit for reading out the data for the row and writing the data for ^two rows of Y (V ₁ / V ₂ ) to the ^second FIFO memory, and similarly writing / reading the first and second FIFO memories is provided. A multi-sync circuit for a monitor device.