JPH1187545A - Semiconductor non-volatile memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor non-volatile memory device to be lessened in operating voltage such as an erase voltage by a method wherein a field effect memory transistor possessed of a charge storage layer is provided between a control gate and a channel forming region in a semiconductor layer. SOLUTION: A floating gate 32a has a function to retain electrical charge in a film, and a tunnel insulating film 22a and an intermediate insulating film 23a serve to confine electrical charge in the floating gate 32a. A proper potential is applied to a control gate 32a and a source drain diffusion layer inside a semiconductor layer 31b, whereby a Fowler Nordheim tunnel current is generated, and electrons are injected from the semiconductor layer 31b into the floating gate 32a through the tunnel insulating film 22a or electrons are discharged from the floating gate 32a into the semiconductor layer 31b. When charge is accumulated in the floating gate 32a, an electrical field is generated by the accumulated charge, so that a transistor is changed in threshold voltage to store data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device and a method of manufacturing the same, and more particularly, to a semiconductor nonvolatile memory device having a charge storage layer for storing charges between a gate electrode of a transistor and a channel forming region, and a method of manufacturing the same. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Currently, semiconductor non-volatile memory devices are being actively developed, and various structures and configurations are being researched and developed, mainly of flash memories having a floating gate structure. This flash memory is roughly classified into a NAND type and a NOR type from the viewpoint of the cell configuration.

[0003] Among the above, the NAND type has a plurality of memory cells connected in series and has a common selection transistor and a bit line. For example, when eight memory cells are connected, 1/2 of the data input / output contacts are shared by the 8-bit memory cells, and each bit has 1/16 contacts. Similarly, the select gate and the source line are all shared by 8 bits. Therefore, as described above, the area per bit is close to the area occupied by the memory transistor, and the memory cell area is very small. Although random access is not possible due to its structure, it is advantageous in terms of high integration, large capacity and low cost. AV
For applications such as (audio, video) or data storage, a low-cost, large-capacity flash memory is required, which is suitable for replacing magnetic recording means such as an HDD (hard disk drive).

On the other hand, the NOR type has a structure in which the number of contacts per bit is １ ／, which is disadvantageous in terms of the degree of integration as compared with the NAND type, but has an advantage that high-speed random access reading is possible. There is. For high-speed read applications, it is expected that it will be part of the main memory in the future. The NAND-type or NOR-type memory transistor may be a floating gate type or a SIOS (or MONOS) type.

A table comparing the performances of the above NAND type and NOR type is shown below.

[0006]

[Table 1]

Here, a circuit diagram of a NOR type memory cell is shown in FIG. In erasing data, a low voltage Vcg is applied to the control gate CG, and a high voltage Vs is applied to the source S.
And the bit line B and the substrate Sub are opened.
As a result, electrons in the floating gate are extracted by the Fowler-Nordheim tunnel phenomenon, and data is erased. This erasing can be performed collectively for each erase sector.

On the other hand, in a NAND type memory cell, for example, 8-bit memory transistors are connected in series to form a NAND string as shown in FIG.
A selection transistor for selecting a column is formed. As a method of erasing data in the NAND type memory cell, 0V is applied to all the control gates CG of the NAND string.
And the selection gate SG of the two selection transistors
1, SG2 and the substrate Sub at a high voltage (for example, 20
V). The source S and the bit line B are open. As a result, as in the case of the NOR type,
Electrons in the floating gate are extracted by the Nordheim tunnel phenomenon, and data in the entire NAND string is erased at a time.

[0009]

However, in the above-mentioned conventional semiconductor non-volatile memory device, it is necessary to apply a high voltage as an operating voltage in the above-described data erasing operation and the like.

[0010] In addition, with the high integration and large capacity of the device,
Cost reduction was required. In particular, cost reduction is an essential condition in order to realize replacement of the magnetic recording means.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention can reduce the operating voltage such as the erase voltage and can reduce the cost of the semiconductor nonvolatile memory. It is an object to provide a storage device and a method for manufacturing the storage device.

[0012]

In order to achieve the above object, a semiconductor non-volatile memory device according to the present invention is a semiconductor non-volatile memory device to which a memory transistor having a charge storage layer is connected. A semiconductor layer having a channel formation region formed on an insulating substrate made of: a charge storage layer formed on the semiconductor layer; a control gate formed above the charge storage layer; and a channel formation region. And a source / drain region formed so as to be connected to the thin film transistor, and a thin film transistor serving as the memory transistor is formed.

The above-described nonvolatile semiconductor memory device of the present invention has a field effect type memory transistor having a charge storage layer between a control gate and a channel formation region in a semiconductor layer. The charge storage layer has a function of retaining charges therein, and by applying an appropriate voltage to the control gate and the semiconductor layer, a Fowler-Nordheim tunnel current is generated, electrons are injected from the semiconductor layer into the charge storage layer, Alternatively, electrons are emitted from the charge storage layer to the semiconductor layer. When electric charges are accumulated in the electric charge accumulation layer, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the memory transistor changes. This change allows data to be stored. For example, data can be erased by storing charges in the charge storage layer, and data can be written by discharging charges stored in the charge storage layer.

In the above-described semiconductor nonvolatile memory device of the present invention, the control gate and the channel formation region in the semiconductor layer are formed on a low-cost substrate such as a glass substrate or a plastic substrate as a low-cost and high-precision transistor. Thin film transistor (Th
in Film Transistor (hereinafter referred to as TFT). As a substrate for forming the TFT, a glass substrate is about 1/15 less than a normal silicon wafer when compared with a size of, for example, 8 inches φ (150 × 150 mm ² ). Also used for liquid crystal display applications
A square glass substrate of 300 × 400 mm ² has an area about 5 times that of an 8-inch φ silicon wafer, while its price is about 1/8. Has become. The price of plastic substrates is also expected to fall in the future. Therefore, a semiconductor non-volatile memory device using a TFT as a memory transistor can employ the above-mentioned inexpensive substrate, and can realize a significant cost reduction.

Further, the TFT formed on an insulating substrate such as a glass substrate can make the junction capacitance of the transistor almost zero, and since it is a fully depleted type, the depletion layer capacitance is so small that it can be ignored. This is advantageous in terms of read speed (ON bit sensing). Further, the gate swing value is determined only by the trap density in the semiconductor layer, a sharp inversion characteristic is obtained, a voltage such as an erase voltage can be reduced, and a memory transistor which can operate at high speed can be obtained.

In the above-described semiconductor nonvolatile memory device of the present invention, preferably, the semiconductor layer is formed of polysilicon or quasi-single-crystal silicon. Here, the quasi-single-crystal silicon includes, for example, a group of substantially rectangular silicon single-crystal particles arranged in a grid pattern on a substrate, and the selected orientation of each silicon single-crystal particle with respect to the substrate surface is approximately (100).
Surface, and the interface between the silicon single crystal particles is a silicon crystallized film in a state close to lattice matching, and is electrically uniform and has excellent characteristics as compared with polysilicon. As the production method, the methods described in Japanese Patent Application Nos. 9-064036 and 9-087728 can be used. Polysilicon or quasi-single-crystal silicon as a layer to be a channel forming region of a TFT is formed at a low temperature suitable for forming on a glass substrate or a plastic substrate such as an excimer laser annealing (ELA) method. By the above process, it is possible to provide a high-performance semiconductor layer capable of reducing the trap density in the film and reducing the gate swing value.

Further, in order to achieve the above object, a semiconductor nonvolatile memory device according to the present invention is a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, the surface of which is covered with a silicon oxide film. A semiconductor layer formed of quasi-single-crystal silicon having a channel formation region formed on an insulating substrate that is a silicon substrate, a charge storage layer formed on the semiconductor layer, and a charge storage layer formed on the semiconductor layer. A control gate formed above,
A thin film transistor which has a source / drain region formed to be connected to the channel forming region and serves as the memory transistor;

The semiconductor nonvolatile memory device of the present invention has a field effect type memory transistor having a charge storage layer between a control gate and a channel formation region in a semiconductor layer. The charge storage layer has a function of holding charges therein, and when charges are stored in the charge storage layer, an electric field is generated by the stored charges, so that the threshold voltage of the memory transistor changes. This change allows data to be stored.

In the semiconductor nonvolatile memory device of the present invention, as a low-cost and high-precision transistor, a control gate and a channel formation region in the semiconductor layer are formed on a silicon substrate whose surface is covered with a silicon oxide film. A TFT having a charge storage layer between them is formed. As the silicon substrate whose surface is covered with a silicon oxide film, since a channel formation region is not formed in the silicon substrate, the silicon substrate is of a low quality and is 1/2 to 1/1 / that of a normal MOS LSI silicon substrate. A silicon substrate at a price of 3 can be used. Therefore, a semiconductor non-volatile memory device using a TFT as a memory transistor can employ the above-mentioned inexpensive substrate, and can realize a significant cost reduction.

A TFT formed on an insulating substrate, which is a silicon substrate whose surface is covered with a silicon oxide film,
The junction capacitance of the transistor can be reduced to almost zero,
In addition, since it is a fully depleted type, the capacitance of the depletion layer is so small as to be negligible, and is advantageous in terms of read speed (ON bit
g). Further, the gate swing value is determined only by the trap density in the semiconductor layer, and a sharp inversion characteristic is obtained.
A memory transistor which can operate at high speed with a low voltage such as an erase voltage can be obtained.

The semiconductor nonvolatile memory device of the present invention preferably has a transistor for a peripheral circuit on the substrate, and more preferably, the gate width of the gate of the transistor for the peripheral circuit is It is larger than the gate length of the gate and the average grain size of the polysilicon forming the gate. Peripheral circuit transistors can also be formed over the same substrate and have a TFT structure. This makes it possible to integrate fine circuits on the substrate at low cost. For example, by forming a logic gate such as a CMOS including a TFT on the same substrate, a versatile and multifunctional micro system-on-chip can be realized. in this case,
By making the gate width of the peripheral circuit transistor larger than the gate length and the average grain size of the polysilicon forming the gate, the characteristics of the peripheral circuit transistor can be improved and the uniformity of the characteristics can be improved. When the peripheral circuit transistor is formed by CMOS, it can be easily formed according to a fine rule.

Further, in order to achieve the above object, a semiconductor nonvolatile memory device according to the present invention is a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, the surface of which is covered with a silicon oxide film. A semiconductor layer formed of polysilicon having a channel formation region formed on an insulating substrate that is a silicon substrate, a charge storage layer formed on the semiconductor layer, and a charge storage layer formed on the semiconductor layer. A thin film transistor serving as the memory transistor is formed having a control gate formed and a source / drain region formed in connection with the channel formation region, and a transistor for a peripheral circuit is provided on the substrate. The gate width of the gate of the transistor for the peripheral circuit forms the gate length of the gate and the gate. Greater than the average particle diameter of Rishirikon.

In the above-mentioned semiconductor nonvolatile memory device of the present invention, since the channel formation region is not formed in the silicon substrate whose surface is covered with the silicon oxide film, it is low in quality and inexpensive. Substrate can be adopted, and significant cost reduction can be realized. In addition, the junction capacitance of the transistor can be reduced to almost zero, and since it is a fully depleted type, the capacitance of the depletion layer is so small that it can be ignored. The gate swing value is determined only by the trap density in the semiconductor layer, and a sharp inversion characteristic is obtained. In addition, a memory transistor that can operate at high speed can be operated at a low voltage such as an erase voltage. Further, the semiconductor non-volatile memory device of the present invention has a transistor for a peripheral circuit on a substrate, and the gate width of the gate of the transistor for the peripheral circuit is equal to the gate length of the gate and the average of the polysilicon forming the gate. Since the size is larger than the particle size, a peripheral circuit transistor having high characteristics and uniform characteristics on the substrate has a fine circuit, for example, a CMOS composed of TFTs.
Logic gates and the like can be integrated at low cost, and a versatile and multifunctional micro system-on-chip can be realized.

In the semiconductor nonvolatile memory device according to the present invention, preferably, the charge storage layer is a floating gate made of a conductor insulated by an insulating film. Electric charges can be confined in the conductor which is insulated by the insulating film, so that a floating gate can be obtained. Thus, a floating gate type semiconductor nonvolatile memory device can be obtained.

In the above-described semiconductor nonvolatile memory device of the present invention, preferably, the charge storage layer is an insulator having a charge trap, and more preferably, the insulator having the charge trap is an oxide film. The insulator having a nitride film-oxide film or the nitride film-oxide film, or the insulator having the charge trap has an average particle diameter of 2 to 5 n.
This is an insulator that holds inside a nanocrystal made of a conductor of m. An insulator having a charge trap can hold a charge in the film, and for example, a MONOS structure having an ONO film (laminated insulating film of an oxide film-nitride film-oxide film) or an NO film (nitride film-oxide MNOS structure having a laminated insulating film of the film, or a nanodot memory capable of holding electric charge in nanocrystals in the insulating film.

In the above-described semiconductor nonvolatile memory device of the present invention, preferably, the memory transistor is connected in a NOR type. Accordingly, high-speed random access reading is possible, and NO for which batch erasing for each erase sector is possible.
An R-type semiconductor nonvolatile memory device can be obtained.

In the semiconductor nonvolatile memory device according to the present invention, preferably, the memory transistor is connected in a NAND type, and more preferably, a lower gate insulating film formed below the semiconductor layer. And an erase gate formed below the lower gate insulating film. More preferably, the erase gate is connected to at least an erase gate of an adjacent memory transistor. Accordingly, a NAND-type semiconductor nonvolatile memory device which is advantageous in terms of high integration, large capacity, and low cost can be provided. An erase gate is provided below the semiconductor layer with a lower gate insulating film interposed therebetween, and an erase voltage (for example, a positive voltage) is applied to the erase gate, so that data can be erased. By connecting to the erase gate of the transistor and sharing the entire memory array or block unit,
Batch erasing can be performed for the entire memory array or for each erase sector in block units.

Further, in order to achieve the above-mentioned object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention is a method for manufacturing a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected. Alternatively, a step of forming a semiconductor layer having a channel formation region on an insulating substrate made of plastic, a step of forming a charge storage layer above the semiconductor layer, and a step of forming a control gate above the charge storage layer And forming a source / drain region connected to the channel formation region to form a thin film transistor serving as the memory transistor.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, a semiconductor layer having a channel formation region is formed on an insulating substrate made of glass or plastic, and a charge storage layer is formed on the semiconductor layer. Then, a control gate is formed above the charge storage layer, and source / drain regions connected to the channel formation region are formed. Thus, a thin film transistor (TFT) serving as a memory transistor having a charge storage layer can be formed on a low-cost insulating substrate made of glass or plastic between the control gate and the channel formation region in the semiconductor layer.

According to the method of manufacturing a semiconductor non-volatile memory device of the present invention, a TFT as a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass is used.
Since the semiconductor nonvolatile memory device is formed, a voltage such as an erase voltage can be reduced, and a semiconductor nonvolatile memory device including a memory transistor which can operate at high speed can be manufactured at a significantly reduced cost.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the steps after the step of forming the semiconductor layer are performed at 600 ° C. or lower. This makes it possible to use an insulating substrate made of glass or plastic, which is low in cost but has a low melting point, so that cost reduction can be realized.

Preferably, in the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, the step of forming the semiconductor layer includes a step of forming a silicon layer, an excimer laser annealing method or a low-temperature solid-state crystallization method. And crystallizing the silicon layer. Thus, the trap density in the film can be reduced and the gate swing value can be reduced by a low-temperature process suitable for forming a TFT serving as a channel formation region on a glass substrate or a plastic substrate. A polysilicon layer or a quasi-single-crystal silicon layer which is a high-performance semiconductor layer can be formed.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, the step of forming the silicon layer is more preferably performed by CVD using Si ₂ H ₆ or SiH ₄ as a raw material.
This is a step of forming by a (chemical vapor deposition) method. CV
As the D method, a low pressure CVD method or a plasma CVD method
The method can be preferably used. Si ₂ H ₆ , or
According to a CVD method such as a low pressure CVD method or a plasma CVD method using SiH ₄ as a raw material, when a laser beam is irradiated in a later ELA step or the like, the insulating film is scattered in a low-temperature process of 500 ° C. or less and holes are opened. The silicon layer can be formed under the condition that the incorporation of hydrogen into the film that causes the silicon layer is small.

In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, the step of forming the silicon layer is more preferably a step of forming by a sputtering method. According to the sputtering method, a silicon layer can be formed by a low-temperature process of 500 ° C. or lower.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, the step of forming the charge storage layer may further comprise the steps of: forming a gate insulating film on the semiconductor layer; Forming a floating gate made of a conductor on the insulating film; and forming an intermediate insulating film on the floating gate. Thus, a floating gate type semiconductor nonvolatile memory device in which charges are confined and held in the conductive floating gate by the gate insulating film and the intermediate insulating film can be obtained.

In the method of manufacturing a semiconductor non-volatile memory device according to the present invention, the step of forming the charge storage layer is preferably a step of forming an insulator having a charge trap on the semiconductor layer. is there. Accordingly, an MO having an ONO film (a stacked insulating film of an oxide film, a nitride film, and an oxide film) that accumulates charges in an insulator having a charge trap is formed.
A semiconductor nonvolatile memory device having an NOS structure or an MNOS structure having an NO film (laminated insulating film of a nitride film and an oxide film) can be manufactured.

In the above-described method of manufacturing a semiconductor nonvolatile memory device according to the present invention, more preferably, the memory transistor is formed by connecting to a NOR type. As a result, it is possible to manufacture a NOR type semiconductor nonvolatile memory device capable of high-speed random access reading and capable of collectively erasing each erase sector.

In the above-described method for manufacturing a semiconductor nonvolatile memory device according to the present invention, more preferably, the memory transistor is formed by connecting the memory transistors in a NAND type. A NAND-type semiconductor nonvolatile memory device which is advantageous in terms of high integration, large capacity, and low cost can be manufactured.

Preferably, in the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, before the step of forming the semiconductor layer, a step of forming an erase gate on the insulating substrate; Forming a lower gate insulating film on the gate. This makes it possible to erase data by applying an erasing voltage (for example, a positive voltage) to the erasing gate, and by sharing this erasing gate in the entire memory array or in block units, the entire memory array or block unit can be erased. It is possible to manufacture a semiconductor non-volatile memory device that enables batch erasure for each erase sector.

Further, in order to achieve the above object, a method of manufacturing a semiconductor nonvolatile memory device according to the present invention is directed to a semiconductor memory having a first transistor which is a memory transistor having a charge storage layer and a second transistor for a peripheral circuit. A method for manufacturing a nonvolatile memory device, comprising: an insulating substrate that is a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic;
Forming a first semiconductor layer having a first channel forming region for the first transistor in a first transistor forming region, and forming a second semiconductor layer having a second channel forming region for the second transistor in a second transistor forming region; Forming a charge storage layer on the first semiconductor layer and forming a gate insulating film on the second semiconductor layer; and forming a control gate above the charge storage layer. Forming a gate electrode above the gate insulating film; and forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region. And a process.

According to the method of manufacturing a semiconductor non-volatile memory device of the present invention, a memory transistor having a TFT structure and a transistor for a peripheral circuit can be simultaneously formed on the same substrate, and a CMOS composed of TFTs can be formed. By forming such logic gates and the like on the same substrate, a versatile and multifunctional micro system-on-chip can be manufactured. Since a TFT is formed as a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor that can operate at high speed can be operated at a low voltage such as an erase voltage. The device can be manufactured at significantly lower cost. When a silicon substrate whose surface is covered with a silicon oxide film is used as a substrate, a high-temperature process such as a thermal oxidation method can be used in a step of forming a gate insulating film or a tunnel insulating film, and a high-quality gate insulating film can be obtained. It is possible to form a film or a tunnel insulating film.

Further, in order to achieve the above object, a method of manufacturing a semiconductor nonvolatile memory device according to the present invention is directed to a semiconductor nonvolatile memory device having a first transistor having a charge storage layer and a second transistor for a peripheral circuit. Forming an erase gate on a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic in a first transistor formation region; Forming a lower gate insulating film; forming a first semiconductor layer having a first channel forming region for the first transistor on an upper layer of the lower gate insulating film; Forming a second semiconductor layer having a second channel formation region for the second transistor in the first semiconductor device; Forming a charge storage layer above the second semiconductor layer and forming a gate insulating film above the second semiconductor layer; forming a control gate above the charge storage layer; and forming a gate electrode above the gate insulating film. Forming and forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, a memory transistor having a TFT structure and a transistor for a peripheral circuit can be simultaneously formed on the same substrate, and an erase gate is used as a memory transistor. Can be formed. Accordingly, a semiconductor nonvolatile memory device having a structure that is shared by the entire memory array or block unit, which is difficult with a NAND type TFT memory transistor, and capable of collectively erasing each erase sector in the entire memory array or block unit Can be manufactured. Since a TFT is formed as a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor that can operate at high speed can be operated at a low voltage such as an erase voltage. The device can be manufactured at significantly lower cost. When a silicon substrate whose surface is covered with a silicon oxide film is used as a substrate, a high-temperature process such as a thermal oxidation method can be used in a step of forming a gate insulating film or a tunnel insulating film, and a high-quality gate insulating film can be obtained. It is possible to form a film or a tunnel insulating film.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor nonvolatile memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. A memory transistor is formed in a region on the left side of the drawing. For example, a glass substrate such as non-alkali glass or an insulating substrate 10 made of a plastic substrate
A base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed in the upper layer, and a semiconductor layer 31b made of, for example, polysilicon and having a channel formation region is formed in the upper layer.

A thin tunnel insulating film 22a made of, for example, silicon oxide is formed on the semiconductor layer 31b. A floating gate 32a made of, for example, polysilicon is formed on the tunnel insulating film 22a. An intermediate insulating film 23a made of a film (a stacked body of an oxide film-nitride film-oxide film) or a silicon oxide film is formed, and a control gate 33a made of, for example, polysilicon is formed thereover. In the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. Thus, a field effect transistor having a TFT structure having the floating gate 32a insulated by the insulating film between the control gate 33a and the channel formation region in the semiconductor layer 31b is obtained.

In the field effect transistor having the above-mentioned structure, the floating gate 32a has a function of retaining charges in the film, and the tunnel insulating film 22a and the intermediate insulating film 23a
Has a role of confining charges in the floating gate 32a. Control gate 33a and semiconductor layer 3
By applying an appropriate voltage to a source / drain diffusion layer (not shown) in 1b, a Fowler-Nordheim type tunnel current is generated, and electrons are injected from the semiconductor layer 31b to the floating gate 32a through the tunnel insulating film 22a, or Electrons are emitted from the gate 32a to the semiconductor layer 31b. When electric charges are accumulated in the floating gate 32a, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes and the memory transistor becomes capable of storing data. For example, data can be erased by accumulating charges in the floating gate 32a, and data can be written by discharging charges accumulated in the floating gate 32a.

On the other hand, a peripheral circuit transistor is formed in a region on the right side in the drawing. A base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an upper layer of the substrate 10 on which the memory transistor is formed.
A semiconductor layer 31b having a channel formation region is formed. On the semiconductor layer 31b, a thin gate insulating film 25a made of, for example, a silicon oxide film and an ONO film or a thin film made of a silicon oxide film is formed, and a gate electrode 33a 'made of, for example, polysilicon is formed thereon.
Are formed. In the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. Thereby, a field effect transistor having a TFT structure is obtained.

The above-mentioned semiconductor nonvolatile memory device can realize a significant cost reduction by using a low-cost substrate such as a glass substrate. In addition, a TFT formed on an insulating substrate such as a glass substrate can make the junction capacitance of the transistor almost zero, and since it is a fully depleted type, the capacitance of the depletion layer is so small that it can be ignored. Is determined only by the trap density in the semiconductor layer, sharp inversion characteristics can be obtained, a voltage such as an erase voltage can be reduced, and a memory transistor which can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. .

Further, the above-mentioned semiconductor nonvolatile memory device comprises:
Peripheral circuit transistors are also formed on the same substrate,
Fine circuits can be integrated on a substrate at low cost. By forming a logic gate such as a CMOS constituted by a TFT on the same substrate, a versatile and multifunctional micro system-on-chip can be realized.

When the gate electrode of the peripheral circuit transistor is formed of polysilicon, as shown in FIG. 2A, the gate width W is set to the gate length L and the average grain size L of the polysilicon forming the gate. 'Is formed larger. Thereby, the characteristics of the peripheral circuit transistor can be improved, and the uniformity of the characteristics can be improved. When the peripheral circuit transistor is formed by CMOS, it can be easily formed according to a fine rule. FIG. 2B shows a case where the gate width W is smaller than that of FIG. 2A and is substantially equal to the gate length L and the average grain size L ′ of the polysilicon forming the gate. And its uniformity is not good.

FIG. 3A is an equivalent circuit diagram of a semiconductor nonvolatile memory device in which memory transistors having the structure shown in FIG. 1 are connected in a NOR type. Two control gates of the memory transistors MT ₁ and MT ₂ are connected to the n-th word line W _n, a source open to a ground (G-O)
Or a source potential is applied. The drain is the n-th bit line B _n and the (n + 1) -th bit line B
_{n + 1} . Another two memory transistors MT ₃ and MT ₄ is also in the same manner as described above the word lines are connected to the bit line.

[0053] As data erasing method in the above NOR type semiconductor nonvolatile memory device, as shown in FIG. 3 (b), a low voltage Vcg is applied to the control gate CG, a high voltage V _s to a source S And the bit line B is open. In this manner, data can be erased by the source erase operation of extracting electrons in the floating gate by the Fowler-Nordheim tunnel phenomenon, and since it is of the NOR type, the entire memory array can be erased collectively or in each erase sector. Can be.

Next, a method of manufacturing the semiconductor nonvolatile memory device according to the above-described embodiment will be described. First, FIG.
As shown in (a), an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate.
Use In the subsequent steps, when a low melting point substrate such as the above glass substrate is used, the process temperature is set at 60 ° C.
For example, in the formation of an insulating film, a sputtering method or a chemical vapor deposition (Chemical vapor deposition) method is used.
ical Vapor Deposition (hereinafter referred to as CVD) method. For example, silicon oxide or silicon nitride is formed on the insulating substrate 10 by plasma enhanced CVD or sputtering, for example, 200 nm in the case of silicon nitride, and 40 nm in the case of silicon oxide.
The base insulating film 20 is formed by depositing with a thickness of 0 nm.

Next, as shown in FIG. 4B, a sputtering method or a CV
The semiconductor layer 31 is formed by depositing amorphous silicon to a thickness of 40 nm by the D method or the like. In particular, according to a sputtering method or a low-pressure CVD method, when a laser beam is irradiated in a later ELA step or the like, the incorporation of hydrogen into the film which causes scattering of an insulating film and opening of holes is reduced. preferable. Further, according to the low pressure CVD method using SiH ₄ or Si ₂ H ₆ as a raw material, a silicon layer can be formed by a low temperature process of 500 ° C. or less.

Next, as shown in FIG.
The amorphous silicon semiconductor layer 31 is crystallized by the LA process to form a polysilicon semiconductor layer 31a. EL
Various beam shot methods are conceivable as the A process. However, in a top gate TFT, the flatness, smoothness, and uniformity of the silicon film are regarded as important, and a single shot or a multi-shot for each chip is preferable. In addition, by heating the substrate, crystallinity can be improved and crystallization can be performed. For example, a step-and-repeat ELA process is performed at 400 ° C. with 300 mJ / cm ² energy and 5 shots and a uniform 2 × 2 cm ² excimer laser beam. This crystallization is performed by a low-temperature solid-phase crystallization method (SP
C) or ELA processing after SPC processing.

Next, as shown in FIG. 5D, the resist film is patterned and the semiconductor layer 31a is patterned by photolithography to form a semiconductor layer 31b in which elements are isolated in an island shape. Because of the TFT structure, element isolation can be easily performed as compared with an element isolation method such as a LOCOS method usually used in a conventional semiconductor device formed on a silicon wafer.

Next, as shown in FIG. 5E, a tunnel insulating film 22 is formed by depositing silicon oxide to a thickness of about 9 nm by, for example, a plasma CVD method. A particularly high-quality film is required as the tunnel insulating film 22, and in order to form it by a low-temperature process, an ECR (Electron Cyclotron) is required.
(Resonance) type plasma CVD.

Next, as shown in FIG. 5F, a polysilicon containing conductive impurities is deposited on the upper layer of the tunnel insulating film 22 by, for example, a CVD method to form a floating gate layer 32. Alternatively, conductive impurities may be ion-implanted after depositing polysilicon.

Next, as shown in FIG. 6 (g), a resist film R1 for protecting the memory transistor formation region is formed by patterning by a photolithography process, and RIE is performed.
(Reactive ion etching) or the like is applied to remove the floating gate layer 32 deposited in the peripheral circuit transistor formation region.

Next, as shown in FIG. 6 (h), after removing the resist film R1, for example, a floating gate layer 32 is coated and the entire surface is subjected to, for example, an ONO film (oxide film-nitride film-oxide film) by a CVD method. A stacked insulating film of a film) or a silicon oxide film is deposited to form an intermediate insulating film 23.
At this time, in the peripheral circuit transistor formation region, the tunnel insulating film 22 and the intermediate insulating film 23 are laminated to form the gate insulating film 25 of the peripheral circuit transistor.

Next, as shown in FIG. 6I, polysilicon is deposited on the intermediate insulating film 23 by, for example, a CVD method to form a control gate layer 33.

Next, as shown in FIG. 7J, a resist film R2 having a pattern of a control gate of the memory transistor and a gate electrode of the peripheral circuit transistor is formed.
Is patterned by a photolithography process.

Next, as shown in FIG. 7K, etching such as RIE is performed using the resist film R2 as a mask.
In the memory transistor formation region, the control gate 33a, the intermediate insulating film 23a, the floating gate 32a, and the tunnel insulating film 22a are patterned and formed in a self-aligned manner. At the same time, in the peripheral circuit transistor formation region, the gate electrode 33a 'and the gate insulating film 25a are patterned and formed in a self-aligned manner.

Next, after removing the resist film R2, using the control gate 33a and the gate electrode 33a 'as a mask, for example, P is applied to the source / drain diffusion layer formation region at a dose of, for example, 2 × 10 ¹⁵ ions / cm ² . Ion implantation,
A source / drain diffusion layer (not shown) is formed.
Annealing is performed by an LA method or an RTA (Rapid Thermal Annealing) method using, for example, a line scan under a condition in which the glass is not melted to activate impurity ions in the source / drain diffusion layers. Thus, the device shown in FIG. 1 can be formed. In the subsequent steps, an interlayer insulating film is formed by covering the control gate, contacts and the like are opened, and upper layer wirings such as bit lines are formed, whereby a desired semiconductor nonvolatile memory device can be obtained.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present embodiment, the T as a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass is used.
Since the FT is formed, a voltage such as an erase voltage can be reduced, and a semiconductor nonvolatile memory device having a memory transistor which can operate at high speed can be manufactured at a significantly reduced cost. Since the peripheral circuit transistors are simultaneously formed on the same substrate, the C
Logic gates such as MOS can be formed on the same substrate,
A variety of multifunctional micro system-on-chips can be manufactured.

In the present embodiment, a silicon substrate whose surface is covered with a silicon oxide film can be used as the substrate. In this case, since the channel formation region is not formed in the silicon substrate, the quality is low and is 1/2 to 1 times smaller than that of a normal MOS LSI silicon substrate.
Since a silicon substrate with a price of ３ can be used, a significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and a tunnel insulating film can be formed.

Second Embodiment FIG. 8 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. For example, a base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an upper layer of an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate. A semiconductor layer 31b made of crystalline silicon and having a channel formation region is formed.
A thin tunnel insulating film (bottom insulating film) 22a made of, for example, silicon oxide is formed on the semiconductor layer 31b, and a charge trapping insulating film 24a made of, for example, silicon nitride is formed on the tunnel insulating film 24a. As the upper layer, a top insulating film 23a made of, for example, silicon oxide is formed. From the bottom insulating film 22a, the charge trapping insulating film 24a, and the top insulating film 23a, a laminated insulating film having a charge trap level in the film and having a charge storage ability is formed. On top of the top insulating film 23a,
Control gate 33a made of, for example, polysilicon
Are formed. In the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. Thereby, between the control gate 33a and the channel formation region in the semiconductor layer 31b,
MONOS, which is a field-effect transistor having a laminated insulating film having a charge storage ability, wherein the charge storage layer is an ONO film
It becomes a memory transistor having a structure.

In the field effect transistor having the above structure, the bottom insulating film 22a, the charge trapping insulating film 24
a and the laminated insulating film composed of the top insulating film 23a
It has the function of retaining charges in the film. By applying an appropriate voltage to the control gate 33a and a source / drain diffusion layer (not shown) in the semiconductor layer 31b, a Fowler-Nordheim tunnel current is generated, and the charge injected from the semiconductor layer 31b through the bottom insulating film 22a is reduced. Charges are trapped in charge trap levels in the charge trap insulating film 24a or charge trap levels at the interface between the charge trap insulating film 24a and the top insulating film 23a, or charges are released from these trap levels through the bottom insulating film 22a. Is done. When electric charge is accumulated in the stacked insulating film, an electric field is generated by the accumulated electric charge, so that the threshold voltage of the transistor changes and the memory transistor can store data. For example, data can be erased by accumulating charges in the stacked insulating film, and data can be written by discharging charges accumulated in the stacked insulating film.

As in the first embodiment, the use of a low-cost substrate such as a glass substrate can significantly reduce the cost of the semiconductor nonvolatile memory device described above, and the voltage such as the erase voltage can be reduced. A memory transistor which can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. .

In the semiconductor nonvolatile memory device of the present embodiment, in the manufacturing method of the first embodiment, the charge trapping insulating film 24 is formed by depositing silicon nitride by, for example, a CVD method instead of the polysilicon floating gate layer.
Except for forming a, it can be formed in the same manner as the manufacturing method of the first embodiment. Instead of the intermediate insulating film of the ONO film, the top insulating film 23a may be formed by depositing silicon oxide by a CVD method, for example.

In the above embodiment, a silicon substrate whose surface is covered with a silicon oxide film can be used as the substrate. In this case, since the channel formation region is not formed in the silicon substrate, the quality is low and is 1/2 to 1 times smaller than that of a normal MOS LSI silicon substrate.
Since a silicon substrate with a price of ３ can be used, a significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and a tunnel insulating film can be formed.

Third Embodiment FIG. 9 is a sectional view of a semiconductor nonvolatile memory device according to the third embodiment . The semiconductor nonvolatile semiconductor of the second embodiment is substantially the same as the semiconductor nonvolatile semiconductor memory according to the second embodiment except that insulators 22a and 23a that hold therein a nanocrystal 32c made of a conductor having an average particle diameter of 2 to 5 nm are formed as a charge storage layer. Memory transistors that are similar to volatile memory devices, can achieve significant cost reductions by using low-cost substrates such as glass substrates, and can operate at high speed with low voltages such as erase voltage. can do. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. .

The semiconductor non-volatile memory device of the present embodiment is different from the manufacturing method of the first embodiment in that the steps from the step of forming the tunnel insulating film to the step of forming the intermediate insulating film are replaced by the tunnel insulating film 22a. And intermediate insulating film 23
First, a silicon oxide film corresponding to a is formed, and silicon ions are ionized by controlling energy from the upper surface such that a Fowler-Nordheim type tunnel current at a distance of several nm from the lower layer in the film can be generated. It can be formed in the same manner as the manufacturing method of the first embodiment except that the nanocrystal 21c is formed in the silicon oxide film corresponding to the tunnel insulating film 22a and the intermediate insulating film 23a by implantation.

Fourth Embodiment FIG. 10 is a sectional view of a semiconductor nonvolatile memory device according to the fourth embodiment . For example, glass substrates such as non-alkali glass,
Alternatively, a base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an upper layer of the insulating substrate 10 made of a plastic substrate, and a metal such as Cr or Mo or a conductor such as polysilicon is formed on the upper layer. Erase gate 30 is formed. On the lower layer, a lower gate insulating film 2 made of, for example, silicon oxide
1 is formed. On the upper layer, a semiconductor layer 31b made of, for example, polysilicon and having a channel formation region is formed.

A thin tunnel insulating film 22a made of, for example, silicon oxide is formed on the semiconductor layer 31b, and a floating gate 32a made of, for example, polysilicon is formed on the tunnel insulating film 22a. An intermediate insulating film 23a made of a film (a stacked body of an oxide film-nitride film-oxide film) is formed, and a control gate 33a made of, for example, polysilicon is formed thereover. In the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. This allows control gate 3
A field effect transistor having a TFT structure has a floating gate 32a insulated by an insulating film between the channel formation region in the semiconductor layer 31b and the channel formation region 3a.

In the field effect transistor having the above structure, the floating gate 32a has a function of retaining charges in the film, and the tunnel insulating film 22a and the intermediate insulating film 23a
Has a role of confining charges in the floating gate 32a. Control gate 33a and semiconductor layer 3
By applying an appropriate voltage to a source / drain diffusion layer (not shown) in 1b, a Fowler-Nordheim type tunnel current is generated, and electrons are injected from the semiconductor layer 31b to the floating gate 32a through the tunnel insulating film 22a, or Electrons are emitted from the gate 32a to the semiconductor layer 31b. When electric charges are accumulated in the floating gate 32a, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes and the memory transistor becomes capable of storing data. For example, data can be erased by accumulating charges in the floating gate 32a, and data can be written by discharging charges accumulated in the floating gate 32a.

The above-described nonvolatile semiconductor memory device has the erase gate 30 under the semiconductor layer 31b with the lower gate insulating film 21 interposed therebetween. By applying an erase voltage (for example, a positive voltage) to the erase gate 30, data can be erased. Further, the erase gate 30 is formed so as to be connected to the erase gate of the adjacent memory transistor so that the erase gate 30 is shared by the entire memory array or the block unit. It is.

FIG. 11 is an equivalent circuit diagram of a NAND-type semiconductor nonvolatile memory device in which memory transistors having the structure shown in FIG. 10 are connected in series by 8 bits. Two select transistors for selecting the present NAND string are arranged at both ends of the NAND string composed of 8-bit memory transistors. One of the source / drain diffusion layers of this NAND string is connected to the bit line B, and the other is connected to the source line S. The erase gate is formed by connecting between 8 bits. The erase gate can be configured to be shared by the entire memory array or by block.
The number of memory transistors connected is not limited to eight, but may be any number.

In the above-mentioned NAND type semiconductor nonvolatile memory device, 1/2 of the data input / output contact is 8
The structure is shared by bit memory cells, and the bit has 1/16 contacts. Similarly,
The select gate and the source line are also shared by 8 bits, the area per bit is close to the area occupied by the memory transistor, and the memory cell area can be very small.
This is advantageous in terms of high integration, large capacity, and low cost.

As a data erasing method in the above-mentioned NAND type semiconductor nonvolatile memory device, as shown in FIG. 11, 0V is applied to the control gates CG of all NAND strings.
Alternatively, the low voltage Vcg is applied, and the high voltages V1 and V2 are applied to the selection gates SG1 and SG2 of the two selection transistors. Further, the high voltage Vbg is also applied to the erase gate BG. The source S and the bit line B are open. As a result, the electrons in the floating gate can be extracted by the Fowler-Nordheim tunnel phenomenon as in the NOR type, and the data in the entire NAND string can be erased collectively.

The semiconductor nonvolatile memory device having such a structure is as follows.
By using a low-cost substrate such as a glass substrate, a significant cost reduction can be realized, a voltage such as an erase voltage can be reduced, and a memory transistor which can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. . In addition, NAN is advantageous in terms of integration.
This is a semiconductor nonvolatile memory device having D-type memory cells and having an erase gate, which can erase data all at once.

In general, a structure having a conductor (erase gate 30) under the source / drain with an insulator (lower gate insulating film 21) therebetween via an insulator (lower gate insulating film 21) generates a capacitance between the two and causes a reduction in read speed. However, with the TFT structure, the junction capacitance is close to zero, and the insulator (lower gate insulating film 2) between the source / drain and the conductor (erase gate 30) is formed.
By increasing the film thickness of 1), the erase voltage is increased.
The above capacity can be reduced. Further, in AV applications and data storage applications, cost and large capacity are prioritized, and reading speed requirements are often not so strong.

Next, a method of manufacturing the semiconductor nonvolatile memory device of the present embodiment will be described. First, FIG.
As shown in (a), an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate.
Use In the subsequent steps, when a low melting point substrate such as the above glass substrate is used, the process temperature is set at 60 ° C.
For example, in the formation of an insulating film, a sputtering method or a chemical vapor deposition (Chemical vapor deposition) method is used.
ical Vapor Deposition (hereinafter referred to as CVD) method. Silicon oxide, silicon nitride, or the like is deposited on the insulating substrate 10 by, for example, a CVD method to form a base insulating film 20. Next, a metal such as Cr or Mo is deposited on the upper layer by, for example, a sputtering method,
Alternatively, sputtering method, plasma enhanced CV
Polysilicon is deposited by a D (PECVD) method, a low pressure CVD method, or the like to form the erase gate 30. Next, on the upper layer, for example, a sputtering method or PECVD
Method (preferably bias ECR (Electron Cyclotron R
an insulator such as silicon oxide or silicon nitride to a thickness of, for example, 20 nm.
The lower gate insulating film 21 is formed. The lower the thickness of the lower gate insulating film 21, the lower the erase voltage can be set.

Next, as shown in FIG. 12B, an amorphous silicon film having a thickness of 4 is formed on the lower gate insulating film 21 by, for example, a sputtering method or a CVD method.
The semiconductor layer 31 is formed by depositing 0 nm. In particular, according to the sputtering method or the low pressure CVD method, the later E
Irradiation with a laser beam in the LA step or the like is preferable because the incorporation of hydrogen into the insulating film, which causes scattering of the insulating film and formation of holes, is reduced. Furthermore, SiH ₄ or Si ₂ H
According to the low pressure CVD method using ₆ as a raw material, a silicon layer can be formed by a low-temperature process of 500 ° C. or less.

Next, as shown in FIG. 12C, the amorphous silicon semiconductor layer 31 is subjected to, for example, an ELA process.
Is crystallized into a polysilicon semiconductor layer 31a. E
Various beam shot methods are conceivable as the LA process.
From the viewpoint of smoothness and uniformity, single shot or multi-shot for each chip is preferable. Further, since the erasing gate 30 is provided in the lower layer and the thermal efficiency is not good, crystallization can be performed with good crystallinity and energy efficiency by heating the substrate. For example, at 400 ° C for 30
5 shots with energy of 0 mJ / cm ² , uniform 2 ×
Step and step with 2cm ² excimer laser beam
A repeat ELA process is performed. This crystallization is performed by low-temperature solid-phase crystallization (SPC) or ELA after SPC treatment.
It can also be performed by processing or the like.

Next, as shown in FIG. 13D, the resist film is patterned and the semiconductor layer 31a is patterned by photolithography to form a semiconductor layer 31b in which elements are separated into islands. Because of the TFT structure, element isolation can be easily performed as compared with an element isolation method such as a LOCOS method usually used in a conventional semiconductor device formed on a silicon wafer.

Next, as shown in FIG. 13E, a tunnel insulating film 22 is formed by depositing silicon oxide to a thickness of about 9 nm by, for example, a plasma CVD method. A particularly high-quality film is required as the tunnel insulating film 22, and in order to form it by a low-temperature process, an ECR (Electron Cyclotr
It is preferably formed by an on-resonance type plasma CVD method.

Next, as shown in FIG. 13F, polysilicon containing a conductive impurity is deposited on the upper layer of the tunnel insulating film 22 by, for example, a CVD method to form a floating gate layer 32. Alternatively, conductive impurities may be ion-implanted after depositing polysilicon. Next, an ONO film (a stacked insulating film of an oxide film, a nitride film, and an oxide film) is deposited on the entire surface by, for example, a CVD method, for example, by covering the floating gate layer 32, and the intermediate insulating film 2.
Form 3 Next, for example, C
Polysilicon is deposited by the VD method to form a control gate layer 33.

Next, patterning is performed by a photolithography process to form a control gate 33a, an intermediate insulating film 23a, a floating gate 32a, and a tunnel insulating film 22a in a self-aligned manner.
Next, for example, P is applied to the source / drain diffusion layer formation region using the control gate as a mask, for example, at 2 × 10 ¹⁵ io.
Ion implantation at a dose of ns / cm ²
A drain diffusion layer is formed, and furthermore, an RTA by an ELA method or a condition in which the glass is not melted, for example, a line scan.
An annealing process is performed by a (Rapid Thermal Annealing) method to activate impurity ions in the source / drain diffusion layers. Thus, the device shown in FIG. 10 can be formed. In the subsequent steps, an interlayer insulating film is formed by covering the control gate, contacts and the like are opened, and upper layer wirings such as bit lines are formed, whereby a desired semiconductor nonvolatile memory device can be obtained.

According to the method of manufacturing the semiconductor nonvolatile memory device of the present embodiment, the T which is a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass is used.
Since the FT is formed, a voltage such as an erase voltage can be reduced, and a semiconductor nonvolatile memory device having a memory transistor which can operate at high speed can be manufactured at a significantly reduced cost. In addition, a structure having an erase gate under the semiconductor layer via a lower gate insulating film can be formed, and by adopting a structure in which the erase gate is shared in the entire memory array or in block units, erasure in the entire memory array or block unit is performed. Batch erase for each sector is possible,
A NAND-type semiconductor nonvolatile memory device that is advantageous in terms of integration can be manufactured.

In the above embodiment, a silicon substrate whose surface is covered with a silicon oxide film can be used as the substrate. In this case, since the channel formation region is not formed in the silicon substrate, the quality is low and is 1/2 to 1 times smaller than that of a normal MOS LSI silicon substrate.
Since a silicon substrate with a price of ３ can be used, a significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and a tunnel insulating film can be formed.

Fifth Embodiment FIG. 14 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. As the charge storage layer, a thin tunnel insulating film (bottom insulating film) 22a made of, for example, silicon oxide is formed, and a charge trapping insulating film 24a made of, for example, silicon nitride is formed thereon. Except that a top insulating film 23a made of, for example, silicon oxide is formed, it is substantially the same as the semiconductor nonvolatile memory device of the fourth embodiment, and uses a low-cost substrate such as a glass substrate. As a result, significant cost reduction can be realized, a voltage such as an erase voltage can be reduced, and a memory transistor which can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. . Further, the present invention is a semiconductor non-volatile memory device which includes NAND type memory cells which are advantageous in terms of the degree of integration and which has an erase gate so that data can be collectively erased.

In the semiconductor nonvolatile memory device of the present embodiment, in the manufacturing method of the fourth embodiment, the charge trapping insulating film 24 is formed by depositing silicon nitride by CVD, for example, in place of the polysilicon floating gate layer.
Except for forming a, it can be formed in the same manner as in the manufacturing method of the fourth embodiment. Since a TFT is formed as a memory transistor having a charge storage layer on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor that can operate at high speed can be operated at a low voltage such as an erase voltage. The device can be manufactured at significantly lower cost. In addition, a structure having an erase gate under the semiconductor layer via a lower gate insulating film can be formed, and by adopting a structure in which the erase gate is shared in the entire memory array or in block units, erasure in the entire memory array or block unit is performed. Batch erase for each sector is possible,
A NAND-type semiconductor nonvolatile memory device that is advantageous in terms of integration can be manufactured.

The semiconductor nonvolatile memory device and the method of manufacturing the same according to the present invention are not limited to the above embodiment. For example, in the second and fifth embodiments, the MO
Although the memory transistor has the NOS structure, the MNO
It may have an S structure. Although the control gate and the floating gate have a single-layer structure, they may have a two-layer structure such as polycide, which is a laminate of polysilicon and tungsten silicide, or a multi-layer structure of three or more layers. As the substrate, in addition to a glass substrate and a plastic substrate, a silicon substrate whose surface is covered with a silicon oxide film can be used. Further, various structures such as an LDD structure may be adopted for the source / drain. The injection of charges into the charge storage layer may be performed in any case of writing or erasing data. In addition, various changes can be made without departing from the gist of the present invention.

[0096]

According to the semiconductor non-volatile memory device of the present invention, the use of a low-cost substrate such as a glass substrate makes it possible to realize a significant reduction in cost, and it is possible to reduce the voltage such as the erase voltage. Thus, a memory transistor which can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b of polysilicon or quasi-single-crystal silicon, the trap density in the semiconductor layer can be reduced, the gate swing value can be reduced, and the voltage such as the erase voltage can be further reduced. . In addition, N which is advantageous in terms of integration degree
This is a semiconductor nonvolatile memory device having AND-type memory cells and having an erase gate, which can erase data all at once.

According to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, the above-described semiconductor nonvolatile memory device of the present invention can be easily manufactured, and charge storage on a low-cost insulating substrate such as glass. Since a TFT which becomes a memory transistor having a layer is formed, a voltage such as an erase voltage can be reduced, and a semiconductor nonvolatile memory device having a memory transistor which can operate at high speed can be manufactured at a significantly reduced cost. it can. In addition, a structure having an erase gate under the semiconductor layer via a lower gate insulating film can be formed, and by adopting a structure in which the erase gate is shared in the entire memory array or in block units, erasure in the entire memory array or block unit is performed. It is possible to manufacture a NAND type semiconductor non-volatile memory device capable of batch erasing for each sector and advantageous in terms of integration degree.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a gate width and a gate length of a peripheral circuit transistor of the semiconductor nonvolatile memory device according to the first embodiment;
FIG. 5 is a diagram showing a relationship between an average grain size of polysilicon forming a gate and polysilicon.

FIG. 3A is an equivalent circuit diagram of the NOR type semiconductor nonvolatile memory device according to the first embodiment, and FIG. 3B is an equivalent circuit diagram for explaining an erase operation.

FIG. 4 is a sectional view showing a manufacturing process of the method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment;
(A) shows up to the step of forming the base insulating film, (b) shows the step of depositing the silicon semiconductor layer, and (c) shows the step of crystallization of the silicon semiconductor layer.

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
(D) shows up to an element isolation step of a semiconductor layer, (e) shows up to a tunnel insulating film forming step, and (f) shows up to a floating gate layer forming step.

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;
(G) shows up to the step of removing the floating gate layer in the peripheral circuit transistor formation region, (h) shows the step of forming the intermediate insulating film, and (i) shows the step of forming the control gate layer.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(J) shows up to the step of forming a resist film of the control gate of the memory transistor and the gate electrode pattern of the peripheral circuit transistor, and (k) shows up to the step of patterning and forming the control gate of the memory transistor and the gate electrode pattern of the peripheral circuit transistor.

FIG. 8 is a sectional view of a semiconductor nonvolatile memory device according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor nonvolatile memory device according to a third embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor nonvolatile memory device according to a fourth embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram for explaining an erasing operation of the semiconductor nonvolatile memory device according to the fourth embodiment.

FIGS. 12A and 12B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semi-semiconductor nonvolatile memory device according to a fourth embodiment, in which FIG. 12A illustrates a process until a lower gate insulating film is formed;
FIG. 4A shows a process up to a silicon semiconductor layer deposition process, and FIG.

13 is a cross-sectional view showing a step subsequent to that of FIG. 12, wherein (d) shows a step until an element isolation step of a semiconductor layer, (e) shows a step until a tunnel insulating film is formed, and (f) shows a control gate. Up to the step of forming the application layer.

FIG. 14 is a sectional view of a semiconductor nonvolatile memory device according to a fifth embodiment of the present invention.

FIG. 15 is an equivalent circuit diagram for explaining an erasing operation of a conventional NOR type semiconductor nonvolatile memory device.

FIG. 16 is an equivalent circuit diagram for explaining an erasing operation of a NAND type semiconductor nonvolatile memory device formed on a bulk silicon semiconductor substrate as a conventional example.

[Explanation of symbols]

Reference Signs List 10: insulating substrate, 20: base insulating film, 21: lower gate insulating film, 22, 22a: tunnel insulating film (bottom insulating film), 23, 23a: intermediate insulating film (top insulating film), 2
4a: charge storage insulating film, 25, 25a: gate insulating film (peripheral circuit transistor), 30: erase gate, 31,
31a, 31b: semiconductor layer, 32: layer for floating gate, 32a: floating gate, 33: layer for control gate, 33a: control gate, 33
a ': Gate electrode (peripheral circuit transistor).

Claims (76)

[Claims] 1. A semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, comprising: a semiconductor layer having a channel formation region formed on an insulating substrate made of glass or plastic; A thin film transistor which has a charge storage layer formed thereon, a control gate formed above the charge storage layer, and a source / drain region formed in connection with the channel formation region, and which serves as the memory transistor A semiconductor nonvolatile memory device in which is formed. 2. The semiconductor nonvolatile memory device according to claim 1, wherein said charge storage layer is a floating gate made of a conductor insulated by an insulating film. 3. The semiconductor nonvolatile memory device according to claim 2, wherein said memory transistor is connected in a NOR type. 4. The semiconductor nonvolatile memory device according to claim 2, wherein said memory transistor is connected in a NAND type. 5. The semiconductor nonvolatile memory device according to claim 4, further comprising: a lower gate insulating film formed below said semiconductor layer; and an erase gate formed below said lower gate insulating film. 6. The semiconductor nonvolatile memory device according to claim 5, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 7. The semiconductor nonvolatile memory device according to claim 2, wherein said charge storage layer is an insulator having a charge trap. 8. The nonvolatile semiconductor memory device according to claim 7, wherein the insulator having the charge trap is a stacked insulating film of an oxide film-nitride film-oxide film or a stacked insulating film of a nitride film-oxide film. 9. The semiconductor non-volatile memory device according to claim 7, wherein the insulator having the charge trap is an insulator that holds therein a nanocrystal made of a conductor having an average particle diameter of 2 to 5 nm. 10. The semiconductor nonvolatile memory device according to claim 7, wherein said memory transistor is connected in a NOR type. 11. The semiconductor nonvolatile memory device according to claim 7, wherein said memory transistors are connected in a NAND type. 12. The nonvolatile semiconductor memory device according to claim 11, further comprising: a lower gate insulating film formed below said semiconductor layer; and an erase gate formed below said lower gate insulating film. 13. The semiconductor nonvolatile memory device according to claim 12, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 14. The semiconductor nonvolatile memory device according to claim 1, wherein said semiconductor layer is formed of polysilicon or quasi-single-crystal silicon. 15. The semiconductor nonvolatile memory device according to claim 14, further comprising a transistor for a peripheral circuit on said substrate. 16. A gate width of the gate of the transistor for the peripheral circuit is larger than a gate length of the gate and an average grain size of polysilicon forming the gate.
6. The nonvolatile semiconductor memory device according to item 5. 17. The nonvolatile semiconductor memory device according to claim 14, wherein said charge storage layer is a floating gate made of a conductor insulated by an insulating film. 18. The semiconductor nonvolatile memory device according to claim 17, wherein said memory transistor is connected in a NOR type. 19. The semiconductor nonvolatile memory device according to claim 17, wherein said memory transistor is connected in a NAND type. 20. The semiconductor nonvolatile memory device according to claim 19, further comprising: a lower gate insulating film formed below the semiconductor layer; and an erase gate formed below the lower gate insulating film. 21. The semiconductor nonvolatile memory device according to claim 20, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 22. The semiconductor nonvolatile memory device according to claim 14, wherein said charge storage layer is an insulator having a charge trap. 23. The semiconductor non-volatile memory device according to claim 22, wherein the insulator having the charge trap is a stacked insulating film of an oxide film-nitride film-oxide film or a stacked insulating film of a nitride film-oxide film. 24. The semiconductor non-volatile memory device according to claim 22, wherein the insulator having the charge trap is an insulator that holds therein a nanocrystal made of a conductor having an average particle diameter of 2 to 5 nm. 25. The semiconductor nonvolatile memory device according to claim 22, wherein said memory transistor is connected in a NOR type. 26. The semiconductor nonvolatile memory device according to claim 22, wherein said memory transistors are connected in a NAND type. 27. The semiconductor nonvolatile memory device according to claim 26, further comprising: a lower gate insulating film formed below the semiconductor layer; and an erase gate formed below the lower gate insulating film. 28. The semiconductor nonvolatile memory device according to claim 27, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 29. A semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, wherein a channel forming region formed on an insulating substrate which is a silicon substrate whose surface is covered with a silicon oxide film is provided. A semiconductor layer formed of quasi-single-crystal silicon, a charge storage layer formed on the semiconductor layer, a control gate formed above the charge storage layer, and a connection formed with the channel formation region. And a source / drain region, wherein a thin film transistor serving as the memory transistor is formed. 30. The semiconductor nonvolatile memory device according to claim 29, further comprising a peripheral circuit transistor on said substrate. 31. A gate width of the gate of the peripheral circuit transistor is larger than a gate length of the gate and an average grain size of polysilicon forming the gate.
0. A nonvolatile semiconductor memory device according to item 0. 32. The semiconductor nonvolatile memory device according to claim 29, wherein said charge storage layer is a floating gate made of a conductor insulated by an insulating film. 33. The semiconductor nonvolatile memory device according to claim 32, wherein said memory transistor is connected in a NOR type. 34. The semiconductor nonvolatile memory device according to claim 32, wherein said memory transistor is connected in a NAND type. 35. The semiconductor nonvolatile memory device according to claim 34, further comprising: a lower gate insulating film formed below the semiconductor layer; and an erase gate formed below the lower gate insulating film. 36. The nonvolatile semiconductor memory device according to claim 35, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 37. The nonvolatile semiconductor memory device according to claim 29, wherein said charge storage layer is an insulator having a charge trap. 38. The semiconductor nonvolatile memory device according to claim 37, wherein the insulator having the charge trap is a stacked insulating film of an oxide film-nitride film-oxide film or a stacked insulating film of a nitride film-oxide film. 39. The semiconductor non-volatile memory device according to claim 37, wherein the insulator having the charge trap is an insulator that holds therein a nanocrystal made of a conductor having an average particle diameter of 2 to 5 nm. 40. The semiconductor nonvolatile memory device according to claim 37, wherein said memory transistor is connected in a NOR type. 41. The semiconductor nonvolatile memory device according to claim 37, wherein said memory transistors are connected in a NAND type. 42. The semiconductor nonvolatile memory device according to claim 41, further comprising: a lower gate insulating film formed below said semiconductor layer; and an erase gate formed below said lower gate insulating film. 43. The nonvolatile semiconductor memory device according to claim 42, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 44. A semiconductor non-volatile memory device to which a memory transistor having a charge storage layer is connected, wherein a channel forming region formed on an insulating substrate which is a silicon substrate whose surface is covered with a silicon oxide film is provided. A semiconductor layer formed of polysilicon having a charge storage layer formed on the semiconductor layer, a control gate formed above the charge storage layer, and a channel formation region. A source / drain region, a thin film transistor serving as the memory transistor is formed, a peripheral circuit transistor is provided on the substrate, and a gate width of the gate of the peripheral circuit transistor is the gate of the gate. A semiconductor non-volatile memory device having a length greater than an average grain size of polysilicon forming the gate. 45. The nonvolatile semiconductor memory device according to claim 44, wherein said charge storage layer is a floating gate made of a conductor insulated by an insulating film. 46. The semiconductor nonvolatile memory device according to claim 45, wherein said memory transistor is connected in a NOR type. 47. The semiconductor nonvolatile memory device according to claim 45, wherein said memory transistor is connected in a NAND type. 48. The nonvolatile semiconductor memory device according to claim 47, further comprising: a lower gate insulating film formed below said semiconductor layer; and an erase gate formed below said lower gate insulating film. 49. The semiconductor nonvolatile memory device according to claim 48, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 50. The semiconductor nonvolatile memory device according to claim 44, wherein said charge storage layer is an insulator having a charge trap. 51. The nonvolatile semiconductor memory device according to claim 50, wherein the insulator having the charge trap is a stacked insulating film of an oxide film-nitride film-oxide film or a stacked insulating film of a nitride film-oxide film. 52. The semiconductor non-volatile memory device according to claim 50, wherein the insulator having the charge trap is an insulator holding therein a nanocrystal made of a conductor having an average particle diameter of 2 to 5 nm. 53. The semiconductor nonvolatile memory device according to claim 50, wherein said memory transistor is connected in a NOR type. 54. The semiconductor nonvolatile memory device according to claim 50, wherein said memory transistors are connected in a NAND type. 55. The semiconductor nonvolatile memory device according to claim 54, further comprising: a lower gate insulating film formed below the semiconductor layer; and an erase gate formed below the lower gate insulating film. 56. The semiconductor nonvolatile memory device according to claim 55, wherein said erase gate is formed so as to be connected to at least an erase gate of an adjacent memory transistor. 57. A method of manufacturing a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, comprising: forming a semiconductor layer having a channel formation region on an insulating substrate made of glass or plastic; Forming a charge storage layer above the semiconductor layer; forming a control gate above the charge storage layer; and forming source / drain regions connected to the channel formation region. A method for manufacturing a semiconductor nonvolatile memory device for forming a thin film transistor serving as the memory transistor. 58. The method according to claim 57, wherein the steps after the step of forming the semiconductor layer are performed at a temperature of 600 ° C. or less. 59. The method according to claim 57, wherein said step of forming a semiconductor layer includes a step of forming a silicon layer and a step of crystallizing said silicon layer by excimer laser annealing or low-temperature solid-phase crystallization. A method for manufacturing a semiconductor nonvolatile memory device. 60. The step of forming the silicon layer comprises the step of forming Si ₂ H
60. The method for manufacturing a nonvolatile semiconductor memory device according to claim 59, wherein the method is a step of forming by a CVD (chemical vapor deposition) method using ₆ as a raw material. 61. The method according to claim 60, wherein said CVD method is a low pressure CVD method or a plasma CVD method. 62. The step of forming the silicon layer comprises the step of forming SiH ₄
60. The method for manufacturing a nonvolatile semiconductor memory device according to claim 59, wherein the method is a step of forming by a CVD (Chemical Vapor Deposition) method using as a material. 63. The method according to claim 62, wherein said CVD method is a low pressure CVD method or a plasma CVD method. 64. The method according to claim 59, wherein the step of forming the silicon layer is a step of forming by a sputtering method. 65. A step of forming the charge storage layer, comprising: forming a gate insulating film on the semiconductor layer; forming a floating gate made of a conductor on the gate insulating film; 58. The method for manufacturing a semiconductor nonvolatile memory device according to claim 57, further comprising: forming an intermediate insulating film on the floating gate. 66. The method according to claim 65, wherein said memory transistor is formed by connecting to a NOR type. 67. The method according to claim 65, wherein said memory transistors are formed by connecting them in a NAND type. 68. The method according to claim 68, further comprising, before the step of forming the semiconductor layer, a step of forming an erase gate on the insulating substrate, and a step of forming a lower gate insulating film on the erase gate. 68. The method for manufacturing a semiconductor nonvolatile memory device according to 67. 69. The method according to claim 57, wherein the step of forming the charge storage layer is a step of forming an insulator having a charge trap above the semiconductor layer. 70. The method according to claim 69, wherein said memory transistor is formed by connecting to a NOR type. 71. The method according to claim 69, wherein said memory transistors are formed by connecting them in a NAND type. 72. The method according to claim 72, further comprising, before the step of forming the semiconductor layer, a step of forming an erase gate on the insulating substrate, and a step of forming a lower gate insulating film on the erase gate. 71. The method for manufacturing a semiconductor nonvolatile memory device according to 71. 73. A method for manufacturing a semiconductor non-volatile memory device having a first transistor which is a memory transistor having a charge storage layer and a second transistor for a peripheral circuit, wherein the silicon has a surface coated with a silicon oxide film. Forming a first semiconductor layer having a first channel forming region for the first transistor in a first transistor forming region on an insulating substrate as a substrate or an insulating substrate made of glass or plastic; Forming a second semiconductor layer having a second channel formation region for the second transistor, forming a charge storage layer on the first semiconductor layer, and forming a gate insulating film on the second semiconductor layer Forming a control gate above the charge storage layer;
Forming a gate electrode above the gate insulating film; forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region A method for manufacturing a semiconductor nonvolatile memory device comprising: 74. A step of forming a charge storage layer on the first semiconductor layer, comprising forming a tunnel insulating film on the first semiconductor layer and forming a floating gate on the tunnel insulating film. 74. The nonvolatile semiconductor memory device according to claim 73, further comprising: a step of forming an intermediate insulating film on the floating gate. 75. The semiconductor non-volatile memory device according to claim 73, wherein the step of forming a charge storage layer above the first semiconductor layer is a step of forming an insulator having a charge trap above the first semiconductor layer. . 76. A method of manufacturing a semiconductor nonvolatile memory device having a first transistor having a charge storage layer and a second transistor for a peripheral circuit, wherein a surface of the first transistor formation region is covered with a silicon oxide film. Forming an erase gate on an insulative substrate or an insulative substrate made of glass or plastic, which is an etched silicon substrate; forming a lower gate insulating film on an upper layer of the erase gate; Forming a first semiconductor layer having a first channel forming region for the first transistor in an upper layer of the film, and forming a second semiconductor layer having a second channel forming region for the second transistor on the substrate in the second transistor forming region; Forming a semiconductor layer; forming a charge storage layer on the first semiconductor layer; and forming a charge storage layer on the second semiconductor layer. Forming a control gate above the charge storage layer; and
Forming a gate electrode above the gate insulating film; forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region A method for manufacturing a semiconductor nonvolatile memory device comprising: