JPH1197526A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To solve various problems that have occurred when forming an embedded wiring having a large line width. SOLUTION: A step of forming a first metal film 103 on a main surface side of a semiconductor substrate 101, a step of forming a resist 104 on the first metal film 103, and a first metal film using the resist 104 as a mask Forming a first wiring 103 by processing the first wiring 103, forming an insulating film 105 covering the first wiring 103, flattening the insulating film 105, and forming the first insulating film 105 on the flattened insulating film 105. The method includes a step of forming a groove 107 and a step of forming a second wiring 108 by embedding a second metal film in the groove 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, LSIs have been widely used in important parts of computers and communication devices, and the performance of the entire device has
This is greatly related to the performance of SI alone. The performance improvement of the LSI alone is realized by increasing the degree of integration, that is, by miniaturizing elements. However, since the width and the wiring space of the wiring are reduced by the miniaturization, there is a problem that a void (hollow) is generated in the interlayer insulating film in the wiring space,
The problem that processing of wiring metal becomes difficult has begun to appear.

A damascene wiring formed by embedding a wiring metal in a groove can solve the problem of generation of voids in an interlayer insulating film and difficulty in processing the wiring metal, and has the advantage that the wiring and the interlayer connection hole can be simultaneously filled with metal. is there. However, this damascene wiring has the following problems. In the damascene wiring, unnecessary metal is removed by chemical mechanical polishing after filling the metal in the wiring groove,
At this time, in the case of a wide wiring, a phenomenon called thinning occurs in which even the wiring in the wiring groove is removed and becomes thin. In order to avoid this phenomenon, a wide wiring is divided into widths in which thinning does not occur (wiring division) to prevent thinning. However, when this wiring division is performed, there is a problem that it is necessary to find a wide wiring at the time of designing an LSI and to divide the wiring, and the area of a pattern for compensating electric resistance of the divided wiring is required. Had to be increased.

[0004]

As described above, damascene wiring is conventionally used in order to avoid problems caused by reduction in wiring width and wiring space caused by miniaturization. However, this damascene wiring has a large width. There is a problem that thinning occurs in the wiring area. In addition, when wiring division is performed to prevent this thinning, it is necessary to find a wide wiring in LSI design and to divide the wiring, thereby increasing the burden on the designer. In order to compensate for the electric resistance of the divided wirings, the area of the pattern must be increased, which causes a problem that the chip size increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and a semiconductor device capable of solving various problems that have arisen when forming a buried wiring having a large line width, and a method of manufacturing the same. The aim is to provide a method.

[0006]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a multi-layer wiring structure comprising a plurality of wiring layers. The wiring is formed by processing the first metal film using a predetermined mask pattern as a mask, and the second wiring is formed by embedding the second metal film in a groove formed in the insulating film. .

As described above, according to the present invention, the first wiring is formed by a process such as photolithography and etching with respect to the first and second wirings formed on the same wiring layer, and the second wiring is formed. Is to form a damascene wiring or the like by an embedding process. By using such a method, the line width of the first wiring can be widened and the line width of the second wiring can be narrowed, so that the problem of thinning that has conventionally occurred in the wide line width of the damascene wiring is obtained. Can be solved, and there is no need to perform wiring division for preventing thinning. Therefore, the problem of increasing the burden on the designer due to the work of dividing the wiring when designing the LSI and the problem of increasing the chip area and increasing the area of the pattern to compensate for the electric resistance of the divided wiring are solved. can do.

In the case where the first wiring is formed before the second wiring, a step of forming a first metal film on the main surface side of the semiconductor substrate, and a step of forming a mask pattern on the first metal film Forming a first wiring by processing the first metal film using the mask pattern as a mask; forming an insulating film covering the first wiring; A step of planarizing the film, a step of forming a groove in the flattened insulating film, and embedding a second metal film in the groove (preferably, embedding by chemical mechanical polishing). And a step of forming a wiring.

In this case, an insulating film may be formed via a stopper film covering the first wiring, and the insulating film may be planarized by chemical mechanical polishing using the stopper film as a stopper. With this configuration, when the insulating film is planarized, the first wiring is prevented from being polished by the stopper film formed on the first wiring. Also,
When a groove is formed in the insulating film by etching, the etching can be stopped by the stopper film. Further, when the second metal film is embedded in the groove by chemical mechanical polishing to form the second wiring, the first wiring is polished by the stopper film formed on the first wiring. Is prevented.

Further, a mask pattern is formed via a stopper film formed on the first metal film, and the stopper film remaining on the first wiring in the step of forming the first wiring is used as a chemical mechanical device. The insulating film may be planarized by mechanical polishing. With this configuration, when the insulating film is planarized, the first wiring is prevented from being polished by the stopper film formed on the first wiring. When the second metal film is embedded in the groove by chemical mechanical polishing to form the second wiring, the first wiring is polished by the stopper film formed on the first wiring. Is prevented.

When the second wiring is formed before the first wiring, a step of forming an insulating film on the main surface side of the semiconductor substrate, a step of forming a groove in the insulating film, and a step of forming the groove in the insulating film Second
Forming a second wiring by embedding (preferably, embedding by chemical mechanical polishing) a metal film of the above, and forming a first metal film on the insulating film and the second wiring And forming a first wiring by processing the first metal film using a mask pattern as a mask.

In this case, a first metal film is formed via a stopper film formed on the insulating film and the second wiring, and the first metal film is etched by using the stopper film as a stopper to form the first metal film. May be formed. With this configuration, when the first metal film is etched, the stopper film formed on the second wiring prevents the second wiring from being etched.

Further, according to the present invention, in a semiconductor device having a multilayer wiring structure including a plurality of wiring layers, the first wiring and the second wiring formed on the same wiring layer have different line widths, and It is characterized by being formed of different metal materials.

As described above, by using different metal materials for the first metal film used for the first wiring and the second metal film used for the second wiring, each of the first metal film and the second metal film can be used alone in an etching process or the like. And the reliability of the wiring can be improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process cross-sectional view illustrating a manufacturing process according to the first embodiment. First, FIG.
As shown in (a), the semiconductor substrate 1 on which the element formation has been completed
A silicon oxide film 102 serving as an interlayer insulating film is deposited on the substrate 01 (especially in a silicon substrate, the same applies to other embodiments) by a method such as CVD. Next, among the first-layer wirings, for example, an aluminum film 10 is used as a metal film to be the first wiring.
3 is deposited using a method such as a sputtering method. Thereafter, a resist pattern 104 for forming a pattern of the first wiring is formed by a lithography technique (eg, application, exposure, and development of a resist). Note that the first wiring has a line width enough to cause thinning.

Next, as shown in FIG. 1B, an aluminum film is processed into the first wiring 103 by dry etching using the resist 104 as a mask. After that, the resist 104 is removed by oxygen ashing or the like.

Next, as shown in FIG. 1C, a fluorine-added silicon oxide film 105 serving as an interlayer insulating film is deposited on the entire surface of the substrate. Next, as shown in FIG. 1D, the interlayer insulating film 105 is flattened by a method such as a chemical mechanical polishing method until the upper surface of the first wiring 103 is exposed. afterwards,
A resist pattern 106 for forming a second wiring pattern is formed by lithography. Note that the line width of the second wiring is a line width that does not cause thinning.

Next, as shown in FIG. 1E, a wiring groove 107 for burying the second wiring is formed by dry etching using the resist 106 as a mask. afterwards,
The resist 106 is removed by oxygen ashing or the like.

Next, as shown in FIG. 1F, an aluminum film 108 is deposited on the entire surface of the substrate as a metal film to be a second wiring by using a method such as a sputtering method.
Next, as shown in FIG. 1G, the aluminum film is left only in the wiring groove 107 by using a chemical mechanical polishing method or the like, and a second wiring 108 serving as a buried wiring is formed.

Next, as shown in FIG. 1H, an interlayer insulating film 109 is formed on the entire surface of the substrate, and then a second insulating film 109 is formed on the interlayer insulating film 109 via the connecting metal 110 filled in the connection hole. The wiring 111 of the layer is formed. Second-layer wiring 111
May be formed using lithography and etching in the same manner as the first wiring 103 according to the line width,
Similarly to the second wiring 108, it may be formed by embedding in a groove using a chemical mechanical polishing method.

FIG. 2 is a process sectional view showing a manufacturing process according to the second embodiment. First, as shown in FIG. 2A, a silicon oxide film 202 serving as an interlayer insulating film is deposited on a semiconductor substrate 201 on which device formation has been completed by using a method such as CVD. Next, for example, an aluminum film 203 is deposited as a metal film to be a first wiring by using a method such as a sputtering method. After that, a resist pattern 204 for forming a first wiring pattern is formed by a lithography technique. Note that the first wiring has a line width enough to cause thinning.

Next, as shown in FIG. 2B, an aluminum film is processed into the first wiring 203 by dry etching using the resist 204 as a mask. After that, the resist 204 is removed by oxygen ashing or the like. continue,
A silicon nitride film 205 serving as a stopper film for etching at the time of chemical mechanical polishing and groove processing is deposited on the entire surface of the substrate.

Next, as shown in FIG. 2C, a fluorine-added silicon oxide film 206 serving as an interlayer insulating film is deposited on the entire surface of the substrate. Next, as shown in FIG. 2D, the interlayer insulating film 206 is flattened by using a method such as a chemical mechanical polishing method until the upper surface of the stopper film 205 is exposed. At this time, since the stopper film 205 is provided on the first wiring 203, the first wiring 203 is prevented from being polished.
After that, a resist pattern 207 for forming a second wiring pattern is formed by a lithography technique. Note that the line width of the second wiring is a line width that does not cause thinning.

Next, as shown in FIG. 2E, a wiring groove 208 for burying the second wiring is formed by dry etching using the resist 207 as a mask. At this time, the etching can be stopped by the stopper film 205 and the etching of the interlayer insulating film 202 can be prevented. After that, the resist 207 is removed by oxygen ashing or the like.

Next, as shown in FIG. 2F, for example, an aluminum film 209 is deposited on the entire surface of the substrate as a metal film to be a second wiring by a method such as a sputtering method.
Next, as shown in FIG.
Is left only in the wiring groove 208 by using a chemical mechanical polishing method or the like to form a second wiring 209 to be a buried wiring. At this time, since the stopper film 205 is formed over the first wiring 203, the first wiring 203 is prevented from being polished.

Next, as shown in FIG. 2H, an interlayer insulating film 210 is formed on the entire surface of the substrate, and then a second insulating film 210 is formed on the interlayer insulating film 210 via the connecting metal 211 filled in the connection hole. The wiring 212 of the layer is formed. Second layer wiring 212
May be formed using lithography and etching in the same manner as the first wiring 203 depending on the line width,
As in the case of the second wiring 209, it may be formed by embedding in a groove using a chemical mechanical polishing method.

FIG. 3 is a process sectional view showing a manufacturing process according to the third embodiment. First, as shown in FIG. 3A, a silicon oxide film 302 serving as an interlayer insulating film is deposited on a semiconductor substrate 301 on which device formation has been completed by using a method such as CVD. Next, for example, an aluminum film 303 is deposited as a metal film to be a first wiring by using a method such as a sputtering method. Subsequently, a silicon nitride film 304 serving as a stopper film during chemical mechanical polishing is deposited. After that, a resist pattern 305 for forming a first wiring pattern is formed by a lithography technique. Note that the first wiring has a line width enough to cause thinning.

Next, as shown in FIG. 3B, the silicon nitride film 304 and the aluminum film 303 are processed by dry etching using the resist 305 as a mask to form a first wiring. After that, the resist 305 is removed by oxygen ashing or the like.

Next, as shown in FIG. 3C, a fluorine-added silicon oxide film 306 serving as an interlayer insulating film is deposited on the entire surface of the substrate. Next, as shown in FIG. 3D, the interlayer insulating film 306 is flattened by using a method such as a chemical mechanical polishing method until the upper surface of the stopper film 304 is exposed. At this time, since the stopper film 304 is on the first wiring 303, the first wiring 303 is prevented from being polished.
After that, a resist pattern 307 for forming a second wiring pattern is formed by a lithography technique. Note that the line width of the second wiring is a line width that does not cause thinning.

Next, as shown in FIG. 3E, a wiring groove 308 for embedding the second wiring is formed by dry etching using the resist 307 as a mask. afterwards,
The resist 307 is removed by oxygen ashing or the like.

Next, as shown in FIG. 3F, for example, an aluminum film 309 is deposited on the entire surface of the substrate as a metal film to be a second wiring by using a method such as a sputtering method.
Next, as shown in FIG.
Is left only in the wiring groove 308 by using a chemical mechanical polishing method or the like to form a second wiring 309 serving as an embedded wiring. At this time, since the stopper film 304 is formed over the first wiring 303, the first wiring 303 is prevented from being polished.

Next, as shown in FIG. 3 (h), an interlayer insulating film 310 is formed on the entire surface of the substrate, and then a second insulating film 310 is formed on the interlayer insulating film 310 via the connection metal 311 filled in the connection holes. The wiring 312 of the layer is formed. Second layer wiring 312
May be formed using lithography and etching in the same manner as the first wiring 303 according to the line width,
As in the case of the second wiring 309, the second wiring 309 may be formed by embedding in a groove using a chemical mechanical polishing method.

FIG. 4 is a process sectional view showing a manufacturing process according to the fourth embodiment. First, as shown in FIG. 4A, a silicon oxide film 402 serving as an interlayer insulating film is deposited on a semiconductor substrate 401 on which device formation has been completed by using a method such as CVD. Next, a fluorine-added silicon oxide film 403 serving as an interlayer insulating film is deposited. Thereafter, a resist pattern 404 for forming a groove pattern for embedding the second wiring among the wirings of the first layer is formed by a lithography technique. Note that the second wiring has a line width that does not cause thinning.

Next, as shown in FIG. 4B, after forming a wiring groove 405 for burying the second wiring by etching using the resist 404 as a mask, the resist 404 is removed by oxygen ashing or the like. Subsequently, for example, an aluminum film 406 is deposited on the entire surface of the substrate by a sputtering method or the like as a metal film to be a second wiring.

Next, as shown in FIG. 4C, a second wiring 406 is formed by leaving the aluminum film in the wiring groove 405 by using a chemical mechanical polishing method. Next, FIG.
As shown in (d), for example, an aluminum film 407 is deposited on the entire surface of the substrate as a metal to be a first wiring by a sputtering method or the like. After that, a resist pattern 408 for forming a first wiring pattern is formed by a lithography technique. Note that the first wiring has a line width enough to cause thinning.

Next, as shown in FIG. 4E, the aluminum film 407 is processed into a second wiring by a method such as a dry etching method using the resist 408 as a mask. After that, the resist 408 is removed by a method such as oxygen ashing.

Next, as shown in FIG. 4F, a fluorine-added silicon oxide film 409 serving as an interlayer insulating film is deposited on the entire surface of the substrate. Next, as shown in FIG. 4G, a second-layer wiring 411 is formed on the interlayer insulating film 409 via the connecting metal 410 filled in the connection hole of the interlayer insulating film 409. The second-layer wiring 411 may be formed by lithography and etching in the same manner as the first wiring 407, or may be formed by chemical mechanical processing in the same manner as the second wiring 405, depending on the line width. It may be formed by embedding in a groove using a mechanical polishing method.

FIG. 5 is a process sectional view showing a manufacturing process according to the fifth embodiment. First, as shown in FIG. 5A, a silicon oxide film 502 serving as an interlayer insulating film is deposited on a semiconductor substrate 501 on which device formation has been completed by using a method such as CVD. Next, a fluorine-added silicon oxide film 503 serving as an interlayer insulating film is deposited. After that, a resist pattern 504 for forming a groove pattern for embedding the second wiring among the wirings of the first layer is formed by a lithography technique. Note that the second wiring has a line width that does not cause thinning.

Next, as shown in FIG. 5B, after forming a wiring groove 505 for burying the second wiring by etching using the resist 504 as a mask, the resist 504 is removed by oxygen ashing or the like. Subsequently, for example, an aluminum film 506 is deposited on the entire surface of the substrate by a sputtering method or the like as a metal film to be a second wiring.

Next, as shown in FIG. 5C, a second wiring 506 is formed by leaving the aluminum film in the wiring groove 505 by using a chemical mechanical polishing method. Subsequently, a silicon nitride film 507 serving as a stopper film is deposited on the entire surface of the substrate.

Next, as shown in FIG. 5D, for example, an aluminum film 5
08 is deposited by a sputtering method or the like. After that, a resist pattern 509 for forming a pattern of the first wiring is formed by a lithography technique. Note that the first wiring has a line width enough to cause thinning.

Next, as shown in FIG. 5E, the aluminum film 508 is processed into a second wiring by a method such as a dry etching method using the resist 509 as a mask. At this time, since the etching of the aluminum film 508 is stopped by the stopper film 507, the second wiring 506 is prevented from being etched. Then, resist 5
09 is removed by a method such as oxygen ashing.

Next, as shown in FIG. 5F, a fluorine-added silicon oxide film 510 serving as an interlayer insulating film is deposited on the entire surface of the substrate. Next, as shown in FIG. 5G, a second-layer wiring 512 is formed on the interlayer insulating film 510 via the connecting metal 511 filled in the connection hole of the interlayer insulating film 510. The second-layer wiring 512 may be formed by lithography and etching in the same manner as the first wiring 508, or may be formed by chemical mechanical processing in the same manner as the second wiring 506, depending on the line width. It may be formed by embedding in a groove using a mechanical polishing method.

In the step shown in FIG. 5F, the stopper film 507 other than the stopper film 507 formed under the first wiring 508 is selectively removed, and then the interlayer insulating film and the Fluorine-added silicon oxide film 5
10 may be deposited. FIG. 5 in this case
Figures corresponding to (f) and (g) are shown in FIGS. 6 (f) and (g).
It was shown to.

As described in the above embodiments, the same wiring layer of the semiconductor device having the multilayer wiring structure is formed by filling the first wiring and the wiring groove formed by photolithography and etching with the wiring metal. By forming the first wiring and the second wiring so as to have a larger line width than the second wiring, thinning with a wide wiring can be prevented.

In each of the above embodiments, the first and second
The wiring was made of aluminum, but this may be an aluminum alloy film or another metal. For example, aluminum can be used for the first wiring and copper can be used for the second wiring. In this case, an etching process or the like (for example, FIG.
In the etching step (e), one metal can be selectively etched with respect to the other metal.
By using different kinds of metals for the first and second wirings as described above, each can be controlled independently, and the reliability of the wirings can be improved. Further, the first and second wirings may be used as a stacked film, and a barrier metal, an adhesion layer, an antireflection layer, or the like may be stacked on a base material of aluminum or copper.

Further, the interlayer insulating layer is not limited to an inorganic material such as a silicon oxide film as shown in each embodiment, but may be an organic material such as polyimide. Further, the stopper film is not limited to the silicon nitride film, and any other insulating film or conductive film can be used as long as it meets the purpose of stopping etching. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0048]

According to the present invention, for the first and second wirings formed on the same wiring layer, the first wiring is formed by photolithography and etching, and the second wiring is embedded. To form damascene wiring and the like. Therefore, the line width of the first wiring can be made wider and the line width of the second wiring can be made smaller, so that the problem of thinning which has conventionally occurred at a wide line width of the damascene wiring can be solved. Therefore, there is no need to perform wiring division for preventing thinning, and it is possible to solve problems such as an increase in chip size and an increase in burden on a designer.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a manufacturing process according to a third embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing a manufacturing process according to a fourth embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a manufacturing process according to a fifth embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing a modification of the manufacturing process according to the fifth embodiment of the present invention.

[Explanation of symbols]

101, 201, 301, 401, 501 ... semiconductor substrate 103, 203, 303, 407, 508 ... first wiring 104, 204, 305, 408, 509 ... resist pattern 105, 206, 306, 403, 503 ... insulating film 107, 208, 308, 405, 505: groove 108, 209, 309, 406, 506: second wiring 205, 304, 507: stopper film

Claims (9)

[Claims] In a method of manufacturing a semiconductor device having a multilayer wiring structure including a plurality of wiring layers, a first wiring is a first metal film with respect to a first wiring and a second wiring formed in the same wiring layer. Is formed by processing using a predetermined mask pattern as a mask, and the second wiring is formed in a groove formed in the insulating film.
A method for manufacturing a semiconductor device, comprising: forming a semiconductor device by embedding a metal film. A step of forming a first metal film on the main surface of the semiconductor substrate; a step of forming a mask pattern on the first metal film; and a step of forming the first metal film using the mask pattern as a mask. Forming a first wiring by processing the film, forming an insulating film covering the first wiring, flattening the insulating film, and forming a groove in the flattened insulating film. And forming a second wiring by embedding a second metal film in the groove. 3. The method according to claim 1, wherein the insulating film is formed via a stopper film covering the first wiring, and the insulating film is planarized by chemical mechanical polishing using the stopper film as a stopper. 3. The method for manufacturing a semiconductor device according to item 2. 4. The step of forming the mask pattern via a stopper film formed on the first metal film, and using the stopper film left on the first wiring in the step of forming the first wiring as a stopper. 3. The method according to claim 2, wherein the insulating film is planarized by chemical mechanical polishing. 5. A step of forming an insulating film on the main surface side of the semiconductor substrate, a step of forming a groove in the insulating film, and forming a second wiring by embedding a second metal film in the groove. A step of forming a first metal film on the insulating film and the second wiring, and a step of forming the first wiring by processing the first metal film using a mask pattern as a mask And a method for manufacturing a semiconductor device. 6. The method according to claim 6, wherein the first metal film is formed via a stopper film formed on the insulating film and the second wiring, and the first metal film is etched using the stopper film as a stopper. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the first wiring is formed by: 7. The method of manufacturing a semiconductor device according to claim 1, wherein a line width of said first wiring is wider than a line width of said second wiring. 8. The semiconductor device according to claim 1, wherein different metal materials are used for the first metal film used for the first wiring and the second metal film used for the second wiring. 13. A method for manufacturing a semiconductor device according to 9. A semiconductor device having a multi-layer wiring structure including a plurality of wiring layers, wherein a first wiring and a second wiring formed in the same wiring layer have different line widths and different metal materials. A semiconductor device characterized by being formed of: