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JPS5481041A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5481041A
JPS5481041A JP14897677A JP14897677A JPS5481041A JP S5481041 A JPS5481041 A JP S5481041A JP 14897677 A JP14897677 A JP 14897677A JP 14897677 A JP14897677 A JP 14897677A JP S5481041 A JPS5481041 A JP S5481041A
Authority
JP
Japan
Prior art keywords
circuit
input
buffering
microprocessor
output unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14897677A
Other languages
Japanese (ja)
Other versions
JPS581812B2 (en
Inventor
Takeshi Kamimura
Yoichi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52148976A priority Critical patent/JPS581812B2/en
Publication of JPS5481041A publication Critical patent/JPS5481041A/en
Publication of JPS581812B2 publication Critical patent/JPS581812B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To prevent the undesirable overrun from being caused, to the read/write to the input and output unit, by increasing the flexibility in data transfer.
CONSTITUTION: Between the input and output control circuit 3 controlling the input and output unit and the microprocessor 2 controlling the circuit 3 with higher processing speed than that of the input and output unit, the command buffer 5 buffering the command tranferring from the microprogram to the circuit 3, write data buffer 6 buffering the write data transferred from the mocroprogram to the circuit 3, and read data buffer 7 buffering the read data transferred from the circut 3 to the microprocessor 2 are provided, and between the microprocessor 2 and the circuit 3, the directo information transfer bus 8 bypassing the said buffers is provided.
COPYRIGHT: (C)1979,JPO&Japio
JP52148976A 1977-12-12 1977-12-12 data processing system Expired JPS581812B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52148976A JPS581812B2 (en) 1977-12-12 1977-12-12 data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52148976A JPS581812B2 (en) 1977-12-12 1977-12-12 data processing system

Publications (2)

Publication Number Publication Date
JPS5481041A true JPS5481041A (en) 1979-06-28
JPS581812B2 JPS581812B2 (en) 1983-01-13

Family

ID=15464882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52148976A Expired JPS581812B2 (en) 1977-12-12 1977-12-12 data processing system

Country Status (1)

Country Link
JP (1) JPS581812B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1132826A3 (en) * 2000-01-20 2004-10-06 Fujitsu Limited Bus control system for integrated circuit device with improved bus access efficiency

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6189278A (en) * 1984-10-08 1986-05-07 Sugimoto Seisakusho:Kk Method of bonding double-coated pressure-sensitive adhesive tape

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4937537A (en) * 1972-08-07 1974-04-08
JPS5195747A (en) * 1975-02-20 1976-08-21 Wan chitsupunyushutsuryokuseigyokairoomotsu johoshorishisutemu
JPS522230A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Multi-operation system using miicrocomputor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4937537A (en) * 1972-08-07 1974-04-08
JPS5195747A (en) * 1975-02-20 1976-08-21 Wan chitsupunyushutsuryokuseigyokairoomotsu johoshorishisutemu
JPS522230A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Multi-operation system using miicrocomputor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1132826A3 (en) * 2000-01-20 2004-10-06 Fujitsu Limited Bus control system for integrated circuit device with improved bus access efficiency
US6917995B2 (en) 2000-01-20 2005-07-12 Fujitsu Limited Bus control system for integrated circuit device with improved bus access efficiency
US7349998B2 (en) 2000-01-20 2008-03-25 Fujitsu Limited Bus control system for integrated circuit device with improved bus access efficiency

Also Published As

Publication number Publication date
JPS581812B2 (en) 1983-01-13

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