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JPS5512775A - Manufacturing method of semiconductor - Google Patents

Manufacturing method of semiconductor

Info

Publication number
JPS5512775A
JPS5512775A JP8585278A JP8585278A JPS5512775A JP S5512775 A JPS5512775 A JP S5512775A JP 8585278 A JP8585278 A JP 8585278A JP 8585278 A JP8585278 A JP 8585278A JP S5512775 A JPS5512775 A JP S5512775A
Authority
JP
Japan
Prior art keywords
wiring layer
layer
insulating film
silicone
side face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8585278A
Other languages
Japanese (ja)
Inventor
Keiji Nishimoto
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8585278A priority Critical patent/JPS5512775A/en
Publication of JPS5512775A publication Critical patent/JPS5512775A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE: To cause no disconnection in the second wiring layer formed on an insulating film by forming the first wiring layer to have a side face of a gentle incline and by rendering the above insulating film evenly thick.
CONSTITUTION: On an insulating film 2 on a base plate 1 is formed the first wiring layer 7 made of polycrystalline silicone, on which is formed the second wiring layer 9 with an insulating film 8 beneath it. In the middle section of the polycrystalline silicone layer forming the first wiring layer 7 is put a thin layer of oxidized silicone. Etching is performed on the polycrystalline silicone layer holding this oxidized silicone layer to form the first wiring layer 7 having a side face of a gradual incline.
COPYRIGHT: (C)1980,JPO&Japio
JP8585278A 1978-07-14 1978-07-14 Manufacturing method of semiconductor Pending JPS5512775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8585278A JPS5512775A (en) 1978-07-14 1978-07-14 Manufacturing method of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8585278A JPS5512775A (en) 1978-07-14 1978-07-14 Manufacturing method of semiconductor

Publications (1)

Publication Number Publication Date
JPS5512775A true JPS5512775A (en) 1980-01-29

Family

ID=13870394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8585278A Pending JPS5512775A (en) 1978-07-14 1978-07-14 Manufacturing method of semiconductor

Country Status (1)

Country Link
JP (1) JPS5512775A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6007590A (en) * 1996-05-03 1999-12-28 3M Innovative Properties Company Method of making a foraminous abrasive article

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6007590A (en) * 1996-05-03 1999-12-28 3M Innovative Properties Company Method of making a foraminous abrasive article

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