JPS5583251A - Method of fabricating semiconductor device - Google Patents

Abstract

PURPOSE:To arbitrarily control a transistor region for a peripheral circuit and a memory cell of SiO2 layer in thickness to a value corresponding to required characteristics without increasing the number of masking steps. CONSTITUTION:A memory cell region I and a transistor region II for a peripheral circuit are insulated to be separated via isolation layers 11 on a silicon substrate 1, a polycrystalline silicon electrode layer 2 is formed through an SiO2 film 12 thereon and extended on the layer 11, SiO2 films 15, 16 are coated thereon, and gate oxide films 13, 14 are formed thereon. A resist 8 is coated on the region II and B ion is implanted onto the region I to thereby control the threshold value of the transistor for a transfer. Then, an aluminum film 9 is coated thereon, the resist 8 is removed, and the SiO2 film 14 is removed. When the aluminum film 9 is then removed and an SiO2 film 14' is formed on the exposed substrate surface, the films 14', 15' and 16' increase their thicknesses. Thereafter, a second polycrystalline silicon layer is provided and patterned to thereby form predetermined gate electrodes 3, 4 and capacity electrode 2, a word wire 5. Thus, a multilayer wiring can be formed in high density, durability against voltage and high speed.