[go: up one dir, main page]

JPS57109084A - Schedule system for instruction in parallel computer having plural operating devices - Google Patents

Schedule system for instruction in parallel computer having plural operating devices

Info

Publication number
JPS57109084A
JPS57109084A JP55186147A JP18614780A JPS57109084A JP S57109084 A JPS57109084 A JP S57109084A JP 55186147 A JP55186147 A JP 55186147A JP 18614780 A JP18614780 A JP 18614780A JP S57109084 A JPS57109084 A JP S57109084A
Authority
JP
Japan
Prior art keywords
instructions
instruction
units
same
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55186147A
Other languages
Japanese (ja)
Other versions
JPS6132697B2 (en
Inventor
Yoshiyuki Tanakura
Yukio Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55186147A priority Critical patent/JPS57109084A/en
Publication of JPS57109084A publication Critical patent/JPS57109084A/en
Publication of JPS6132697B2 publication Critical patent/JPS6132697B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To execute instructions in parallel effectively to simplify hardware for parallel instruction execution, by inspecting an instruction sequence to be executed and giving the same identification name to instructions requiring serializing to serialize instructions including the memory access. CONSTITUTION:Plural scalar or vector operation units 16-1-16-N are provided, and instructions executed in units 16-1-16-N are inputted to a part 19 of a shared memory. Instructions of an object program 10 to be inputted to these units 16-1-16-N are fetched successively by an instruction fetch part 11 and are decoded by an instruction decoder 12, and the same ID is given to instructions which use the same memory area. Next, instructions are stacked in corresponding instruction queue stacks 14-1-14-N by an ID-classified instruction stack control part 14, and instructions of queue stacks 14-1-14-N are taken out to units 16-1-16-N by instruction stack taking-out parts 15-1-15-N and are serialized by the register reserve technique of a serializing control part 17 utilizing a register.
JP55186147A 1980-12-26 1980-12-26 Schedule system for instruction in parallel computer having plural operating devices Granted JPS57109084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55186147A JPS57109084A (en) 1980-12-26 1980-12-26 Schedule system for instruction in parallel computer having plural operating devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55186147A JPS57109084A (en) 1980-12-26 1980-12-26 Schedule system for instruction in parallel computer having plural operating devices

Publications (2)

Publication Number Publication Date
JPS57109084A true JPS57109084A (en) 1982-07-07
JPS6132697B2 JPS6132697B2 (en) 1986-07-29

Family

ID=16183195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55186147A Granted JPS57109084A (en) 1980-12-26 1980-12-26 Schedule system for instruction in parallel computer having plural operating devices

Country Status (1)

Country Link
JP (1) JPS57109084A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991546A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨンシステムズ・インコ−ポレ−テツド Central processing unit
JPS5991547A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨン・システムズ・インコ−ポレ−テツド collection device
JPS60120472A (en) * 1983-12-02 1985-06-27 Fujitsu Ltd Multiple loop vector processing method
JPS61100862A (en) * 1984-10-12 1986-05-19 Fujitsu Ltd Instruction serialization method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0561596U (en) * 1991-11-28 1993-08-13 セイキ工業株式会社 Protective cover for buried pipe

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110746A (en) * 1974-07-17 1976-01-28 Hitachi Ltd
JPS53108254A (en) * 1977-03-02 1978-09-20 Nec Corp Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110746A (en) * 1974-07-17 1976-01-28 Hitachi Ltd
JPS53108254A (en) * 1977-03-02 1978-09-20 Nec Corp Information processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991546A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨンシステムズ・インコ−ポレ−テツド Central processing unit
JPS5991547A (en) * 1982-10-13 1984-05-26 ハネウエル・インフオメ−シヨン・システムズ・インコ−ポレ−テツド collection device
JPS60120472A (en) * 1983-12-02 1985-06-27 Fujitsu Ltd Multiple loop vector processing method
JPS61100862A (en) * 1984-10-12 1986-05-19 Fujitsu Ltd Instruction serialization method

Also Published As

Publication number Publication date
JPS6132697B2 (en) 1986-07-29

Similar Documents

Publication Publication Date Title
JPS56149646A (en) Operation controller
EP0411747A2 (en) Multiple instruction decoder
EP0782071A3 (en) Data processor
EP0335515A3 (en) Method and apparatus for executing instructions for a vector processing system
EP0137191A3 (en) Virtual machine system controller
HK90795A (en) Data processing system with instruction tag apparatus
TW280879B (en)
DE3070051D1 (en) Pipeline control apparatus for generating instructions in a digital computer
JPS57109084A (en) Schedule system for instruction in parallel computer having plural operating devices
EP0354585A3 (en) Instruction pipeline microprocessor
EP0331191A3 (en) Information processing system capable of carrying out advanced execution
EP0297265A3 (en) An instruction control mechanism for a computer system
GB2016753A (en) Data Processing System
EP0299075A1 (en) Processing unit having at least one coprocessor
JP2538053B2 (en) Control device
JPS5790762A (en) Instruction control system
EP0762271A2 (en) Early completion of floating-point operations during load/store multiple operations
US4285036A (en) Data processing device using a subroutine call instruction
EP0333365A3 (en) Method and apparatus for handling asynchronous memory management exceptions by a vector processor
JPS54107239A (en) Program execution order control system
JPH01271840A (en) Microcomputer
JPS5523510A (en) Sequence control unit
JPS578851A (en) Parallel processing system
JPS556602A (en) Multiprocessor system
JPS6435630A (en) Information processor