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JPS57206063A - Semiconductor substrate and manufacture therefor - Google Patents

Semiconductor substrate and manufacture therefor

Info

Publication number
JPS57206063A
JPS57206063A JP56090936A JP9093681A JPS57206063A JP S57206063 A JPS57206063 A JP S57206063A JP 56090936 A JP56090936 A JP 56090936A JP 9093681 A JP9093681 A JP 9093681A JP S57206063 A JPS57206063 A JP S57206063A
Authority
JP
Japan
Prior art keywords
type
formation
region
layer
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56090936A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwasaki
Koichi Kanzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56090936A priority Critical patent/JPS57206063A/en
Priority to EP82302987A priority patent/EP0067661A1/en
Publication of JPS57206063A publication Critical patent/JPS57206063A/en
Priority to DE8419430U priority patent/DE8419430U1/en
Priority claimed from DE8419430U external-priority patent/DE8419430U1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To build a P and N islands separated from each other by a method wherein an opposite condutivity type layer is buried in a semicondcutor substrate and a semiconductor region of the same conductivity type is formed therein for the formation of a diffused region reaching the buried layer from the semiconcutor region primary surface. CONSTITUTION:An N type impurity is diffused into a P type substrate 3-1 of 10<14>-10<17>cm<-3> concentration with a patterned heat oxidized film 3-2 acting as a mask for the formation of a buried layer 3-3 with a sheet resistance of 3- 20OMEGA/mm.<2>. After the removal of the film 3-2, on the whole substrate surface a P type epitaxial layers 3-4 are grown with an impurity concentration 10<14>- 10<16>cm<-3>. P ions are implanted into the epitaxial layer 3-4 for the formation of a diffusion source 3-7. P is thermally diffused in an inert atmosphere for the formation of an N type well region 3-5 adjoining the buried layer 3-3. A P channel MOS is formed in the N type well region 3-5 and an N channel MOS in the P type epitaxial layers 3-4.
JP56090936A 1981-06-15 1981-06-15 Semiconductor substrate and manufacture therefor Pending JPS57206063A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56090936A JPS57206063A (en) 1981-06-15 1981-06-15 Semiconductor substrate and manufacture therefor
EP82302987A EP0067661A1 (en) 1981-06-15 1982-06-09 Semiconductor device and method for manufacturing the same
DE8419430U DE8419430U1 (en) 1981-06-15 1984-06-28 Snap hinge made of plastic

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP56090936A JPS57206063A (en) 1981-06-15 1981-06-15 Semiconductor substrate and manufacture therefor
DE8419430U DE8419430U1 (en) 1981-06-15 1984-06-28 Snap hinge made of plastic

Publications (1)

Publication Number Publication Date
JPS57206063A true JPS57206063A (en) 1982-12-17

Family

ID=25949967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56090936A Pending JPS57206063A (en) 1981-06-15 1981-06-15 Semiconductor substrate and manufacture therefor

Country Status (1)

Country Link
JP (1) JPS57206063A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220453A (en) * 1985-03-23 1986-09-30 エステイーシー　ピーエルシー Integrated circuit and its manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214388A (en) * 1975-07-25 1977-02-03 Hitachi Ltd Process for complementary insulated gate semiconductor integrated circuit device
JPS5239380A (en) * 1975-09-25 1977-03-26 Mitsubishi Electric Corp Semiconductor device
JPS5493981A (en) * 1978-01-09 1979-07-25 Toshiba Corp Semiconductor device
JPS56169359A (en) * 1980-05-30 1981-12-26 Ricoh Co Ltd Semiconductor integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214388A (en) * 1975-07-25 1977-02-03 Hitachi Ltd Process for complementary insulated gate semiconductor integrated circuit device
JPS5239380A (en) * 1975-09-25 1977-03-26 Mitsubishi Electric Corp Semiconductor device
JPS5493981A (en) * 1978-01-09 1979-07-25 Toshiba Corp Semiconductor device
JPS56169359A (en) * 1980-05-30 1981-12-26 Ricoh Co Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220453A (en) * 1985-03-23 1986-09-30 エステイーシー　ピーエルシー Integrated circuit and its manufacturing method

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