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JPS57203278A - Controlling method for hierarchical buffer - Google Patents

Controlling method for hierarchical buffer

Info

Publication number
JPS57203278A
JPS57203278A JP56086965A JP8696581A JPS57203278A JP S57203278 A JPS57203278 A JP S57203278A JP 56086965 A JP56086965 A JP 56086965A JP 8696581 A JP8696581 A JP 8696581A JP S57203278 A JPS57203278 A JP S57203278A
Authority
JP
Japan
Prior art keywords
buffer
data
pointers
storage device
indicating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56086965A
Other languages
Japanese (ja)
Inventor
Yosuke Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56086965A priority Critical patent/JPS57203278A/en
Publication of JPS57203278A publication Critical patent/JPS57203278A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To improve the throughput of queuing processing for a real time input by using a small capacitance buffer on a main memory storage together with a large capacitance buffer on an auxiliary storage device. CONSTITUTION:A queuing table having a buffer 10 on a main storage device and a buffer 11 on an auxiliary storage device is controlled by a hierarchical buffer controlling part 8, which is composed of a group of serial pointers 13-16 indicating the buffer storing status of data and a mode indicator 12 indicating the using status of the two buffers. When the buffer 10 is satisfied, the pointers 13, 14 indicate the same position. When data are read out from the buffer 10, the position of the buffer 10 in which read data have been stored is cleared, the position is detected by the positions of the pointers 13, 14. Subsequently, data in the buffer 11 are transferred to the buffer 10 by the volume of read data.
JP56086965A 1981-06-08 1981-06-08 Controlling method for hierarchical buffer Pending JPS57203278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56086965A JPS57203278A (en) 1981-06-08 1981-06-08 Controlling method for hierarchical buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56086965A JPS57203278A (en) 1981-06-08 1981-06-08 Controlling method for hierarchical buffer

Publications (1)

Publication Number Publication Date
JPS57203278A true JPS57203278A (en) 1982-12-13

Family

ID=13901579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56086965A Pending JPS57203278A (en) 1981-06-08 1981-06-08 Controlling method for hierarchical buffer

Country Status (1)

Country Link
JP (1) JPS57203278A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146348A (en) * 1984-01-10 1985-08-02 Nippon Telegr & Teleph Corp <Ntt> Hierarchy memory control system
US7841371B2 (en) 2005-11-30 2010-11-30 Tdk Corporation Lid opening/closing system of an airtight container

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146348A (en) * 1984-01-10 1985-08-02 Nippon Telegr & Teleph Corp <Ntt> Hierarchy memory control system
US7841371B2 (en) 2005-11-30 2010-11-30 Tdk Corporation Lid opening/closing system of an airtight container
US8082955B2 (en) 2005-11-30 2011-12-27 Tdk Corporation Lid opening/closing system of an airtight container
US8375998B2 (en) 2005-11-30 2013-02-19 Tdk Corporation Lid opening/closing system of an airtight container
US8413693B2 (en) 2005-11-30 2013-04-09 Tdk Corporation Lid opening/closing system of an airtight container

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