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JPS5736856A - Manufacture of complementary type insulated gate field effect semiconductor device - Google Patents

Manufacture of complementary type insulated gate field effect semiconductor device

Info

Publication number
JPS5736856A
JPS5736856A JP11170680A JP11170680A JPS5736856A JP S5736856 A JPS5736856 A JP S5736856A JP 11170680 A JP11170680 A JP 11170680A JP 11170680 A JP11170680 A JP 11170680A JP S5736856 A JPS5736856 A JP S5736856A
Authority
JP
Japan
Prior art keywords
channel
mos
type impurity
semiconductor device
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11170680A
Other languages
Japanese (ja)
Inventor
Takashi Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11170680A priority Critical patent/JPS5736856A/en
Publication of JPS5736856A publication Critical patent/JPS5736856A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a C-MOS having a variety of threshold voltages by injecting P type impurity in the channel regions of the first N-channel and P-channl MOS and injecting N type impurity in the second N-channel and P-channel MOS. CONSTITUTION:A P-well 2 and a thick field oxidized film 4 are formed on an N type silicon substrate 1. Then, with a photoresist as a mask P type impurity is injected in the channel region of the first N-channel and P-channel MOS to form injection regions 7, 8. Then, with the new photoresist 9 as a mask N type impurity ions 10 are injected in the channel region of the second N-channel and P-channel MOS to form injection regions 11, 12. Subsequently, a gate oxidized film 13 and a gate electrode 14 are formed, source and drain regions are formed to form a C-MOS semiconductor device. By varying the mask pattern the various threshold values can be provided in the MOS.
JP11170680A 1980-08-15 1980-08-15 Manufacture of complementary type insulated gate field effect semiconductor device Pending JPS5736856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11170680A JPS5736856A (en) 1980-08-15 1980-08-15 Manufacture of complementary type insulated gate field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11170680A JPS5736856A (en) 1980-08-15 1980-08-15 Manufacture of complementary type insulated gate field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS5736856A true JPS5736856A (en) 1982-02-27

Family

ID=14568082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11170680A Pending JPS5736856A (en) 1980-08-15 1980-08-15 Manufacture of complementary type insulated gate field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5736856A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210863A (en) * 1984-01-10 1985-10-23 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Complementary MOS integrated circuit and its manufacturing method
JPS61133656A (en) * 1984-12-03 1986-06-20 Hitachi Ltd Semiconductor device and its manufacturing method
JPS6276665A (en) * 1985-09-30 1987-04-08 Toshiba Corp Complementary semiconductor device
WO2001037333A1 (en) * 1999-11-18 2001-05-25 Intel Corporation Method of fabrication dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210863A (en) * 1984-01-10 1985-10-23 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Complementary MOS integrated circuit and its manufacturing method
JPS61133656A (en) * 1984-12-03 1986-06-20 Hitachi Ltd Semiconductor device and its manufacturing method
JPS6276665A (en) * 1985-09-30 1987-04-08 Toshiba Corp Complementary semiconductor device
WO2001037333A1 (en) * 1999-11-18 2001-05-25 Intel Corporation Method of fabrication dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
US6803285B2 (en) 1999-11-18 2004-10-12 Intel Corporation Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation

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