JPS58105578A - semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Technical field The present invention relates to devices with shallow junction gate structures.

BACKGROUND OF THE INVENTION Recently, many materials have been considered for use in semiconductor devices; silicon is currently used in the vast majority of such devices. This is true even though other materials, such as group compound semiconductors, have more potential than silicon for certain applications such as high-speed field effect transistors. ■-GaA, one of the V group materials
s has been extensively studied for use in field effect transistors. This is because such devices made from this material can be faster than silicon devices due to the high drift mobility of electrons in GaAs.

For example, other materials such as GaO, 47xno, 113As have higher mobility at low electric fields, making them suitable for FETs.
As such, it is potentially more attractive than GaAs. This composition, along with other compositions containing phosphorus, is of interest because it can be epitaxially grown in lattice i-coupling on InP substrates.

However, there is no suitable gate structure, and InGaAs
Field effect transistors have not reached the stage of development and at least partial commercial devices of GaAs FETs. For example, Abra Physics Letters
, 2 3 4 5 8-4 5 9
Page, October 15, 1973, a simple An/cao
, 47InO, 53AS contacts have been reported to have a barrier height of about 0.2 volts, which is too low for useful field effect transistors.

In order to overcome the drawback of not having a suitable gate structure,
Several methods have been used.

Device Letters) + 1 + 11
0 111 pages.

p-n produced by zrl diffusion in June 1980
We report an InGaAs junction field transistor with a junction gate. Although this device has the advantage of reducing gate leakage current due to a reverse biased pn junction, it has not been easy to fabricate such a device with a short channel length. Morgan et al.
csLetlersJ, 1 4, 7 3 7
7 3 8 pages, November 9, 1978,
Due to the presence of the thin SiOx layer, the barrier height is approximately 0.
．． Increased to 5 volts fr-InGaAs Schottky
Friend reporting the diode. The presence of the SiOx layer obviously increases the barrier height, but it is preferred because of the presence of a large number of trap levels that provide a field accumulation effect. In addition, to increase the Schottky barrier height, semi-insulating Alo, as In(1, GaI using HAs layer)
nAs FET was determined by Ohno et al.
ヱ(-eeeeee Chishikutro 2, Eba(:l L
/ 9 2:X (I EEE Ele'ctronD
evice Letters) l + 154-15
Reported on page 5 9 August 1980. Aj required to prevent essential tunneling current! The minimum thickness of the InAs layer is reported to be 20 nanometers (200 angstroms).

This causes significant field effects in the insulating layer.

There are other reports on methods to increase the Schottky barrier height for materials other than GaInAs. for example,
Bucher et al.
etters), 23-+ pp. 617-619,
December 1, 1973 1c, Cu-diffused Au/CdS
A friend reported that the junction increases the Schottky barrier height. Shannon (5hannon) is an Applied Physics Lecturer.
tters) + 25+ 75. -77 pages, 197
reported on July 1, 2013 that the Schottky barrier height of Ni-8i diodes was increased by using ion implantation to produce a shallow n-type layer on the underlying p-type layer. did.

SUMMARY OF THE INVENTION In accordance with the present invention, a thin (and heavily doped InGaAs layer) of -conductivity type is disposed on an InGaAs layer having a different conductivity type.
The GaAs layer increases the effective Schottky barrier height of the former InGaAs layer. In a preferred embodiment,
The latter layer is fully depleted and consists of n-type GaO,4? grown on an InP substrate. ■no, 53 As ・P-type Ga0.4 placed above? In6. ．． Consists of 3 Ali. In a further preferred embodiment, the resulting structure is used in a field effect transistor device.

Detailed Description InGa with increased Schottky barrier height according to the present invention
An As diode is shown in cross-section in FIG. For the sake of clarity, the elements of the device are shown in this drawing, as in the other drawings, not to scale. Devices generally designated 1 include an InP substrate 11. having a first conductivity type. A first epitaxial I nGaAa layer 13 having a first conductivity type, a second I nGaAs epitaxial layer 15 having a third conductivity type, and a third I nGaA layer having a second conductivity type.
It consists of an As epitaxial layer 17.

The layer is an InGaAs layer, but the resulting layer is an InP layer.
These layers may also contain other elements, such as phosphorus, as long as they are lattice matched to the substrate. Furthermore, it is layer 11 respectively.
and 17, and a Schottky contact 21. In one preferred embodiment, the second
The conductivity type of is p-type and layer 17 is fully depleted at thermal equilibrium and has a thickness and doping density such that it increases the effective Schottky barrier height of layer 15. Layers that are too thin are undesirable because of increased tunneling current.

In one embodiment, the substrate is an n+ (100) InP substrate. Layer 13 has a thickness of 0.5 μm and 2×10183-3
with a doping density of n10aO,4? rno
, 5sAs layers are grown to eliminate the possibility of forming interfering junctions at the interface with the substrate. This layer can be omitted if necessary. Layer 15 has a thickness of 3 μm and 1. lX10
n-type Ga04 with doping density of cm? I
n (1,53Aa.

Layer 17 is p'' Ga0,4?I no,sa As and approximately 8 nanometers (80 angstroms) thick;
It has a doping density of x1018cW1-3. The n-type dopant can be Sn or Si, and the p-type dopant can be B.
It may be e or Mg. Ohmic contact 19 is S to the substrate.
It is formed by electrolytically plating n Au and sintering at 450C for about 20 seconds.

Schottky contacts 21 are circular Au dots deposited on the surface.

The device shown as an example is an AI
IYlICho) and J.R. Arthur (J.
, J.T., Arthur)
in 5solid 5tate Physics)
It is conveniently produced by the well-known molecular beam epitaxy, as described in the article in 1975, p. 157. Layer thicknesses and doping densities are examples and may be modified. Layer 17 is about 7 to 100 nanometers (70
and 1000 angstroms). Other modifications are also possible. For example, M may be used instead of Au to form a Schottky contact.

To increase the barrier height as much as possible, device parameters are selected such that the p+ layer is fully depleted at thermal equilibrium. The energy band diagram of a pseudo-Schottky barrier diode with a thin and fully depleted layer is shown in FIG. Region 41 is an n-type layer, region 43 is a p+ type layer, and region 45 is a metal. Ec, Ef and Ev refer to the conduction band, Fermi level and valence band, respectively. The diagram is obtained by solving Poisson's equation.

An increase in the barrier height, denoted by Δφ'3, for a large number of electrons is evident. The p layer is partially depleted due to p+
It should be noted that one part is for the -〇 junction and one part is for the Au/p+ contact. A detailed analysis can also be made, which shows that the latter makes a larger contribution than the former. Therefore, the potential-energy peak is inside the p layer, but close to the p+, metallic junction. The inflection point in the alternating energy band diagram, denoted A, is exactly at the p+ junction.

Figure 3 shows p of approximately 8 nanometers (80 angstroms).
of the Schottky barrier diode of the present invention having a + layer,
Typical current-voltage characteristics are shown, with voltage plotted horizontally and current plotted vertically. The device has a diameter of 300 μm and the reverse leakage current is approximately 30 μA at 1 volt.
, 115 μA at 1.5 volts. This is l
85nA at 1 volt for x200μm gate
, corresponding to reverse leakage currents of 0 and 33 μA at 1.5 volts, respectively. This magnitude of leakage current is comparable to that of an oxide-enhanced Schottky diode. The reverse leakage current was found to increase exponentially with applied voltage, which was shown to be due to tunneling.

The effective barrier height of the Schottky barrier diode can be calculated from equation (1).

kT *.

φ', = -In (A T/Js) (1) Here, A* is Richardson's constant (Richardson's constant
nconstant) and Js is the reverse leakage current density. The effective mass of the electron is 0.041 m, A-4,92A
/cm”/K”, the effective barrier height is 0.
It is 47 volts. Theoretically, the increase in Schottky barrier height due to the p+ surface layer, Δφ'8, is approximately given by equation (2).

Here, εS is the dielectric constant of the Ga(1,47xno,53As layer), NA is the doping level of the p+ layer, and d is the p
+Layer thickness. It is shown that equation (2) holds only when equation (3) holds.

Here, ND is the doping level of the n-type layer, and Vb+ is the p
− This is the buried potential of the n junction.

The thickness and doping level of the structure shown here satisfies this condition. Therefore, the increase in Schottky barrier is 0.3
volts, and the total effective barrier height is 0.5 volts, which agrees well with the calculation from equation (1).

The forward 1-V characteristic shown in Figure 3 has an ideality factor of 1.3.
fits well with the standard current equation for a Schottky barrier diode. This fact that the ideality factor is not 1 indicates a strong voltage dependence of the effective barrier height. This is not surprising given that the applied voltage drops across the depletion region in the depleted p+ and n-type layers. The ideality factor of the Schottky barrier is not 1, which causes excessive shot noise in mixer diodes, but MIS
It is not very important for FET. Other devices include, for example, along with other Schottky barrier devices.
Includes an iMPATT diode. For example, assuming the cut-in voltage is the forward bias voltage required for the current to reach 10 μA, a Schottky barrier diode has a cut-in voltage of 0.005 volts.

The spacing between the Fermi level and the valence band maximum and the estimated free hole density in the p+ layer is approximately 1.6X10” cm
-3. This value is negligibly small compared to N″A and satisfies the depletion condition. That is, p is much smaller than NA.

Here p is the free hole density.

A device was fabricated with the same doping concentrations and layer thicknesses as in FIG. 1, except that layer 17 had a thickness of 70 nanometers (700 angstroms). Ga 0.47"0.53 As with the same area as the previously mentioned device
The p-n junction diode had a reverse leakage current of 1 mA at a cut-in voltage of 0.14 volts and a bias of 2 volts.

The capacitance-voltage characteristics of diodes are also a good friend.

Measurement of C-■ characteristics in I MH2 did not show hysteresis. A plot of C versus voltage (not shown) showed a uniform carrier concentration of 1.2 x 10 cm in the n-type layer and a barrier height of about 0.51 volt. These measurements agreed well with Hall measurements and IV measurements, respectively.

The device shown in FIG. 1 and its modifications are:
It may be used on its own or with further modification or in conjunction with other devices such as, for example, a field effect transistor, shown in cross section in FIG. This device generally incorporates the device shown in FIG. 1, but layer 13 is omitted and substrate 31 is semi-insulating. Electrode 21 is marked G, and ohmic contact 19 or substrate electrode is omitted. Layer 35 consists of an n-type layer n-53Ga, 47As, and layer 37 consists of p-type In, 1lsGa, 47As. The device further consists of source (first) and drain (second) electrodes, labeled S and D, respectively. Devices are conveniently fabricated by well-known molecular beam epitaxy. The electrodes are made by depositing a conventional G6 Au alloy on the p-type nGaAs surface and alloying at a temperature of about 440C for about 30 seconds. The alloy is p+
It penetrates the layer and stops in the n-type layer. According to measurements, sinter (S
After inteving) the source and drain electrodes became ohmic.

The p+ layer, as originally formed, is approximately 100 nanometers (1000 angstroms) or less thick, and is thick enough to prevent substantial tunneling current. Thicker layers are not preferred because the electrodes to layer 35 are difficult to make. Approximately 1 between the gate electrode and the source and drain electrodes
After forming the ohmic electrodes, layer 17 was etched to a thickness of less than 5 nanometers (150 angstroms).

The metal electrode serves as a mask for the etching process.

Etching may be performed using a normal etching technique. Since the portion of the layer 37 under the gate electrode is completely depleted, p
It is not necessary to completely remove the layer. If the thickness of the p+ layer is less than 150 angstroms as originally formed,
Etching may be omitted.

Although normally-off devices have been described, normally-off devices can also be fabricated by varying the thickness of layer 37 in well known manner. Additionally, although an n-channel FET is described, a p-channel FET may be fabricated by making layer 37 n-type and layer 35 p-type.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a diode according to the invention with increased Schottky barrier height; FIG. 2 is an energy band diagram at thermal equilibrium of a Schottky barrier diode according to the invention; FIG. 3 is a typical Schottky according to the invention. FIG. 4, a diagram showing the current-voltage characteristics of a barrier diode, is a schematic diagram of a field effect transistor according to the present invention. [Explanation of symbols of main parts] Substrate 11.31 First epitaxial layer 15.35 Second epitaxial layer 17.37 Ebitaxial InGa
As layer 13 Electrode to second epitaxial layer
21. G ohmic contact 19
2 additional electrodes D and S Applicant: Western Electric Company, Inc.

Claims (1)

[Claims] 1. A semiconductor device comprising a substrate, at least one epitaxial layer and at least one electrode, wherein the substrate is made of InP, and the at least one epitaxial layer is, in order, of a first conductivity type. a first epitaxial layer of single-portion GaAs having a conductivity type and a second epitaxial layer having a second conductivity type, the second epitaxial layer having a thickness in the range of 7 to 100 nanometers; at least one of the electrodes includes an electrode to the second epitaxial layer, and at least one of the epitaxial layers optionally has the first conductivity type and connects the InP substrate and the first epitaxial layer. A semiconductor device characterized in that it may include another epitaxial InGaAs layer disposed intermediate the semiconductor device. 2. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. 3. A semiconductor device as claimed in claim 1 or 2, characterized in that the second epitaxial layer has a thickness of less than 15 nanometers. 4. A semiconductor device according to claim 2 or 3, wherein the at least one electrode includes an ohmic contact to the substrate;
A semiconductor device characterized in that the second epitaxial layer is completely depleted in thermal equilibrium. 5. A semiconductor rubber as set forth in claim 11, item 2 or 3. In the chair, the at least one electrode includes an electrode to the second epitaxial layer and two additional electrodes to the first epitaxial layer, and the first electrode is connected to the additional electrode. A semiconductor device characterized by being in the middle. 6. The semiconductor device according to claim 5, characterized in that at least the portion of the second epitaxial layer between the electrodes until said addition has a thickness of less than 15 nanometers. .