JPS58122688A - Memory device - Google Patents

Abstract

PURPOSE:To prevent mis-matching of bit length for a memory device and input data, by selectively switching the memory device in a digital picture processing system as the memory device having different bit length in response to a control signal. CONSTITUTION:When the control signal C is ''0'', the memory block is operated as 8-bit/address accessed with an address signal in 16-bit of A0-A5. When the control signal is ''1'', a pair of memory elements out of memory elements designated for the address signals A0-A15, B0, B1 and the memory system of 2-bit/ address is constituted. Thus, the mis-matching of bit length of the memory device per one address and the input data is prevented to attain high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and a data processing system having an N-bit (N is a natural number) parallel data transfer path;
By selectively switching memory devices in a digital image processing system as memory devices with different bit lengths according to control signals, the bit length per address of the memory device and the bit length of input data can be changed. It is an object of the present invention to provide a memory device capable of storing input data while preventing mismatch.

In a digital image processing system, image data obtained by quantizing image information per pixel, usually in 1 to 8 bits, is stored in a memory, and the stored image data is read out from the memory. On the other hand, writing and reading are performed using the above symbol, write and read control signal rw, etc., but since current CPUs process in 8 bits (i.e., 1 byte) as a basic unit, the bits per memory address are The basic unit of length is 1 byte.

Therefore, when writing and reading 8-bit/screen image data to memory, the memory address and pixel address in the OPU correspond 1:1, which not only simplifies the processing, but also allows the cptr to The memory used for storing variables and the image memory can be shared, which is extremely convenient.

However, if the image data is 4 bits/pixel, 2 bits/pixel, or Fi1 bit/slip, there will be a mismatch with the bit length per address of the memory.

For example, 11igI with 2 bits/pixel! In a data processing system, if the memory structure is such that each byte stores and reads 4 pixels, the correspondence between memory addresses and pixel addresses will not be 1:1, but the advantage is that the normal memory connected to cptrK and the image memory can be shared. There is. However, 4 bits per address in the above memory of 8 pits/address.
Since pixels are written, it is not possible to rewrite only one specific pixel, and a processing method is required that reads all four pixels at once, changes only the bit data corresponding to the specific pixel, and then writes all four pixels together again. Therefore, the processing becomes complicated and the processing speed becomes slow.

Furthermore, in order to eliminate this drawback, if image data of 2 bits/pixel is stored at a ratio of 1 pixel to 1 address of memory, the memory becomes 2 bits/address, and this memory cannot be used as memory for programs or variables. Another drawback has arisen that will disappear.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the structure of a memory block of the device of the present invention, and FIG. 2 is a block diagram of one embodiment of the control circuit section of FIG. 1. In FIG. 1, 1 is a memory block consisting of eight 64-bit memory elements 2', 3,
4, 5, 6, 7.8, and 9, and has a configuration of 64x bytes. Here, this embodiment is applied to an image processing system in which one screen has 256 pixels arranged in the vertical direction and 256 pixels in the horizontal direction, and the image data is 2 bits/pixel. shall be provided. In addition, the memory block 1 is 16 indicated by MAO to M 15.
1M at the address specified by the bit address signal.
It is a normal type that can transfer S-bit parallel data indicated by DO to MDT via a bidirectional data bus, and reading or writing is controlled by the R/ signal from the CPU (not shown). . Furthermore, the chip select of a pair of memory elements 2 and 3 among memory elements 2 to 9 is performed by a signal c.
BO is supplied, and similarly memory elements 4, 5, 6 and T
, 8 and 9 each have a signal CB1. C.B.
2, (!83 are supplied respectively. These signals CB
O to cs3 allow the memory block 1 to operate as four sets of 2-bit memories. Address signal M above
The signals MU0 to MA15 and the signal cso-ass are generated by the circuit shown in FIG. 2, which is supplied with the output signal of the OM.

In FIG. 2, 10 is an input terminal for a control signal C that selects a 1-bit memory access mode;
1115 is an input terminal for each bit of a 16-bit address signal indicated by AU to AIS; 12o and 121 are input terminals for each bit of a 2-bit memory space selection signal indicated by BQ and Bl for selecting a memory space; 13 is the write and read control signal R of the memory block 1 shown in FIG.
/, are the input terminals incoming, and these input terminals 1G, I
to~111. , 12 o.

121.1 m, each input signal is a signal sent out from cpσ (not shown). Address signals AO to A15 are supplied to a driver 141C whose output is in three states, and the lower two bits of address signals AO to A15)
AD# The 14-bit signal excluding Al is not supplied to the driver 15 whose output is in 3 states. Also, the memory space selection signals of BO and Bl have 3 outputs,
The signal is supplied to the driver 16 which is in the state of operation. Furthermore, the lower two bits AQ and Al of the address signal are sent to the decoder 2.
0.

Drivers 14, 15, and 16 mentioned above and Driver 1 described below
8, decoder 20, driver 21, bus driver 19
, 22a to 22 (L is in the output state when the input control signal is 11', and is in the output blocking state when it is 'O'. Therefore, the control signal C from the input terminal 10 is 1
1'', the drivers 15, 16, decoder 20, and driver 21 are in the output state, and as will be described later, each of the 2-bit bus drivers 22a to 22 (l) is in the output state.On the other hand, Control No. 8a
When is 101, the control signal 0 is inverted in polarity by the inverter 17 and is supplied to the drivers 14, 18 and the bus driver 19.
'4.18 and the bus driver 19 are in the output state.

Therefore, first, the operation when the control signal C is IOI will be explained. At this time, as mentioned above, driver 1
4 is in the output state, so its input address signal M0~
The program 15 receives address signals MAO to M through the driver 14.
The memory block 1 shown in FIG. 1 is supplied as a program 15, and its address is specified.

On the other hand, the driver 18 also enters the output state, but its input signals are all 11', so the signals of all 4 bits 11N pass through the driver 18 to the signals CSO~08.
3 is applied to each chip select of memory elements 2 to 9 shown in FIG. 1, respectively, to put them in an active state. As a result, when control signal C is O, memory block 1 has 8 bits/address (that is, storage capacity 2
It is operated as a ``X8 bits'' memory.

This is the same memory used in normal computers, here 2 bits/pixel, 256
For example, 16 bytes of picture image data from 256 pixels are stored in the memory in the address space of -1 from 0 to 16 of memory block 1 (addresses 11 from 0 to 16 are used as picture image memory). ). In this case (normal mode), since the bidirectional bus driver 19 is in the output state, the data input/output terminal of each one pit of the memory elements 2 to 9 is transmitted to the cptr through the bus driver 19. Since it is connected to the data input/output terminal, the output data D7-DO of CPH is sent to the memory elements 2-9 as data MD7-M.
A total of 8 bits of data MD7 to MDO written as DO to the address specified by the address signal MAO-MA15 and read from the address specified by the address signal MAO-MA15 of the mesori elements 2 to 11 is CPU
The data is output as data DT to DO. Here, the above data DO and DI, D2 and D3, D4 and D5
, DI and Dr each indicate one piece of data of one pixel, so 4rMJ pixels are accessed at the same time with one address.

Next, the operation when the control signal C is 11'' will be explained. At this time, as mentioned above, the drivers 15 and 1
6 are in the output state, so of the 16-bit address signals MA15 to MAD supplied to the memory block 1, the upper 2 bits MA15 and MA14 become the CPU output signals BO and Bl, and the remaining VMs 13 to MAO is 0P
Upper 14 of output address signals A15 to AO at t7
Bits AI5 to M2. On the other hand, the above driver 15
At the same time as the output state of 16 and 16, the decoder 2
0 and driver 21 become active. The decoder 20 receives the lower two of the address signals AI5 to AO from the CPU.
A bit of AI, 80 is supplied, and AI, A
n roOJ, roIJ, rlOJ.

This is a decoder that outputs one of the four outputs as 11' corresponding to the four states of "11", and the four outputs are sent to the chips of memory elements 2 to 9 as signals C80 to 0EI3 through the driver 21. While being applied to the select signal, the signal is applied to the bidirectional pass drainos (22a to 22(l), respectively.

Therefore, when the control signal C is 11', AI,
Signal C8O~ specified according to the value of 2 bits of AO
Since one of the memory elements 083 becomes 11N and the others become "0", only one pair of the memory elements 2 to 9 is activated. Also, the bus driver 22
Only one of a to 22cL is in an output state, and the other three are all in an open state. The bus driver 22a is connected to the 1-bit data input/output terminals of each of the memory elements 2 and 3, and the bus driver 22b is connected to the 1-bit data input/output terminal of each of the memory elements 4.5. Furthermore, the bus driver 22c is connected to each 1-bit data input/output terminal of the memory element 6°T, and the bus driver 226K is connected to the memory element 8,
Each 1-bit data input/output terminal of I is connected.

That is, a pair of memory elements 2, 3, 4, 5, 6, 1, 8, and 9 to which chip select signals of the same value are supplied are as follows.
The data input/output terminals are bus drivers 22a, 22
b, 22c, 22 (connected to 1, respectively,
Among the bus drivers 22a to 22a, only one bus driver connected to the data input/output terminal of the pair of memory elements set to the active state is set to the output state. Furthermore, the bus driver 22a
The other data input/output terminal of ~22a is connected to cP.
The data Do and DI input/output terminals of Tlr are connected.

Therefore, when control signal C is lII, signal A
O～mu15. A pair of memory elements 2 to 2 whose addresses are designated by BO and B1 operate, forming a 2-bit/address memory system in which 2-bit data Do and DI of the cPU are transmitted and received. . That is, memory block 1 uses 14 bits A2 to AIS of address signals AO to A15 from CM as an address, and 2 bits are used to select memory elements to be accessed in parallel, thereby reducing the storage capacity to 2. It will be operated as a ×2 bit memory.

tBO, set the value of B1 to “OO” and set memory block 1
When accessing , 2-bit/pixel image data 110 from cpa, DI is address signal AO~mu1
5, memory elements 2, 3, memory elements 4, 5, memory element 6. T1 memory elements 8, 9, memory elements 2.3.・
... are sequentially stored in a pair of memory elements.

On the other hand, the image data MD7, ! read out from the pair of memory elements in the same order as above. : MDI.

Mn2 and Mn2, Mn2 and Mn2, MDI and M
DO is read out to the CPU as data Do, DI. In this way, the 16-bit address of the AO-AIS directly becomes the address of 256 x 256 pixels, and image data can be accessed using the 2 bits Do and DI.

Also, if the values of Be and B1 are set to other than "00", the addresses 111K to 32 in the noffle mode will be set to 32K.
It is possible to access the memory corresponding to the address space of addresses 48 to 48 and addresses 411 to 64. In addition, signal B
O and B1 may be signals from a switch or the like, a signal from an output port, or an address signal other than AD to M1S.

In this way, BO, B1 and AO-A15 operate as addresses. Compared to the 8-bit/address memory when the control signal O is IO", this is a memory in which the address is expanded four times and the data is reduced to seven.

In this manner, the control signal C allows the memory block 1 to be used in two ways: standard memory with 8 bits/address or memory for image processing with 2 bits/address.

Next, if both the signals BO and Bl are fixed at 1101, then from K, ii! ii My memory is O~11ix-1
An example of a memory system that uses an address space of addresses will be described. If control signal 0 is set to IO, 11iK ~ 84 11 address 48 /<ite's at L// (It is clear that the memory of the space can operate as a normal memory for variables, programs, etc. Since this control signal C is an output signal of the 3PU, it does not matter whether it is a signal from the output port or a part of the address signal. Assume that bit A16 is assigned (assuming that the CPU can handle a total of 128 addresses in the address space).In this way, the address O~ by OFυ is assigned.
Addresses 64 to 11 are normal memory address spaces that can be accessed with 8 bits per address, and addresses 64 to 1211x-1 are irregular image memory addresses that can be accessed with 2 bits per address by the CPU. It is a space, and furthermore, the address 11 in 0 to 16 by CPH is 64 ~
12! This becomes an address space in which the image memory at address ll-1 can be accessed by 4 pixels per address. Such a system enables the following applications.

The memory space of memory block 1 at addresses 16 to 64 to 11 by CPH is used as a program and data area, and the memory space of memory block 1 at addresses 64 to 128 to -1 by CPH has one pixel per address. Since the image data is accessed, the ms data of any pixel can be freely rewritten. Pixel atto vxo ~l
Address @x-1 is 84 to 1211 by CPH.
It corresponds to the street address. i.e. (0,0) at X, 7 coordinates
The address of the pixel at the position is 64, m, (255,
The address of the pixel at position 255) is 12! IK-1
Corresponds to the street address.

Furthermore, if the start address of the image data of the pixel you want to access is a multiple of 4, and you want to access the image data of the number of pixels that is an integral multiple of 40, use O to 11.
By accessing addresses 1 to 11, image data of 4 pixels can always be accessed in one access. Thereby, the data transfer time can also be reduced to -i-.

Note that the above embodiment has been explained assuming that the image data of one pixel is 2 bits, but when the image data is 1 bit/pixel, the signals BO and B1 are expanded to BO-B2, and the circuit is changed accordingly. In addition, in the case of 4 bits/pixel, only two signals are required for the signal CBO-083, so the signals Be, B1
Only Be is required, and in this case, the circuit configuration is simpler than in the embodiment. Also, signal BO.

BIH memory block 1 address signal MAO~MA
Although this is used as a signal of the upper two bits of 15, the lower two bits may also be used.

As described above, in the memory device according to the present invention, a memory block is constituted by a plurality of memory elements whose access operations are controlled by a 1-bit control signal, and the value of the control signal is 'O' (or I). When I I'), addressing is performed by all bits of address information of M bits (M is a natural number), and it operates as a first memory with a storage capacity of 2M-I bits (L is a natural number, L≦N). However, when the value of the control signal is 11'' (or IO2), the address is specified by (M-K) bits of the M-bit address information (X is a natural number, K≦M, L≧2). At the same time, bits to be accessed in parallel among the plurality of memory elements are selected and operated by the K-bit signal, and the stored contents of the second memory are transferred to the first memory.
Since the bit signal is used to determine which address space among the 2M addresses corresponds to when accessing the memory, data with the number of bits equal to the number of bits per address, for example, 8 bits/pixel. It retains the advantage of a memory that writes or reads image data in that only the image data of a desired pixel can be accessed, and also uses part of one memory block as standard memory (random access memory) for other than image data. In addition, it can be used as an image memory for image data with a bit number different from the number of bits in one address, and can be shared with the CPH standard of 1 byte/address.
When high-speed transfer of private data is required, it can be executed in the 4-pixel/address mode, so it has features such as simple processing, high-speed processing, and markedly improved memory sharability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the main part of the apparatus of the present invention, and FIG. 2 is a four-wheel system diagram showing another embodiment of the main part of the apparatus of the present invention. DESCRIPTION OF SYMBOLS 1...Memory block, 2-9...Bit memory element in 64, 10...Control signal input terminal, 11
゜~1115... Address signal input terminal, 14, 15
, 16゜111.21-・Driver, 19 , 22a
~22a +++ bus driver, 20... decoder.

Claims (1)

[Claims] In a memory device connected to an N-bit (N is a natural number) parallel data transfer path, a memory block is composed of a plurality of memory elements whose access operations are controlled by a 1-bit control signal, The value of the control signal is O
When I (or 11N), K is M bits) (M is a natural number), and all bits of the address information are given a special address.The storage capacity is 2', L bits) (L is a natural number, and L≦N). )
When the value of the control signal is 11' (or 16N), (M-K) bits of the M-bit address information (K is a natural number, K≦
M, L≧2K), and the bits to be accessed in parallel from among the multiple memory elements are selected by the X-bit signal to increase the memory capacity to 12M.
- (Top) A memory device characterized in that a 2M address is determined by a bit signal by accessing the first memory to the second memory 2 of the bit.