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JPS58145259A - Multivalued signal generator - Google Patents

Multivalued signal generator

Info

Publication number
JPS58145259A
JPS58145259A JP57029413A JP2941382A JPS58145259A JP S58145259 A JPS58145259 A JP S58145259A JP 57029413 A JP57029413 A JP 57029413A JP 2941382 A JP2941382 A JP 2941382A JP S58145259 A JPS58145259 A JP S58145259A
Authority
JP
Japan
Prior art keywords
signal
resistor
output
level
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57029413A
Other languages
Japanese (ja)
Inventor
Keiji Murakami
村上 圭司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57029413A priority Critical patent/JPS58145259A/en
Publication of JPS58145259A publication Critical patent/JPS58145259A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To generate easily a wave-shaped multivalued signal with good accuracy, by locating various different resistors for an output of a binary transversal filter and selecting one of them according to a level control signal. CONSTITUTION:The selection of the level of quadrivalue signal is determined with a level control signal inputted to a terminal 10. A single pulse is inputted to binary transversal filters BTF30, 31 from a resistor selector 20 in synchronizing with a clock inputted to a terminal 11. The BTEs 30, 31 make response with opposite polarity. Thus, the waveform of inverted polarity is inputted to a resistor group 40. The rsistor group 40 is provided with resistors of resistance values R and 2R, and the selection of the resistors depends on a signal outputted from a resistor selector 20 via a delay line. The output signal level of the resistor group 40 depends which of the resistance values R, 2R is to be connected, and the relation between the resistance value and the output signal level are in the inverse proportion.

Description

【発明の詳細な説明】 この発明は、ディジタμ通信に用いられ、波形整形され
た多端信号を発生する多lll11g号光生器に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical generator for use in digital .mu. communications, which generates waveform-shaped multi-end signals.

従来1この種の信号発生器として第1図に示すものかあ
った。図1C?いて、は)は2+di1m号入力端子、
(2)はクロック入力端子、13)はクロック入力端子
(2目ζ入力したクロックのdm数をM4f!t (M
 : @数)して出力するてい倍3、(4)は2(d+
、i号入力端子(1)に入力した信号をてい倍器(3)
カらのクロックで一段ずつシフトするシフトレジスタ、
(5)はこのシフトレジスタ、4)の各段の出力のうち
の一方D)らのPi#段伏信号に11列に接続された抵
抗器群、+61はこの抵抗器群t512))ら出力され
た階段状15号をIJuJr−する加算器、(7)はこ
のhOx器(6)の出力D)ら高614彼を除去してJ
!!続信号とする高調彼除去低域逍過フィルタ(L P
 F ) 、+MIは信号出力端子である。
One conventional signal generator of this type was the one shown in FIG. Figure 1C? and ) is the 2+di1m input terminal,
(2) is a clock input terminal, 13) is a clock input terminal (2nd ζ is the number of dm of the input clock, M4f!t (M
: @Number) and output it multiplied by 3, (4) is 2(d+
, the signal input to the i input terminal (1) is multiplied by the multiplier (3)
A shift register that shifts one step at a time using a clock from
(5) is this shift register, one of the outputs of each stage of 4) is a group of resistors connected in 11 columns to the Pi# stage signal D), +61 is the output from this resistor group t512)) The adder that converts the stepped No. 15 into IJuJr-, (7) is the output D) of this hOx unit (6) by removing the high
! ! A harmonic filter eliminating low-pass filter (L P
F ) and +MI are signal output terminals.

次に動作番こついて説明する。入力端子山番こ入力した
21直(バイナリ−)信号は、クロッつてい倍器(31
の出力クロツク蔭こよってデータレートのM后のAPi
でシフトレジスタ+41の中を一段ずつシフトされる。
Next, the operation sequence will be explained. The 21 direct (binary) signal input to the input terminal is sent to the clock multiplier (31
Due to the output clock, the data rate of M after API
The data is shifted one stage at a time in the shift register +41.

ただし図では、シフトレジスタ、4)の中をシフトする
15号線は省いである。シフトレジスタ(4)の出力は
、次段のレジスタへの入力信号になると同時に、Q、Q
なる2つの出力を何して抵抗器群15+への入力信号と
なる。抵抗器群15)は、シフトレジスタ(4)の段数
に等しい数の抵抗から成り、各段のシフトレジスタ+4
1の出力見、Qのうちの一方に接続される。シフトレジ
スタ(4)から出力された階段状信号は、抵抗器群16
1で#続される抵抗値に逆比例した振幅(これをタップ
係数と呼ぶ)をもつ階段状信号となって加算器16目こ
入力する。加算器(6)によってシフトレジスタ+4)
の段数に等しい1a号が加算された後、高調波除去L 
’i’ F 171によってなめらかな連続信号となり
、出力端子(8)から出力される−この時の時間波形と
周波数スペクトルとの関係を第2図に示す、た疋し、図
ではMW12としであるが、M(Z)値は2以上ならば
いくらでもよい0図にνいて、1a)は最終的に発生さ
せようとする信号波形であり、4波数スペクトルは帯域
〜」限されている。1b)はクロックのてい倍器(31
の出力クロック(T/2周期、T : 1シンボル信号
の長さ)で、シフトレジスタ(4)を駆動した時にQ又
はQから出力される信号かインパルスである場合の時間
域波形と周波数スペクトルである。(C)はシフトレジ
スタ(4)の出力がインパルスである時に、抵抗器群(
5)の各抵抗値を所望信号波形の振幅値となるように選
択した場合を図示して2す、(d)はシフトレジスタ(
4)の出力か4賽的な階段状波形である場合の時間域波
形と周波数スペクトルである。加算器(6)の出力階段
波形が(d1図に示すものであれば、l16a波除去L
 P F i71によって高調波が除去5nて、1m)
図に示す所望波形が得られることになる。
However, in the figure, line 15, which shifts in the shift register 4), is omitted. The output of the shift register (4) becomes an input signal to the next stage register, and at the same time
The two outputs become input signals to the resistor group 15+. The resistor group 15) consists of a number of resistors equal to the number of stages of the shift register (4), and the number of resistors in each stage is +4.
The output of Q1 is connected to one of Q. The step-like signal output from the shift register (4) is transmitted to the resistor group 16.
A stepped signal having an amplitude inversely proportional to the resistance value (this is called a tap coefficient) is input to the adder 16. shift register +4) by adder (6)
After No. 1a equal to the number of stages is added, harmonic removal L
'i' F 171 produces a smooth continuous signal, which is output from the output terminal (8).The relationship between the time waveform and frequency spectrum at this time is shown in Figure 2. However, the M(Z) value may be any value as long as it is 2 or more, and 1a) is the signal waveform to be finally generated, and the 4-wavenumber spectrum is limited to a band ~. 1b) is the clock multiplier (31
Time domain waveform and frequency spectrum when the signal output from Q or Q is an impulse when the shift register (4) is driven with the output clock (T/2 period, T: length of 1 symbol signal) be. (C) shows the resistor group (
Figure 2(d) shows the case where each resistance value in 5) is selected to correspond to the amplitude value of the desired signal waveform.
These are the time domain waveform and frequency spectrum when the output of step 4) is a four-way stepwise waveform. If the output staircase waveform of the adder (6) is as shown in the d1 diagram, then the l16a wave removal L
Harmonics removed by P F i71 (5n, 1m)
The desired waveform shown in the figure is obtained.

第1図に示した信号発生器は、バイナリ−トランスパー
サルフィルター(MTF)と呼ばれる。
The signal generator shown in FIG. 1 is called a binary-transpersal filter (MTF).

従来の波形整形された信号を発生するljI号発生器は
以上のようIC構成されていたので、このままの構成で
は常に同一レベルの波形しか発生できず、多値信号を発
生できないという欠点かあった。
The conventional LJI generator that generates waveform-shaped signals had the above IC configuration, so with this configuration, it could only always generate waveforms of the same level and had the disadvantage of not being able to generate multilevel signals. .

この発明は上記のような従来のものの久侭を除去するた
めになされたもので、従来のバイナリ−トランスパーサ
ルフィルタの出力に値のIIなる各檎抵抗器を置き、レ
ベA/制御信号に従ってその抵抗器の1つを選択するこ
とにより、多III信号の発生が可能な多+1信号発生
器を提供することを目的としている。
This invention was made in order to eliminate the long-standing problems of the conventional filter as described above, and by placing each resistor with a value of II at the output of the conventional binary transversal filter, The object is to provide a multiple +1 signal generator capable of generating multiple III signals by selecting one of its resistors.

以下、この発明の一夾施例を図について説明する。第3
図は4値1g号発生−のブロック図であり1図に2いて
、IlGは4値信号のうちの一つを指定するためのレベ
ル制御信号入力端子、(■1はクロック入力端子、ωは
4値信号のうちの一つを指定するレベル制御信号とクロ
ックとを入力信号として、二つのバイナリ−信号をバイ
ナリ−トランスパーサルフィルタm 、 @0−ζ送る
と同時に、檀々の抵抗値を内蔵した抵抗器群−にどの抵
抗器を選択するかの情報を送り出す抵抗選択器、m、t
sDは波形整形を行うバイナリ−トランスパーサ/L/
フィルタ(BTF)であり、そのタップ係数をそれぞれ
(an%、I an’)とすると@ B ’wm−a 
n (na=i a・・”a LaL:Vフトレシスタ
段数)である・−は値のSなる檀々の抵抗とスイッチか
ら成る抵抗器群、補はB T F 翰、 @υに2ける
信号の遅延時間を補正して抵抗器群−に2ける抵抗器の
切換えが正しく行われるようにするための遅延a、−は
上記抵抗m群−の出力を加算して出力する加算器、−は
多値信号出力端子である。
Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. Third
The figure is a block diagram of the 4-value 1g signal generation. 1 and 2 are the level control signal input terminals for specifying one of the 4-value signals, (■1 is the clock input terminal, and ω is the Using a level control signal specifying one of the four-valued signals and a clock as input signals, two binary signals are sent to the binary transversal filter m, @0-ζ, and at the same time, the resistance values of each Resistance selector m, t that sends information on which resistor to select to the built-in resistor group
sD is a binary transparser/L/ that performs waveform shaping.
filter (BTF), and if its tap coefficients are (an%, I an'), @ B 'wm-a
n (na=i a..."a LaL: number of V resistor stages) - is a resistor group consisting of various resistors and switches with value S, complement is B T F wire, @υ is the signal in 2 Delay a is used to correct the delay time of resistor group - so that the switching of the two resistors in resistor group - is performed correctly. This is a multi-level signal output terminal.

以下1この装置の動作について説明する。4値信号の出
力レベルを3A、^、−^、−3A(A:定数)とする
と、そのレベルの選択は端子u1ζ入力するレベル制御
信号により決定される。端子(鳳1)に入力したクロッ
クに同期して抵抗選択器−からパルスgT(T:IFン
ポル長)の長さの単一パルスが、出力信号*1.bを通
って波形幡形用ノBTFJl、Cll1C入力する。I
ITF(Dり’7プ係数はBPF@lと@Oとでは、m
a’m−In  (D関係かあるから、たとえばBTF
cIlの単一/(ρス応答が上向きの応答ならば、BT
FlIIlの単一/くルス応答は全く同形で、極性の正
反対な下向きの応答を行う。
The operation of this device will be explained below. Assuming that the output level of the four-level signal is 3A, ^, -^, -3A (A: constant), the selection of the level is determined by the level control signal inputted to the terminal u1ζ. In synchronization with the clock input to the terminal (Front 1), a single pulse with a length of pulse gT (T: IF port length) is output from the resistor selector as an output signal *1. BTFJl and Cll1C for the waveform are input through b. I
ITF (D rip coefficient is m for BPF@l and @O.
a'm-In (D-related, for example BTF
cIl's single/(ρ) If the response is an upward response, then BT
The single/cursive response of FlIII is completely isomorphic, with a downward response of opposite polarity.

このようにして、櫓性反対の波形が抵抗器m−に入力す
る・抵抗器群−には2つの抵抗値k及び2λをもつ抵抗
器かあり、抵抗−の選択は抵抗選択IiI■から出力さ
れて遅延41−を経由した信号に従う、抵抗器群−の出
力信号レベルは2つの抵抗値it、2iのどちらが接続
されるD)により決まりへ抵抗値と出力信号レベルとは
逆比例の関係番こある。
In this way, the opposite waveform is input to the resistor m-.The resistor group- has two resistors with resistance values k and 2λ, and the selection of the resistor is output from the resistor selection IiI■. The output signal level of the resistor group according to the signal passed through the delay 41- is determined by which of the two resistors it and 2i is connected.The resistance value and the output signal level are inversely proportional. There it is.

すなわち、出力信号レベVが2への場合番こは、Bに抵
抗1m 21Lの抵抗器を接続する。又、出力信号レベ
ルか−Aの場合にはB TF 俤υの出力に抵抗111
2M−の抵抗器を接続し、出力1J号レベルが一2Aの
場合には8TFlυの出力−こ抵抗値にの抵抗器を接続
する。抵抗器群−の出力は加算器−で加算されて出力端
子−から出力される。単一パルスに対する443図の各
部の信号こ〜fの波形を第4図1m)〜(flに示す、
第4図1elで、抵抗器群顛内で接続される抵抗器の値
が艮の時は振Ipaii2^の波形、21Lの時は振幅
への波形であり、(f)では抵抗器の値が2にの時に振
幅−への波形、λの時は振幅−2への波形か得られるこ
とを示している。第5図に一例として4値信号波形を実
線で示す、同時6ζBTFで波形優形を行わない場合を
破線で示す・なり、上記実施例では4値信号発生器につ
いて説明したが、4値以外の場合でも実現可能なことは
明らD)である、又、出力信号レベルがDCを中心とし
て正負対称である場合を例にとって説明したが、これは
他の任意の信号Vべ〜を有するものであってもよく、こ
の信号レベルの調整はレベルVフト回路によって可能で
ある。
That is, when the output signal level V is 2, a resistor with a resistance of 1 m and 21 L is connected to B. Also, if the output signal level is -A, a resistor 111 is connected to the output of BTF 迤υ.
A resistor of 2M is connected, and if the output 1J level is 12A, a resistor of 8TFlυ is connected to the output. The outputs of the resistor group are added together by the adder and output from the output terminal. The waveforms of the signals ko to f in each part of Fig. 443 for a single pulse are shown in Fig. 4 1m) to (fl,
In Fig. 4 1el, when the value of the resistor connected in the resistor group is 艮, the waveform is Ipaii2^, and when it is 21L, it is the waveform to amplitude, and in (f), the value of the resistor is 2, a waveform with an amplitude of -2 is obtained, and when λ, a waveform with an amplitude of -2 is obtained. As an example, in FIG. 5, the solid line shows the 4-value signal waveform, and the broken line shows the case where the waveform is not dominantly shaped by simultaneous 6ζBTF. It is clear that D) can be realized even in the case of Adjustment of this signal level is possible by a level V shift circuit.

また以上は多11信号発生器そのものについて説明した
が、この多+m <i号発生器は各種の用途に応用でき
、たとえば、多値変調方式にνける波形優形を兼ねた変
調器のドライバー回路として使用できる。多値変調方式
の例としては、多相位相変調7・方式、あるいは多値直
交振幅fil方式等か考えられる。
Although the multi-11 signal generator itself has been described, this multi-+m < Can be used as Examples of multilevel modulation methods include a multiphase phase modulation method, a multilevel quadrature amplitude fil method, and the like.

Wi6図−)及びlblに8相位相変調方式及び16値
直交振幅変一方式の信号空間配m図を示す、これらは直
交する両チャネルともに4値(iI号レベルが用意され
、それらか線形合成されている例である・又、8相位相
変一方式に2ける変調部のブロック図を87図に示す0
図にνいて、(101)〜(103)はデータ入力端子
、(111) )−(112)は抵抗選択器、BTF、
抵抗器群より成る上記多値信号発生器、(121)、 
(122)は変調器、(131)は局部発振器、(14
1)はこの局部発振器(131)の二つの出力のうちの
一方の位相をff/2だけ回転して、ff1l![12
2)へ入力する搬送波の位相を変調器(121)へ入力
する搬送波の位相と直交させるための移相器%  (1
51訂変@ 13(121) r(122)で変調され
た変調波形を線形合成する合1112器、(161)は
8相位相変調波出力端子である・次にこの変調部の動作
について説明する・データ入力端子(101)〜(10
3)に入力した3系列の符号列は、多値信号発生器(1
11) 3(112)へ入力して多イー信号発生器の出
力信号レベルを定める抵抗選択器及び抵抗器群への制御
信号となる。多値信号発生器(111) 、 (112
)に内蔵されているBTFのタップ係数により波形優形
された信号は、4値出力レベルms 、 at 、 −
at、−amのうちのいずれかとなった後に、変m 1
Il(121) −r (122)の一つの入力ポート
に入力する・一方、局部発振器(131)から出力され
た搬送波は二分岐された後に一部は直接f調器(121
)へ入力し、一部は移相器(141)によりπ/2だけ
位相を変えられてfM器(122)へ入力する。すなわ
ち、fdl器(121)と(122)に入力する搬送波
の位相は直交してνす、これらの変HA @ (121
)(122)の出力を合成n (151)で線形合成す
ることによって、出力端子(161)には′s6図1m
)の信号空間配置図のうちのいずれかに位相変調された
変調波形が得られることになる・ な2以上は多値信号発生器を8相位相変調方式のt’g
aのドライバー回路に応用した場合1こついて説明した
が、これは他の多相位相変調方式や多値1直交振幅変調
方式にも応用できる。
Figure Wi6) and lbl show the signal space distribution diagrams of the 8-phase phase modulation method and the 16-value orthogonal amplitude conversion method. This is an example of the 8-phase phase shift system.
In the figure, (101) to (103) are data input terminals, (111) to (112) are resistance selectors, BTF,
The multi-value signal generator (121) is composed of a group of resistors;
(122) is the modulator, (131) is the local oscillator, (14
1) rotates the phase of one of the two outputs of this local oscillator (131) by ff/2, ff1l! [12
2) to make the phase of the carrier wave input to the modulator (121) orthogonal to the phase of the carrier wave input to the modulator (121).
51st revision @ 13 (121) A combiner 1112 that linearly synthesizes the modulated waveform modulated by r (122), (161) is the 8-phase phase modulated wave output terminal.Next, the operation of this modulation section will be explained.・Data input terminals (101) to (10
The three code strings input to 3) are sent to a multilevel signal generator (1
11) It is input to 3 (112) and serves as a control signal to the resistor selector and resistor group that determines the output signal level of the multi-E signal generator. Multilevel signal generator (111), (112
) The signal whose waveform has been shaped by the tap coefficients of the built-in BTF has four-level output levels ms, at, -
After becoming either at or -am, the change m 1
Input to one input port of Il (121) -r (122). On the other hand, the carrier wave output from the local oscillator (131) is split into two, and then a part is directly input to the f modulator (121).
), and a part of the signal is shifted in phase by π/2 by a phase shifter (141) and then input to an fM unit (122). In other words, the phases of the carrier waves input to the fdl units (121) and (122) are orthogonal ν, and these variations HA @ (121
) (122) by linearly combining the outputs of n (151), the output terminal (161) is
) A modulated waveform that is phase-modulated in one of the signal space layout diagrams will be obtained.For 2 or more, the multilevel signal generator is
Although one problem has been described when applied to the driver circuit of A, this can also be applied to other multi-phase phase modulation systems and multi-level single quadrature amplitude modulation systems.

以上のように、この発明によれば、多1−1d号発生器
を、バイナリ−トランスバーサルフィルタとそれに縦続
接続される値の異なる種々のは仇姦を用意して、所望4
N号レベル曇こ応じて上記抵抗器のうちの一つを選択す
るというように411!成したので、波形優形された多
値信号を谷易番こ積度艮〈拍生できるという効果がある
As described above, according to the present invention, a multiple 1-1d signal generator is provided with a binary transversal filter and various values cascade-connected thereto, so that a desired number of signals can be obtained.
Select one of the above resistors depending on the N level, and so on 411! As a result, it is possible to generate a waveform-shaped multi-level signal in an easy-to-understand manner.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の波形優形した信号を発生する信号発生器
のブロック図、第2図は上記[号妬生器で信号を発生す
る場合の動作yA理図、第3図はこの発明の−*!施例
による多値4t1wj@生器を示すブロック図、第4図
はff3図の各部の信号波形図、第5図は第3図の多1
−信号発生器の多端15号出力波形の一例を示す図、1
1g6図(al 、 iblはこの発明の詳細な説明す
るための8相位相変調方式νよび16値直交振幅変調方
式のイ5号空聞配置鑑図、第7図はこの発明の応用例と
しての8相位相変調方式に?vyる変#1部のブロック
図である。 ■・・・抵抗選択器、−、+30・・・バイナリートラ
ンスパーサルフイVり、鴎・・・抵抗器群、顛・・・遅
延線、リシ〔琴・・・ )nコ 算器 。 代  連  人       萬   野   信  
 −第4図 ヒ−T−1 第5図 第6図 (b) ch
Figure 1 is a block diagram of a conventional signal generator that generates a signal with an excellent waveform, Figure 2 is a diagram of the operation when generating a signal with the above-mentioned signal generator, and Figure 3 is a diagram of the present invention. -*! A block diagram showing the multilevel 4t1wj@generator according to the embodiment, FIG. 4 is a signal waveform diagram of each part of the ff3 diagram, and FIG.
- Diagram showing an example of the multi-end No. 15 output waveform of the signal generator, 1
Figure 1g6 (al, ibl is a diagram of the A5 space arrangement of the 8-phase phase modulation system ν and the 16-value quadrature amplitude modulation system for detailed explanation of this invention, and Figure 7 is an example of the application of this invention. It is a block diagram of the first part of the 8-phase phase modulation system. ...Delay line, Rishi [Koto...] nko calculator. Representative Makoto Yomano
-Figure 4 H-T-1 Figure 5Figure 6 (b) ch

Claims (1)

【特許請求の範囲】[Claims] 山 211!入力信号を波形整形して出力するトランス
バーサル形信号発生器と、それぞれ所望出力振幅に逆比
例した値を埒つ俟数の抵抗器D)らなり上記悟号光生器
の出力を所望出力振幅に夏期して多値1N号を出力する
抵抗器群と、レベル制(財)信号曇こ従って上記抵抗a
群の中D)ら上記1g号光生器の出力にf#続tべき抵
抗器を選択する抵抗倍沢器とを謔えたことを特徴とする
多l111ぎ号弁生器。
Mountain 211! A transversal signal generator that shapes the waveform of an input signal and outputs it, and a resistor D) each having a value inversely proportional to the desired output amplitude. The resistor group that outputs multi-value 1N in summer and the level system (incorporated) signal cloud, so the above resistor a
Among the group D), a multi-sized valve generator is characterized in that it is equipped with a resistance multiplier for selecting a resistor of f# for the output of the above-mentioned 1-g optical generator.
JP57029413A 1982-02-23 1982-02-23 Multivalued signal generator Pending JPS58145259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57029413A JPS58145259A (en) 1982-02-23 1982-02-23 Multivalued signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57029413A JPS58145259A (en) 1982-02-23 1982-02-23 Multivalued signal generator

Publications (1)

Publication Number Publication Date
JPS58145259A true JPS58145259A (en) 1983-08-30

Family

ID=12275439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57029413A Pending JPS58145259A (en) 1982-02-23 1982-02-23 Multivalued signal generator

Country Status (1)

Country Link
JP (1) JPS58145259A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326229A (en) * 1991-01-18 1992-11-16 Motorola Inc Multiple amplitude sample generator and method thereof
US6407627B1 (en) 2001-02-07 2002-06-18 National Semiconductor Corporation Tunable sallen-key filter circuit assembly and method
US7221711B2 (en) 2002-03-27 2007-05-22 Woodworth John R Multilevel data encoding and modulation technique

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326229A (en) * 1991-01-18 1992-11-16 Motorola Inc Multiple amplitude sample generator and method thereof
US6407627B1 (en) 2001-02-07 2002-06-18 National Semiconductor Corporation Tunable sallen-key filter circuit assembly and method
US7221711B2 (en) 2002-03-27 2007-05-22 Woodworth John R Multilevel data encoding and modulation technique

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