JPS58165347A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To melt down a metal layer by low power laser lights by a method wherein a metallic layer is formed making a part of its surface black colored with high light absorption factor so that a wiring of integrated circuit may be cut down as necessary. CONSTITUTION:The impurity regions 52, 53 as wiring with high concentration are separately formed on the internal surface of a semiconductor substrate 51. Firstly, for example, Mo layer 56 is evaporated to make a part of the surface of Al layer 55 black colored. Secondly the surface of the layer 56 is etched to make the processed metallic surface black colored remarkably deteriorating the reflecting power of any incoming laser lights. Thirdly a wiring with region to be cut down and a passivation film is formed. Then laser lights 57 are irradiated to melt down the laminated structure of layers 56 and 55.

Description

[Detailed description of the invention] [Technical field of the invention] Book! 1@ relates to a method of manufacturing a semiconductor device, and relates to a manufacturing method suitable for application to means for partially disconnecting the wiring of an integrated circuit.

[Development@O technical background and its problems]

Super LB! ,9 Especially as semiconductor memories become more sophisticated and larger in size, the storage capacity of seven Omega memory also increases to 641 bits or 25 bits.
6 bits and Nashi, inevitably the Houmasho will be exposed m% to%
lk',) is also a defective element, which makes the yield rate even more foolish. Redundancy is a means to remedy such partial defects.
Means for improving the yield p by incorporating circuits are known.Such redundant circuits are constructed as shown in FIGS. 11 to 3, for example. That is, No. 1N shows a circuit configuration diagram of a semiconductor memory with redundant bits, in which a memory cell group 1 is provided in which a large number of memory cells are connected to each intersection of word lines and pit lines running vertically and horizontally, and this memory cell group IK The decoder 2 for word line selection is connected, and the decoder 2 for pit line selection is connected. The configuration is such that a desired memory cell is selected by supplying an address signal to each cell. In this circuit configuration, redundant circuits 4.5 are connected to locations with a relatively high probability of defectiveness, such as memory cell #J and decoder 2.3, and countermeasures are taken for elements with defective locations through a disconnection process. It is. ,. That is, the word line selection decoder 2 receives address signals M, M, M, and M.

A3 to An are supplied, and any one of a large number of word lines is selected by a combination of address signals.

Similarly, an address signal is supplied to the bit selection decoder 1 to select a desired memory cell. In this case, for example, if there is a defect in a certain word line, the word line is not used and the redundant cell I is used instead, so that the device can achieve the desired characteristics. Being able to get an image of the real body parts makes you feel better.

This concrete step is shown in Figure 2. That is, the memory cell 11 selected for the pit line 11 and the word line 11
is composed of a transistor 24 and a capacitor 25. The cage cell 21 having such a configuration is connected to each line ax, a.
It is placed at the intersection of x. The word line driving transistor # is connected to the food line JJK, and this transistor NX1
1gC)? '-) to control transistor -1~
SOWS connection 1 is established. Transistors ze and so are one:'
Manually select the desired hood line 22, and the r-) control 1171 of the selected nine word lines is set to a low level. Then, the reset signal is transmitted to the transistors 2B and 81.
-), the transistor 28 becomes conductive, the r-to control line S2 is charged to a high level, and then the address signal Atemt... is input, and when selected, the transistor 29.3"0 becomes conductive. In the non-conducting letter, r-) control line 3
2 maintains a high level. Conversely, when 1 is not selected, the transistor j 9 e J 0 becomes conductive, and the r-) control @SX of the non-selected word line becomes low level. Due to this potential, transistor J6 becomes conductive, and word @22 becomes high level. In such an integrated circuit, if there is an error in the word line 22, an error will occur if it is selected, so selection must be prohibited. In this case, the f-) control line 32 is brought to a low level. As an example of making this low level, if a cut section 33 is formed, cutting this cut section SX from K will eliminate the problem. This disconnect prevents the r-1- control line 32 from being set high in the path of transistor 28. Further, when selected by the transistor JIK, the r-) control line 32 is made floating to operate to avoid p% malfunction. That is, p conduction occurs due to the input of the S and G signals to the transistor 31,
When charging, the r-) control line J1 is at ground potential.
When the hood line is selected and operated, it will not reach a high level.

The cutting section 11 in the above-mentioned integrated circuit has conventionally been constructed as shown in FIG. 3. That is, high concentration impurity regions ax, , 4s used as interconnections are formed at a distance on one inner surface of the semiconductor substrate 41, an oxide film 44 is formed on the surface, and after death, high concentration impurity regions 4 J,' 4 Selectively edify so that each end of J is exposed. After that, a fuse 4J is formed on the surface. In this case, the polycrystalline silicon trench is formed of a metal (aluminum, molybdenum) layer or the like. However, if there is a defective bit as described above, the fuse must be blown out by irradiating it with 44 K/4 Ruthlede light. The only remedy for this is that polycrystalline silicon is used to test the functionality of semiconductor devices after they have been tested. It is better to form the 7h-holes with a metal layer in the subsequent device process. - The thickness of other films formed on the glass can be easily adjusted, and furthermore, it can be relatively easily formed into a structure that is easy to melt with a radar.

Damage to other surrounding elements due to heat generated when the fuse is blown out is also reduced and faster when the fuse is formed by a metal layer located on the upper layer. However, fuses made of metal layers, such as an aluminum upper layer or a molybdenum layer, have a very large reflection coefficient for LED light, and have the disadvantage that they are more difficult to blow than fuses made of polycrystalline silicon layers.

[Etitp purpose], ′, 1′・! The present invention was made in view of the above circumstances, and its purpose is to reduce the Radical reflection coefficient of the metal layer to be melted, so that it can be easily melted even in a melting process using K such as low/mother-warm Radical light. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[Approximate cost of sounding]

The present invention involves forming a metal layer whose surface is black with a high light absorption rate at least in a part of the rounded part so that the wiring of the temporary integrated circuit can be cut as necessary. The layer is rounded so that it can be cut by JIK fusion using low-density laser beams.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. As shown in Figure #I4, there is a high-concentration impurity region as a wiring on the inner surface of one side of a -conductivity type semiconductor substrate, for example, a p-type silicon substrate J1, 9, for example, a t diffusion region s.
x, ss are formed at a distance of □, and a cuttable region is formed at this separation. Benari-b, oxide film on the surface, e.g. 810, m
After forming the e08102 film J4 and turning the e08102 film J4 so that the end facing J4 is exposed, a metal layer 9, for example AlO--upper layer 65 is applied to its surface. Next, the upper layer JJO is formed to a thickness of about 0.8 μm by electron beam evaporation, as shown in FIG. In other words, a molybdenum layer IIC is formed by electron beam evaporation to a thickness of approximately 1 sooK on the surface of the upper layer 55 made of aluminum, for example.The formation conditions in this step are such that the semiconductor substrate j1 is
This molybdenum layer 56 is heated to 0 degrees Celsius or higher.
0 surface is subjected to machining, cinder treatment, and plasma etching treatment, for example.

That is, derasma treatment was carried out for 40 seconds in an atmosphere of CF4 gas x 5 Qcc/min, 0260 ccZ min, and a pressure of 005 torr.

Do Chinda. Since the surface of the plasma-etched metal layer is black, the reflectance against the incidence of Radical light can be significantly reduced. The mechanism of this blackening is that by heating the substrate 81 during vapor deposition of the molybdenum layer 56, molybdenum grows into columnar crystals, and etching progresses along the columnar grain boundaries in the subsequent etching process. Therefore, it has been found that the surface of the metal layer may deteriorate.Next, we cut the cuttable area as shown in Figure 4(B) by turning the metal layer so that it becomes part of the wiring. 0th order K to form a wiring with a 0th order K, a 0th order K to form a /f paste 1 film on this cuttable area, and a wiring O cutting process to be performed as necessary as shown in FIGS. 1 and 2. , 14
As shown in the figure (qK), the cuttable area is irradiated with ΔRusslede light (for example, 5 μl) for 100.4 seconds.

- The problem is that the laminated structure of the upper aS layer and the molybdenum layer 56 is melted down.In addition, in the above-mentioned example II, redundant circuits as shown in Figures 1 and 2 are provided to prevent the occurrence of some defective parts. Although the case where the present invention is applied to the integrated circuit repair means described above has been described, the present invention can also be similarly applied during or after manufacturing when a cutting process is required in the manufacturing process of an integrated circuit.

Previously, in the above embodiment, a precedent example was explained in which Raded light was irradiated as a means of fusing, but any method such as electron beam or heat ray irradiation may be used.Furthermore, in the above embodiment, a molybdenum layer was formed on an aluminum layer as a metal layer. Although an example in which the metal layer is deposited has been described, it may be formed using another metal layer such as MO81.

Furthermore, in the above embodiment, the black chemical coating of the metal layer 8! Explains the etching process using an example using etching. Not limited to rasmae and ching, but also chemical dry etching (COE) such as ion etching and ching, and ching moves are good at 4.

As explained above, according to the present invention, at least a part of the surface of the metal layer to be fused is made black with high light absorption, so even when irradiated with laser light, the light reflectance is extremely low. However, it is possible to provide a method for manufacturing a seat conductor device that can be easily fused even with low-power LED light. jl 5, . . .:1 amo"*'!"0, 0. Figure 1 is a circuit configuration diagram for explaining a semiconductor memory having a well-known redundant circuit, and Figure 2 is a diagram showing one word line selection in Figure 1. Specific circuit wiring diagram to repair defective bits in the circuit,
Fig. 3 is a rounded structural sectional view explaining the conventional manufacturing method of the cut portion in the stripe 2, and Figs. be.

51...Silicon substrate, is, ss...wiring, 54
...810. Film, 5j... Aluminum layer, 56.
... Molybdenum layer, 51... Rede light.

Applicant's agent: Patent attorney Suzue Takehiko:・ 1:1. ,.

L1 Figure 1 @t,B (A) (B) (C) 11th 57

Claims (7)

[Claims] (1) When forming a part Kw# line possible region of the wiring, the wiring is provided with a knee which is electrically wired and forms a black metal layer on at least a part of the surface thereof. A method for manufacturing a semiconductor device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer has a laminated structure in which a -1-lipden layer is formed on an aluminum layer. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the metal layer is formed by depositing a metal film having columnar crystals on its surface, and etching or etching the surface of the columnar crystal metal film. . (4) The method for manufacturing a semiconductor device according to claim 3, wherein the deposition of the columnar crystal metal film is performed by heating the substrate. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the metal layer is a budenyl oxide layer. (6) The method for manufacturing a semiconductor device according to claim 1, characterized in that the disconnection in the metal layer O is irradiated with an electron beam. (7) The method for manufacturing a semiconductor device according to claim 1, wherein the key metal layer is used for a circuit 01111 that activates a redundant circuit in the event of a failure.