JPS5819011A - Digital agc circuit - Google Patents

Abstract

PURPOSE:To improve the leading response speed of an AGC in a training sequence, by coupling an output of a comparator and a level detection signal of an operation processing section with an OR circuit and triggering a timer with the output of the OR circuit. CONSTITUTION:The gain of a variable amplifier 1 is controlled with an output value of an up-down counter 7 and an output C is inputted to a comparator 3 via a full-wav rectifying circuit 2. When a signal (c) is greater than a compared value (b), an input is given to a counter 7 via a selector to lower the gain of the amplifier 1. The output (c) is converted at an A/D converter, processed at an operation-section 5, and when the output is a dynamic range or below, the logic of a level detection signal (h) is taken to 1. The signal (h) is given to a timer 8, the counter 7 and the input of an FF9. Further, an OR circuit inputting the signal (h) and an output (d) of the comparison circuit 3 is provided and the output triggers the timer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital AGC for use in a data demodulator.
Regarding circuits.

In a data modulation/demodulation device with a built-in automatic equalizer, in order to converge the automatic equalizer, it is necessary to transmit a training sequence before transmitting the data signal, and after converging the automatic equalizer, transmit data. Common. Therefore, the demodulator needs to identify the training sequence from the received input. In order to secure the time required for this identification, an AGC circuit with as fast a response as possible is required.

Even in data modulation and demodulation equipment that does not have a built-in automatic equalizer,
In order to shorten the time l1Jj from the generation of a transmission request by the terminal to the time when transmission becomes possible, it is required that the initial response of the AGC circuit be quick.

Conventional analog AGC circuits used in data modulation and demodulation devices in Europe generally employ a peak AGC method in order to shorten the time required for initial response, ie, rise. The peak AGC method is a method in which the gain is quickly suppressed by the peak value of the reception signal (g) or a short-time input signal.Since the disturbance is large when impulsive noise is mixed into the received signal, the average value AGC method is used. It may also be used in combination with

For example, at the beginning of the received input signal, the peak A
It operates in GC mode to quickly change the gain, and after a certain period of time switches to average value AGC mode with a long time constant to prevent disturbances due to impulsive noise.

In the digital AGC circuit, as described above, the gain is quickly controlled immediately after receiving input, and after a certain period of time, the gain is adjusted by outputting the average value. I try to do it 1ilJIIll.

An example of such a conventional digital AGC circuit is shown in FIG. That is, the input signal Ae (8) is input to the variable amplifier 1 whose output is variable. During unmanned operation, the gain of the variable amplifier 1 is set to the maximum gain. That is, the gain of the ijJ variable amplifier l is determined by the output 1 of the up-down counter 7, and becomes the maximum gain when the output value 11 of the counter 7 is 0'', and becomes the minimum gain when the output value of the counter 7 is maximum. The output C of the variable amplifier 1 is input to the comparator 3 through the full-wave rectifier circuit 2 and compared with the comparison value.Then, when the input signal is a constant reference value b j By setting the output signal of the circuit 3 (j to be a logic pass 1" and inputting it to the count-up input of the amplifier-down counter 7 through the selector 6, the counter 7 counts and amplifies the frequency of the clock signal a and quickly varies the frequency. The gain of the amplifier l is lowered. When the output of the full-wave rectifier 2 is lowered due to the lower gain of the variable amplifier 1, the logic of the output signal d of the comparator 8 becomes M OI+,
The counter 7 stops counting and the gain of the variable amplifier 1 is maintained at the previous gain.

On the other hand, the output C of the variable amplifier 1 is converted into a digital value by the A/D converter (4) 4 and subjected to arithmetic processing by the arithmetic processing section 5. In other words, the human signal A is determined by the average value of several points of the input signal over a relatively short period of time.
Determine whether the level is within the dynamic range of the GC circuit, and if it is below the dynamic range, set the level detection signal logic to 1". If it is within the dynamic range, the signal logic is 0". It is. In addition, the average level is calculated by averaging over a relatively long period of time, and when the average level is higher than a certain value, an up signal e is output, and when the average level is below a certain value, a down signal f is output. .

The r'4TJg level detection signal is connected to the timer 8 and the reset inputs of the up/down counter 7 and flip-flop 9. Therefore, when there is no reception input A, the up/down counter 7 is reset by the logic "1" of the level detection signal, so the variable amplifier 61 is on standby at the maximum gain as described above. . Then, when the signal becomes @0" due to the reception input within the dynamic range, the up/down counter 7 becomes active, and the gain decreases due to the up-count by the signal d mentioned above, and the logic of the signal d becomes O". In other words, it is maintained at the planned level.

On the other hand, the timer 8 is triggered when the erasure signal is reversed from 1'' to 0'', and after a certain period of time, the flip-flop 9 is set by the output of the timer 8.

When the flip-flop 9 is set, the selector 6 selects the up signal e based on its output and connects it to the up input of the up/down counter 7. The down signal f is connected to the countdown input of the up/down counter 7.

Therefore, after the output of the timer 8, the gain of the variable amplifier 1 is controlled by a count-up or (d) count-down input based on the signal e or f that detects the average level.

That is, since the gain of the variable amplifier 61 is controlled by the average value, it is not disturbed by impulse noise.

The signals e and f are positive pulses having a pulse width equal to the period of the clock signal a, and their synchronization is performed by the arithmetic processing unit 5.
Since it almost matches the average value time constant of , the counting operation by signals e and f is done once in the above time constant period, and the gain change of 1-variable amplification 1 is done by one step in the above time constant period. be. That is, the gain i4 change fr' due to the signals e and f
iIt is gradual and does not change continuously and rapidly.

FIG. 2 shows the signal states of each part during the above-described operation. In other words, the signal 11 becomes 0'' with a slight delay from the time of input of the human power No. 1 A shown in Fig. 6412 (a).
b)), then for a certain period of time 1. So 1δ number l is “1”
(See figure (c)). JtJ where Iki No. 1 is 0″]
In iLH, the flip-flop 9 is in the reset state,
Selector 6Vi1 selects number d and outputs the length.

Therefore, the one gnoso down counter 7 is controlled by the signal d.
The amplifier counts at W speed, the gain of the variable 4-width amplifier 1 is quickly lowered, and its output C drops to a substantially constant value. After that, when the signal l becomes 1', the selector 6 is switched to perform average value detection (-, gain control is performed by No. 4 e or f, so the output C of the variable amplifier 1 is as shown in FIG. 2(d). It becomes like this.

(7) The conventional digital p, GC circuit as described above has the following drawbacks. That is, the waveform of the input signal A is generally the same as that of the main iN, as shown in FIG. 3(a).
The waveform has a transient precursor part A2 before Ji##jA. When the level of the input signal is low, the level of the precursor is also low, so the first level detection signal is already inverted from 0 to 0 at the first wave of the precursor (see Figure 8(b). )).If the duration of the glycercer is t, and the time required for AGC to rise is t3, then the average value AGC should not be applied until time t has elapsed after the input of the main signal AI. Since it is necessary, the set time 1 of the timer 8 is the time t and t.
, the time equivalent to the sum of , is required. However, the set time may essentially be as long as about 1 s, which is the time required for AGC to start up. For example, when the input signal is low, the level of the precursor section is low, so the signal is not inverted from 1" to 0" in the precursor section, but is inverted to 0" after the main signal A1 is manually input (8th Figure (d)
reference). In this case, it is sufficient to apply the average value AGC at a time of about t after (8) and shift to steady operation, but for the reasons mentioned above, timer 8
Since the set time is tI, there is a drawback that the time required to shift to steady operation is longer than necessary (see FIG. 8(e)). In other words, there is a drawback that the initial response period of the AGC is slow, that is, the start-up is slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital AGC circuit which solves the above-mentioned conventional drawbacks and improves the rise response speed of AGC within a training sequence.

The AGC circuit of the present invention includes a variable amplifier with a variable step gain, an up/down count that controls the gain of the variable amplifier, a comparator that compares the absolute value of the output signal of the variable amplifier with a reference level, and the variable An A/D converter that converts the output signal of the amplifier into a digital signal, and an A/D converter that processes the output of the A/D converter and outputs a level detection signal when it is below the dynasty range and increases depending on the level. an arithmetic processing unit that outputs a signal or a down signal; a timer that is triggered by the inversion of the level detection signal and temporarily outputs the output for a certain period of time; and a flip-flop that is set by the output of the timer and reset by the level detection signal;
a selector that selectively outputs either the output signal of the comparator or the up signal according to the output of the flip-frog; A digital AGC circuit configured to limit the gain of the variable amplifier to 1 by counting up and down according to the output signal or the down signal, comprising an OR circuit inputting the output of the comparator and the level detection signal. The invention is characterized in that the timer is triggered by the output of the OR circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention,
Elements and signals that are similar to those in FIG. 1 have the same reference numerals or symbols. The difference from the conventional example shown in FIG. The point is that the timer 8 is configured to be triggered by the signal. Therefore, as in the conventional case, the timer 8 is triggered when level detection No. 16 is inverted from "L" to ON, and outputs after the delay time t4 to set the flip-flop 9, but the output of the comparator circuit 8 is When the signal d is input in the form of a pulse, the above delay time t
4 is updated each time. That is, the timer 8 does not operate while the output signal d of the comparator circuit 3 is being outputted in a pulsed manner. The other configurations are the same as the conventional example shown in FIG.

Next, the operation of this embodiment will be explained. Now, Figure 5 (
When a receiving input signal A having a precursor part A and a main signal as shown in a) is input, and the receiving input level is, for example, OdBm, the signal shown in FIG. 5(b) is input. , the first wave of the precursor inverts the signal from 1'' to O'' and triggers the timer 8. However, every half wave of the signal A, the comparator circuit 8
) is input to the timer 8 via the OR circuit 1o, the timer 8i-1 is triggered every time the pulse falls, and the delay time is updated.

On the other hand, due to the same signal d, the gain of the 5T variable amplifier l1m device 1 decreases rapidly, and the AGC converges at the input of the main section A.
When the output signal d of the comparison circuit 8 is no longer output, since the timer 8 was triggered at the time of the last fall of the output signal d, an output signal is output from the timer 8 at time t4 and the flip-flop 9 is set. . Flip Frog 9 is
It is reset by @11+ of the level detection signal, but when it is set by the output of the timer 8, the output l becomes 11'' as shown in FIG. 5(d), and the selector 6 5 is selected and applied to the count-up input of the up-down counter.Therefore, it is possible to operate in the steady average value AGC mode after a delay time t4 from the time when the main signal is input.Next, , the level of input signal A is low, for example -40
When input at dBm, the signal C amplified by the maximum gain (for example, 41 dB) of the variable amplifier 1 becomes +1 dB in the main section, but at a much lower level in the precursor section. Therefore, as shown in FIG. 5(e), the level detection signal output from the arithmetic operation processing section 5 remains ++IH at the input signal A's cursor section.
It is only after the main part is input that it is reversed from +1111 to @O lung. On the other hand, the output signal JPjd of the comparator circuit 8 is not output from the precursor section of the input signal A, but becomes the main section, and when the level of the output C of the variable amplifier 1 reaches +1 dB, the output signal JPjd outputs "l" as the first wave. (See Figure 5(f)). When the up/down counter 7 counts 1 due to this signal d of 1'', the gain of the variable amplifier 1 is, for example, 2.7d.
Since the B gain decreases, its output C becomes -17 dBm. However, the variable increase [fil (7) gain from HO dB to 41
It is assumed that dB t changes in approximately 17 dB steps. Therefore, the signal d is not output after that. That is,
The timer 8 is triggered when the main part of the input signal A is input, and the signal is inverted from 1'' to 0'', or at the falling edge of the signal d (which is approximately the same time), whichever is later. After that, it is output with a delay time t4. Therefore, the output i of the flip-flop 8 becomes 1'' at the above-mentioned time point as shown in FIG. In other words, it shifts to a steady average value AGC operation. In this case, as mentioned above, since the input level is low, the time required for the step control of the variable amplifier 1 is small (in the above case, only one step). Therefore, the time required for the gain of the variable amplifier 1 to decrease and reach a steady state is short.When the input signal A in the dynamic range (-48 dBm to OdBm) is input, the level detection signal changes from "1" to 0. After reversing to t4+α
(α is smaller than t4), the steady average value A
It is possible to move to GC. That is, even with a long input signal to the glycercer section, it can be shifted to the average value AGCK in a time approximately equal to the sum of the signal detection time (which is very short) and the delay time t4 of the timer.

By appropriately setting the delay time t4, AGC can be performed in approximately the same amount of time from the input of the main section even when β is a signal with a long precursor, and whether the input is high or low. It is possible to set it up. That is,
It is possible to speed up the initial response time of AGC.

As described above, in the present invention, the conventional digital AG
In addition to the Clff1 path, the output of the comparator and the level detection signal of the arithmetic processing section are combined by an OR circuit, and the timer is triggered by the output of the OR circuit, so when the input level is high, the precursor The timer is re-triggered by the comparator output pulse generated by the comparator. As a result, it becomes possible to set the timer delay time appropriately, and the time required for the initial response of the AGC can be shortened. That is, it is possible to shorten the time required for the AGC to rise in the training sequence. For example, even if a roll-off filter with a low roll-off rate is used and the input signal has a long signal precursor, it is not necessary to increase the timer setting time as in the conventional method. is a dog.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional digital AGC circuit, Fig. 2 is a time chart showing signals of each main part to explain the operation of the digital AGC circuit, and Fig. 8 explains the drawbacks of the conventional example. FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. M5 is a time chart showing signal states of main parts of the above embodiment. In the figure, 1... variable amplifier, 2... full wave rectifier, 3... comparator, 4... A/D converter, 5... arithmetic processing unit, 6... selector, 7 ...Ack down counter, 8...Timer, 9...RS flip-flop, 10...OR circuit. Agent Patent Attorney Toshimune Sumita Figure 4-54- Figure 5 A? A1

Claims (1)

[Claims] a variable amplifier with a variable step gain; an up/down counter that controls the gain of the variable amplifier; and a comparator that compares the absolute value of the output signal of the variable amplifier with a reference level;
A converting the output signal of the variable amplifier into a digital signal;
an A/D converter, and an arithmetic processing unit that processes the output of the A/D converter, outputs a level detection signal when it is below the dynamic range, and outputs an up signal or a down signal depending on the magnitude of the level; a timer that is triggered by the inversion of the level detection signal and outputs after a certain period of time; a flip-flop that is set by the output of the timer and reset by the level detection signal; and an output signal of the comparator in accordance with the output of the flip-flop. or a selector that selectively outputs any one of the up signals; The digital AGC circuit configured to control the gain of the digital AGC circuit is further provided with an OR circuit that inputs the output of the comparator and the level detection signal, and the timer is triggered by the output of the OR circuit. A digital AGC circuit featuring