JPS58218169A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit comprising an MO8 type field effect transistor using a thin film medium conductor as a substrate, and relates to an electrode structure used for a gate.

M using an amorphous or polycrystalline thin film medium conductor as a substrate
Research and development efforts for O8 field effect transistors are being actively carried out. This is because if a semiconductor integrated circuit device having thin film MO8 field effect transistors as a component becomes practical, various great advantages will emerge. For example, we can expect significant cost reductions and large ICs.
With the realization of multi-layered ICs and the like, a wide range of applications for ICs will emerge.

This thin film 1j is currently being researched and developed everywhere.
There are some major problems with OEI field effect transistors and integrated circuit devices.

Among the major problems are leakage between the source and drain, and the problem of low transistor drive ability, ie, low mobility.

The drain leakage of the next transistor using a silicon single crystal substrate is 10-B when converted to one transistor.
~10-”A. In comparison, thin film MOs using amorphous silicon and polycrystalline silicon as substrates
The leakage between the source and drain of the B field effect type is I Ll-' ~ 1Q- when converted to one transistor.
10A, which is 2 to 5 digits more. Even with a static type drive, there is a lot of leakage, which causes problems, and a dynamic type drive cannot operate due to leakage.

Furthermore, among the applications of semiconductor integrated circuit devices that use thin-film MQS'IL field-effect transistors as constituent elements, there are applications in which they are directly exposed to light, such as being used as electrode panels for liquid crystal display panels. The leakage current value described above becomes even larger.

Furthermore, because of its low mobility, it is unsuitable for circuits that require speed, and its range of applications is limited. By the way,
The mobility in N-channel transistors using polycrystalline silicon is 60 to 40 cm/V"□e, and in the case of P-channel transistors, it is 10 to 20 cm/vl. An example will be described below with reference to FIGS. 1 to 3.

As shown in FIG. 1, a layer 5TOZ[2 of vapor phase growth is formed on a quartz glass substrate 1, and a P-type polycrystalline silicon layer 6 is formed thereon and selectively etched.

Thereon, thermal oxidation 5i02 t1g4 is formed to form gate electrode arrangement aS. As shown in Figure 2,
'A 19N+ diffusion layer 6 is formed on the on-implant, and a phosphosilicate glass 7 is formed thereon. Further, as shown in FIG. 5, an xD contact hole is formed by selective etching, and an M film 8 is formed thereon.

When the above structure is adopted, as mentioned above, vapor phase growth 5
Leakage occurs at the interface between i02 and polycrystalline silicon, and at the interface between grains in the polycrystalline silicon, and when exposed to light, charges are generated and leakage occurs. In particular, when used as an electrode substrate for a liquid crystal display panel, the leakage current is very large because the source is directly in contact with the quartz glass substrate side. Furthermore, as mentioned above, it is difficult to incorporate circuits J. which have low mobility and require high speed, such as an internal one-bit shift register.

The present invention improves the above-mentioned L5 drawbacks.
Another object of the present invention is to improve the performance of a transistor, and another object of the present invention is to reduce leakage current due to light. Furthermore, other objects of the present invention will be made clear in the following description of the present invention.

The present invention will be described below with examples shown in FIGS. 4 to 6.

As shown in FIG. 4, a vapor phase growth layer 5iQ212 is formed on the quartz glass substrate 11, and a lower gate electrode 15 is formed on it.
form. A vapor phase growth layer 51o21JjK14 is formed thereon, and N2 annealing is performed. Then, after forming a P strip crystal silicon IH 15 and selectively etching it, a thermally oxidized 5102 film 16 is formed. An upper electrode 17 is formed thereon.

As shown in Figure 5, the N+ diffusion layer 1 is
After forming 8, phosphosilicate glass 19 is formed.

Further, as shown in FIG. 6, a rainbow contact hole t6 is formed by selective etching, and an M wiring 20 is formed thereon.

If necessary, the lower gate electrode and the upper gate electrode are connected and short-circuited during the process.

As described above, according to the method of the present invention, voltage can be simultaneously applied to the upper gate electrode and the lower gate electrode to form an inversion layer from the upper and lower parts, and a current can be passed through the upper and lower inversion layers. A synergistic effect can also be expected by applying voltage from below.Furthermore, by using opaque electrode materials for the upper and lower gate electrodes, it is possible to block light from both the upper and lower directions, reducing leakage current. It becomes less. In addition, a gate electrode is formed at the bottom, and a depletion layer is also generated from the bottom, and leakage at the interface between the bottom insulating film and the thin conductor layer is also reduced.

Furthermore, if the upper gate electrode and the upper gate electrode are not short-circuited but are used as separate electrodes, a single-output transistor can be formed by two people.

In addition, the present invention exhibits the respective effects of the present invention even when both the upper and lower gate electrodes are made of gold, both are semi-transparent electrodes such as polycrystalline or amorphous/silicon, or both are used. I can do things.

Further, although the example has been given in which a quartz glass plate is used as the substrate, the same applies to cases where other glass materials, plastic materials, ceramic materials, and other materials are used.

Further, although the above description has been made regarding the gate material, sio, PIi+, and thermally oxidized Si Q2 film grown in the groove vapor phase, the same applies to the case where other materials are used. Further, although the example of the present invention is shown for N channel, the same applies to P channel and complementary type.

[Brief explanation of drawings]

1 to 3 are schematic cross-sectional views of the manufacturing process according to the conventional method. 4 to 6 are schematic cross-sectional views of the manufacturing process according to the method of the present invention. The following is as follows. : 1,. 11... quartz glass substrate), 2.12.14... vapor phase grown S i 02 film, 6.
15... P-type polycrystalline silicon layer, 4.16... Thermal oxidation 5102 film, 5... Gate electrode wiring, 6.18... N+ diffusion layer, 7.1? ...phosphosilicate glass, 8.20...
M wiring. 16...Lower gate electrode wiring, 17...Upper gate N-electrode wiring, Applicant Suwa Seikodai Co., Ltd. Patent attorney Mogami Tsutomu

Claims (2)

[Claims] (1) In a semiconductor integrated circuit device whose component is an MO8 field effect transistor using an amorphous semiconductor or a polycrystalline semiconductor thin film as a substrate, an insulating gate film is provided above and below the substrate to form an upper gate electrode and a lower gate electrode. A semiconductor integrated circuit device characterized by forming a gate electrode.・ (2) Claim 1, characterized in that the upper gate electrode and the lower gate electrode are short-circuited and have the same potential.
The semiconductor integrated circuit device described in .