JPS5834951A - Manufacture of double heat sink type semiconductor device - Google Patents
Manufacture of double heat sink type semiconductor deviceInfo
- Publication number
- JPS5834951A JPS5834951A JP56134566A JP13456681A JPS5834951A JP S5834951 A JPS5834951 A JP S5834951A JP 56134566 A JP56134566 A JP 56134566A JP 13456681 A JP13456681 A JP 13456681A JP S5834951 A JPS5834951 A JP S5834951A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- pair
- heat sink
- semiconductor device
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000465 moulding Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 14
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000005520 cutting process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000007789 sealing Methods 0.000 description 4
- 239000012778 molding material Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はモールド形半導体装置、特にダイオードや整
流器等2端子構造の半導体素子の両側にヒートシンクを
配設し、両電極面より放熱させるダブルヒートシンク構
造の半導体装置の製造方法(関する。[Detailed Description of the Invention] This invention relates to a method for manufacturing a molded semiconductor device, particularly a semiconductor device with a double heat sink structure in which heat sinks are disposed on both sides of a semiconductor element with a two-terminal structure such as a diode or a rectifier, and heat is dissipated from both electrode surfaces. (Regarding.
従来、ダイオードや整流器は小形で放熱特性が優れ、比
較的電流容量の大きいものが得られるため、素子電極の
両側に電極板を取付したDHD構造のものが主流を占め
ている。例えば、第1図はこの種DHD形ガラス封止ダ
イオード1の断面図であり、ダイオード素子2の両電極
2a、’2bが一対のジュメット材よりなる口出導体3
.8で挾着され、これらの周囲を覆ってガラス管4によ
り口出導体8の側面で封止されている。口出導体8の外
方には、一対のリード線5,5が溶接され。Conventionally, diodes and rectifiers are small, have excellent heat dissipation characteristics, and have a relatively large current capacity, so the DHD structure in which electrode plates are attached to both sides of the element electrode has been the mainstream. For example, FIG. 1 is a cross-sectional view of this kind of DHD type glass-sealed diode 1, in which both electrodes 2a and '2b of the diode element 2 are connected to a pair of lead conductors 3 made of Dumet material.
.. 8, and the glass tube 4 covers the periphery thereof and is sealed on the side surface of the outlet conductor 8. A pair of lead wires 5, 5 are welded to the outside of the outlet conductor 8.
ダイオード素子2内部で発生した熱は大径の口出導体8
を通して素子両側に導出するよう構成されている。とこ
ろで、このようなダイオード1をプリント基板等に実装
するには、図示・しないが、前記リード線5をプリント
基板の装着孔にピッチ合わせして成形し、この成形され
たリード線5をプリント基板の装着孔に弾接させて挿入
した後、半田付けして行われるが、作業が繁雑で多大の
工数を要していた。このため、第2図に示すように、小
径部6と大径部7を有する一対の日出導体8゜8を用い
、この小径部6の端面間にダイオード素子2の電極2a
、2bを挟着させ、ダイオード素子2を囲んで口出導体
8の小径部6の側面でガラス管4で封止したDHD形ガ
ツガラス封止ダイオード9案されている。(DHD形ダ
イオード出願番号51−118208昭和53年8月2
8日付参照)このダイオード9は口出導体8の大径部7
が板状であり、上記ダイオードの如く曲がり易いリード
線5を用いないから、取扱いが容易となりプリント基板
の取付に自動化が適用出来る等優れた効果を有するもの
である。The heat generated inside the diode element 2 is transferred to the large diameter outlet conductor 8.
It is configured to lead out to both sides of the element through the tube. By the way, in order to mount such a diode 1 on a printed circuit board or the like, the lead wires 5 are molded to match the pitch of the mounting holes of the printed circuit board, and the molded lead wires 5 are attached to the printed circuit board. This is done by inserting elastically into the mounting hole and then soldering, but this is a complicated process and requires a large amount of man-hours. For this reason, as shown in FIG.
. (DHD type diode application number 51-118208 August 2, 1973
8) This diode 9 is connected to the large diameter portion 7 of the outlet conductor 8.
Since it is plate-shaped and does not use a lead wire 5 that is easily bent like the diode described above, it is easy to handle and has excellent effects such as being able to apply automation to the mounting of printed circuit boards.
しかしながら、このように使用面で優れた特徴を有する
ダイオニド9も、一方製造面に於いては、小径部6と大
径部7を有する日出導体8の製造や、ガラス封止作業が
難しくなる欠点があった。即ち、日出導体8は小径円筒
状のジュメット部品と大径の板状部品を溶接等により接
合して得られるが所定寸法精度のものが得にくいもので
あった。又ガラス封止作業はカーボン治具等を用い、ダ
イオード素子2、口出導体8、ガラス管4等の封着部品
を位置合わせして装着し、ガラス管4を高温に加熱溶融
して行われるが、何分にも異形状の日出導体8の装着に
手間がかkり工数増となる等のため、高価となり、製造
及び使用の両面を併せて満足出来るダブルヒートシンク
構造の半導体装置は得られていない。However, even though Dionide 9 has such excellent characteristics in terms of use, in terms of manufacturing, it becomes difficult to manufacture the Hiji conductor 8 which has a small diameter part 6 and a large diameter part 7, and to perform glass sealing work. There were drawbacks. That is, the sunrise conductor 8 is obtained by joining a small-diameter cylindrical Dumet part and a large-diameter plate-like part by welding or the like, but it is difficult to obtain one with a predetermined dimensional accuracy. Further, the glass sealing work is carried out by using a carbon jig or the like to align and mount the sealing parts such as the diode element 2, the lead conductor 8, and the glass tube 4, and then heat and melt the glass tube 4 at a high temperature. However, mounting the irregularly shaped sun conductor 8 takes many minutes and increases the number of man-hours, making it expensive, and it is difficult to obtain a semiconductor device with a double heat sink structure that satisfies both manufacturing and usage aspects. It has not been done.
本発明は以上の点に鑑み提案されたものであり、プリン
ト基板への装着や取扱いが容易な構造で、しかも量産性
よく安価に製造出来るダブルヒートシンク構造の半導体
装置の製造方法を提供する。The present invention has been proposed in view of the above points, and provides a method for manufacturing a semiconductor device with a double heat sink structure that is easy to attach to a printed circuit board and handle, and can be mass-produced at low cost.
本発明に係る半導体装置は、半導体素子面主面に形成さ
れた電、極面がヒートシンクとなる一対の平坦な電極板
間にサンドイッチ構造にマウントされる。そしてこれら
の電極板間に半導体素子が固着されたマウント体は、半
導体素子及び両電極板の外端面を除く主要部分がモール
ド部材で被覆されるもので、一対の日出導体に平板状の
電極板を用いるため、製造が極めて容易となると共に、
細線のリード線を用いないチップ構造であるから、半導
体装置の使用が容易となる等優れた効果が得られる。か
−る構造の半導体装置の製造は、少なくとも次の如き工
程を経て製造される。即ち、1 半導体素子の両主面に
形成された電極面を一対の電極板間に固着する半導体素
子のマウント工程、2 前記半導体素子の固着されたマ
ウント体を複数個、夫々の電極板の両主面をこれらの電
極板より大きく形成されたマウント体の保持具、例えば
−組の基台間に密着議定させ、前記電極板の外端面をカ
バーする工程、
8 前記電極板の端面をカバーした保持具の各マウント
体間の空隙内にモールド部材を充填し、前記半導体素子
と前記電極板を一体にモールドする工程、
4 前記充填されたモールド部材を固化する工程、5
前記モールド部材の固化層、前記−組の基台を前記一対
の電極板の端面から除去する工程、及び6 前記固化さ
れたモールド部材を半導体素子間で切断分離し個々の半
導体装置を得る工程とを含むもので、半導体素子の両電
極面を固着する一対のヒートシンクとなる電極部材に、
製造容易な平板状電極部材が使用され、又モールドタイ
プであるから従来のガラス封止タイプに比べ封止作業が
容易且つ量産性に優れる等、製造及び使用両面に亘って
優れた特徴を有するダブルヒートシンク構造の半導体装
置が安価且つ能率よく製造される。The semiconductor device according to the present invention is mounted in a sandwich structure between a pair of flat electrode plates, with the electrode surface formed on the main surface of the semiconductor element serving as a heat sink. The mount body in which the semiconductor element is fixed between these electrode plates is one in which the main parts of the semiconductor element and both electrode plates except for the outer end surfaces are covered with a molding material. Since it uses a plate, manufacturing is extremely easy, and
Since the chip structure does not use thin lead wires, excellent effects such as ease of use of the semiconductor device can be obtained. A semiconductor device having such a structure is manufactured through at least the following steps. That is, 1. a semiconductor element mounting step in which the electrode surfaces formed on both main surfaces of the semiconductor element are fixed between a pair of electrode plates; 2. a plurality of mount bodies to which the semiconductor element is fixed are mounted on both sides of each electrode plate; 8. Covering the outer end surface of the electrode plate by placing the main surface of the mount body in close contact with a holder, for example, a pair of bases, the main surface of which is larger than the electrode plates; 8. Covering the end surface of the electrode plate; a step of filling a mold member into the gap between each mount body of the holder and integrally molding the semiconductor element and the electrode plate, 4 a step of solidifying the filled mold member, 5
a step of removing the solidified layer of the mold member and the set of bases from the end faces of the pair of electrode plates, and 6 a step of cutting and separating the solidified mold member between semiconductor elements to obtain individual semiconductor devices. The electrode member, which serves as a pair of heat sinks that fixes both electrode surfaces of the semiconductor element,
The double electrode has excellent features in terms of both manufacturing and use, such as using a flat electrode member that is easy to manufacture, and being a mold type, making the sealing work easier and easier to mass-produce than conventional glass-sealed types. A semiconductor device having a heat sink structure can be manufactured inexpensively and efficiently.
以下本発明の実施例を図面と共に詳述する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第3図は本発明方法で得られるダブルヒートシンク構造
の半導体装置の一実施例で、樹脂封止タイプの81ダイ
オード11が示されている。1ン1に於いて12はプレ
ーナ構造のダイオード素子で、両主面には図示しないが
内部のP−N接合に対応したアノード電極12a1及び
カソード電極12bがオーミックコンタクトの良好な金
属、例えばAu 、 Aqの蒸着又はノブキ法等で形成
されている。13及び14はこれらの両電極1272,
12bに夫々銀ペースト等の鑞材15により接合された
平板電極で、素子12の電極導出端子及びヒートシンク
として作用する。16は素子12及び平板電極18.1
4の外端面13a、14aを除く主要部を被覆したエポ
キシ樹脂等のモールド部材である。か(る構造のダイオ
ード11は、素子12が一対の平板電極18.14間に
挟着された状態で接合されており、素子12内部で発生
した熱はこれらの両平板電giA13.14を通して両
側に放熱される。又、一対の平板電F!i!、18,1
4の外端面1112,14aが夫々露出して樹脂封止さ
れているから、これらの端面18a、14aを、図示し
ないがプリント基板等の導電ランドに半田付は等により
取付出来、リードを用いないチップ構造であるから、取
扱いが容易である。FIG. 3 shows an embodiment of a semiconductor device having a double heat sink structure obtained by the method of the present invention, in which a resin-sealed type 81 diode 11 is shown. In 1-1, 12 is a diode element with a planar structure, and although not shown on both main surfaces, an anode electrode 12a1 and a cathode electrode 12b corresponding to the internal P-N junction are made of metal with good ohmic contact, such as Au, It is formed by Aq vapor deposition or the Nobuki method. 13 and 14 are these two electrodes 1272,
12b, each of which is a flat plate electrode bonded with a solder material 15 such as silver paste, serves as an electrode lead-out terminal of the element 12 and a heat sink. 16 is the element 12 and the flat electrode 18.1
This is a molded member made of epoxy resin or the like, which covers the main parts of 4 except for the outer end surfaces 13a and 14a. In the diode 11 having such a structure, the element 12 is sandwiched between a pair of flat plate electrodes 18 and 14, and the heat generated inside the element 12 is transferred to both sides through these flat plate electrodes giA13 and 14. The heat is radiated to .In addition, a pair of flat plate electrodes F!i!, 18,1
Since the outer end surfaces 1112, 14a of 4 are exposed and sealed with resin, these end surfaces 18a, 14a can be attached to conductive lands of a printed circuit board, etc. (not shown) by soldering, etc., without using leads. Since it has a chip structure, it is easy to handle.
次にか−る構造の81ダイオード11の製造方法につい
て述べる。先づ、第4図に示すようにダイオード素子1
2の両電極12a、12bを一対の平板電極18.14
間にApペースト等の鑞材15を介してサンドイッチ式
に接合して固着する。Next, a method of manufacturing the 81 diode 11 having the above structure will be described. First, as shown in FIG.
Both electrodes 12a and 12b of 2 are connected to a pair of flat electrodes 18.14.
They are joined and fixed in a sandwich manner with a solder material 15 such as Ap paste interposed therebetween.
このダイオード素子12の平板電極18.14への取付
けは、図示しないが、例えばカーボン治具等を用いてコ
ンベア炉に通す方法等通常の半導体マウント装置を用い
て容易に達成出来る。又、用いる鑞材15は、A9ペー
ストの住辛導体素子12及び平板電極18,1.4と接
着性良好な半田部材、例えば金錫半田や銀錯半田等を用
いることが出来る。次に、半導体素子12の両軍%12
a、12bを平板電i1.8.14に取付したマウント
体17は第5図に示すように、先づ一方の平板電極14
側の外端面14aを平板状基台18に接着材19等を用
いて複数個所定間隔離間して固定する。接着材]9とし
ては、後述する半導体素子12のモールド時、電極端面
14aが充分カバー出来る程度の接着力を有し、モール
ド部材の同化后容易に剥離出来る樹脂性接着材が用いら
れる。又、20は平板状基台18の各マウント体17間
に設けた仕切板で、必らずしも必要でないが、モールド
部材固化後の切断分離を容易にしている。次に他方の平
板電極13上から平板状基台21を接着材19を用いて
その電極端面13aを同様に密着固定させる。即ち、平
板状基台18及び21はマウント体17の夫々の電極端
面1412.j8aが密着固定されるマウント体17の
モールド用保持具であり、必らずしも平板状基台として
これに接着剤で固定する必要はなく、要は各マウント体
17のモールドに先立ち、各マウント体17の電極端面
14a、13aがカバーされる構造であればよい。Although not shown, the diode element 12 can be easily attached to the flat plate electrode 18.14 using a conventional semiconductor mounting apparatus, such as a method of passing the diode element 12 through a conveyor furnace using a carbon jig or the like. Further, as the solder material 15 to be used, a solder material having good adhesion to the A9 paste conductor element 12 and the flat plate electrodes 18, 1.4, such as gold-tin solder or silver complex solder, can be used. Next, both sides of the semiconductor element 12% 12
As shown in FIG.
A plurality of side outer end surfaces 14a are fixed to the flat base 18 using an adhesive 19 or the like at predetermined intervals. As the adhesive 9, a resinous adhesive is used which has enough adhesive strength to sufficiently cover the electrode end face 14a during molding of the semiconductor element 12, which will be described later, and which can be easily peeled off after assimilation of the mold member. Further, 20 is a partition plate provided between each mount body 17 of the flat base 18, which, although not necessarily necessary, facilitates cutting and separation after the mold member has solidified. Next, the electrode end surface 13a of the flat base 21 is similarly tightly fixed from above the other flat electrode 13 using the adhesive 19. That is, the flat bases 18 and 21 are connected to the respective electrode end surfaces 1412 . j8a is a mold holder for the mount body 17 to which the mount body 17 is closely fixed, and it is not necessarily necessary to fix it to this as a flat base with adhesive. Any structure may be used as long as the electrode end faces 14a and 13a of the mount body 17 are covered.
次に、このように両電極板18.14が平極板基台18
.21間に固定され、両電極外端面13a、14aがカ
バーリングされた複数個のマウント体17は、第6図に
示すように、両基台18゜21間の空隙内にエポキシ、
シリコン等の樹脂材、又はガラス材等のモールド部材1
6を充填することにより、半導体素子12及び両手板電
極13゜14が一体にモールドされる。モールド部材1
6の充填は、ディップ法、スプレー法、射出法等種種の
方法が採用されるが、両電極18.14の外端面18a
、14aは基台18.24でカバーリングされ、この部
分にはモールド部材16が被覆されないようにする。次
にモールドされたマウント体17は所定の温度でモール
ド部材16を固化した後、全体を接着材19の洗浄液中
に浸すと、第7図に示すように、平板状基台18,21
が平板電i13.14から除去されると同時に、接着材
19が剥離され両手板電極の外端面laa、14aが露
呈する。その後、矢印図示するように各素子12間でモ
ールド部材16を切断分離することにより、第3図に示
すダブルヒートシンク構造のS1ダイオード11が同時
に多数個製造される。Next, both electrode plates 18.14 are attached to the flat plate base 18 in this way.
.. As shown in FIG. 6, a plurality of mount bodies 17, which are fixed between the two bases 18 and 21 and whose outer end surfaces 13a and 14a of both electrodes are covered, are filled with epoxy,
Mold member 1 made of resin material such as silicone or glass material
6, the semiconductor element 12 and both-handed plate electrodes 13 and 14 are integrally molded. Mold member 1
Various methods such as a dip method, a spray method, and an injection method are used for filling the electrodes 18 and 14.
, 14a are covered with a base 18.24, so that this part is not covered with the molding member 16. Next, after solidifying the mold member 16 at a predetermined temperature, the molded mount body 17 is immersed in a cleaning solution for the adhesive 19. As shown in FIG.
At the same time as the electrodes are removed from the flat electrodes i13 and 14, the adhesive 19 is peeled off and the outer end surfaces laa and 14a of the electrodes on both hands are exposed. Thereafter, by cutting and separating the mold member 16 between each element 12 as shown by the arrows, a large number of S1 diodes 11 having the double heat sink structure shown in FIG. 3 are manufactured at the same time.
この切断分離は、ダイシング法、プレスカット法等種々
の方法が採用されるが、図示するように、基台18.2
1のモールド部材16切断予定域にモールド部材16と
非接着性の仕切板20を設けてお七と、切断分離が容易
となる。又、モールド部材16の充填を、第8図に示す
ように、個々の素子12毎に行ない各素子12間に空隙
を設けるようにすれば、モールド部材16の固化後の切
断作業が不要になる。Various methods such as a dicing method and a press cutting method can be used for this cutting and separation.
By providing the mold member 16 and a non-adhesive partition plate 20 in the area where one mold member 16 is to be cut, cutting and separation becomes easy. Furthermore, if the mold member 16 is filled in each individual element 12 and a gap is provided between each element 12, as shown in FIG. 8, cutting work after the mold member 16 is solidified becomes unnecessary. .
第9図及び第10図は、本発明に係る他の実施例で、上
記実施例の平板電i13.14に、個々の電極板となる
複数個の半導体素子12のマウント部と、これらのマウ
ント部間を接続する連結部とで構成したフレーム体が用
いられ、夫々半導体素子12のマウント后の状態が示さ
れている。即ち、第9図に示すフレーム体22は、隣接
するマウント部23間を連結片24で複数個縦横に連結
したものであり、又第10図に示すフレーム体25は、
−、tの巾広の電極板26をプレス打込み又は切削加工
で縦横の溝27を形成して複数個のマウント部28を構
成したもので、これらのフレーム体22及び25は、マ
ウント部28及び28が多数板状に連結されており、取
扱いが容易となり、自動化に適する利点がある。これら
のフレーム体22.25を用いたものも、同様に個々の
電極板となるマウント部28及び28の背面側が図示し
ないが一対の基台18.21でカバーされ、基台’18
.21間にモールド部材16が充填される。FIGS. 9 and 10 show another embodiment of the present invention, in which a flat plate electrode i13.14 of the above embodiment is provided with mounting portions for a plurality of semiconductor elements 12 serving as individual electrode plates, and these mounts. A frame body is used, which is made up of connecting parts that connect the parts, and the state after the semiconductor element 12 is mounted is shown in each frame body. That is, the frame body 22 shown in FIG. 9 has a plurality of adjacent mount parts 23 connected vertically and horizontally by connecting pieces 24, and the frame body 25 shown in FIG.
A plurality of mount parts 28 are constructed by forming vertical and horizontal grooves 27 in a wide electrode plate 26 of -, t by pressing or cutting. 28 are connected in a plate shape, which has the advantage of being easy to handle and suitable for automation. Similarly, in the frame body 22.25, the back sides of the mount parts 28 and 28, which serve as individual electrode plates, are covered by a pair of bases 18.21 (not shown), and the base '18
.. The mold member 16 is filled between the spaces 21.
そして固化後、切断分離され、夫々第11図及び第12
図に示すダブルヒートシンク構造のダイオード29.8
0が得られる。これらのダイオード29、!30は、平
板電極のマウント部28.28の外端面がモールド部材
16から露出するばかりでなく、側面の連結片24や溝
26の切断面81が露出した構造が得られ、この露出し
た切断面31をプリント基板等の取付けに利用すること
が出来便利である。After solidification, they are cut and separated, as shown in FIGS. 11 and 12, respectively.
Diode 29.8 with double heat sink structure shown in the figure
0 is obtained. These diodes 29,! 30 has a structure in which not only the outer end surface of the flat plate electrode mounting portion 28.28 is exposed from the mold member 16, but also the connecting piece 24 on the side surface and the cut surface 81 of the groove 26 are exposed, and this exposed cut surface 31 can be conveniently used for attaching printed circuit boards, etc.
本発明は以上のように、ヒートシンクとなる一対の平板
状電極体間に半導体素子の両電極を固着し、この半導体
素子の固着されたマウント体複数個をそれぞれの電極体
を各マウント体のモールド用保持具に密着固定して、電
極体の端面をカバーした後、両爪台間にモールド部材を
充填して半導体素子と電極体を一体にモールドし、モー
ルド部材を固化した後カバーリングを除去して個々の半
導体装置を得るように構成したから、製造が容易となり
、しかもプリント基板への装着や、取扱いの容易なチッ
プ構造のダブルヒートシンク形半導体装置が提供出来る
。As described above, the present invention fixes both electrodes of a semiconductor element between a pair of flat electrode bodies serving as a heat sink, and attaches each electrode body to the mold of each mount body. After tightly fixing the electrode body to the holder and covering the end face of the electrode body, fill the molding material between both claw stands to mold the semiconductor element and the electrode body together, and remove the cover ring after solidifying the molding material. Since the semiconductor device is constructed so as to obtain individual semiconductor devices, it is possible to provide a double heat sink type semiconductor device having a chip structure that is easy to manufacture, easy to mount on a printed circuit board, and easy to handle.
第1図及び第2図は従来のダブルヒートシンク形半導体
装置の断面図、第3図は本発明に係るダブルヒートシン
ク形半導体装置の断面図、第4図乃至第7図は第3図の
製造過程を示す部品断面図、第8図は第3図の一実施態
様を示す部品断面図、第9図乃至第12図は本発明の他
の実施例を示す部品及び製品の斜視図である。
11.29.80・・・・・・ダブルヒートシンク形半
導体装置、 12・・・・・・半導体素子、18
.14,22.25・・・・・平板状電極体、13aI
14a・・・・・・端面、
16・・・・・・モールド部材、17・・・・マウント
体、18.21・・・・・・保持具(基台)。
第1 国
14久1 and 2 are cross-sectional views of a conventional double heat sink type semiconductor device, FIG. 3 is a cross-sectional view of a double heat sink type semiconductor device according to the present invention, and FIGS. 4 to 7 are manufacturing steps shown in FIG. 3. FIG. 8 is a cross-sectional view of parts showing one embodiment of FIG. 3, and FIGS. 9 to 12 are perspective views of parts and products showing other embodiments of the present invention. 11.29.80...Double heat sink type semiconductor device, 12...Semiconductor element, 18
.. 14,22.25... Flat electrode body, 13aI
14a...End face, 16...Mold member, 17...Mount body, 18.21...Holder (base). 1st country 14 years
Claims (1)
して前記一対の平板状電極体を保持具に密着させ、前記
保持具内の空隙内にモールド部材を充填して前記半導体
素子のモーlレド体を形成し、前記保持具を前記一対の
平板状電極体から除去し、前記モールド体のモールド部
材を前記半導体素子間で切断分離することを特徴とする
ダブルヒートシンク形半導体装置の製造方法。A plurality of semiconductor elements clamped by a pair of flat electrode bodies are spaced apart, and the pair of flat electrode bodies are brought into close contact with a holder, and a molding member is filled into the gap in the holder, so that the semiconductor elements are Manufacturing a double heat sink type semiconductor device, characterized in that a molded body is formed, the holder is removed from the pair of flat electrode bodies, and the mold member of the molded body is cut and separated between the semiconductor elements. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134566A JPS5834951A (en) | 1981-08-26 | 1981-08-26 | Manufacture of double heat sink type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134566A JPS5834951A (en) | 1981-08-26 | 1981-08-26 | Manufacture of double heat sink type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5834951A true JPS5834951A (en) | 1983-03-01 |
| JPS6234153B2 JPS6234153B2 (en) | 1987-07-24 |
Family
ID=15131327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56134566A Granted JPS5834951A (en) | 1981-08-26 | 1981-08-26 | Manufacture of double heat sink type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834951A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0893808A1 (en) * | 1994-06-10 | 1999-01-27 | Avx Corporation | Preforms for the fabrication of surface mountable solid state capacitors |
| EP1253637A3 (en) * | 2001-04-25 | 2004-03-03 | Denso Corporation | Semiconductor device including heat sinks and manufacturing method therefor |
| EP1148547A3 (en) * | 2000-04-19 | 2005-06-15 | Denso Corporation | Coolant cooled type semiconductor device |
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| ITMI20112300A1 (en) * | 2011-12-19 | 2013-06-20 | St Microelectronics Srl | CONSTRUCTION OF DSC-TYPE ELECTRONIC DEVICES VIA SPACER INSERT |
-
1981
- 1981-08-26 JP JP56134566A patent/JPS5834951A/en active Granted
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0893808A1 (en) * | 1994-06-10 | 1999-01-27 | Avx Corporation | Preforms for the fabrication of surface mountable solid state capacitors |
| EP1047087A1 (en) * | 1994-06-10 | 2000-10-25 | Avx Corporation | Method of manufacturing solid state capacitors |
| US7106592B2 (en) | 2000-04-19 | 2006-09-12 | Denso Corporation | Coolant cooled type semiconductor device |
| EP1148547A3 (en) * | 2000-04-19 | 2005-06-15 | Denso Corporation | Coolant cooled type semiconductor device |
| US7248478B2 (en) | 2000-04-19 | 2007-07-24 | Denso Corporation | Coolant cooled type semiconductor device |
| US7250674B2 (en) | 2000-04-19 | 2007-07-31 | Denso Corporation | Coolant cooled type semiconductor device |
| EP1742265A3 (en) * | 2000-04-19 | 2011-02-16 | Denso Corporation | Coolant cooled type semiconductor device |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| US6963133B2 (en) | 2001-04-25 | 2005-11-08 | Denso Corporation | Semiconductor device and method for manufacturing semiconductor device |
| EP1253637A3 (en) * | 2001-04-25 | 2004-03-03 | Denso Corporation | Semiconductor device including heat sinks and manufacturing method therefor |
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| US8309434B2 (en) | 2006-06-05 | 2012-11-13 | Denso Corporation | Method for manufacturing semiconductor device including semiconductor elements with electrode formed thereon |
| ITMI20112300A1 (en) * | 2011-12-19 | 2013-06-20 | St Microelectronics Srl | CONSTRUCTION OF DSC-TYPE ELECTRONIC DEVICES VIA SPACER INSERT |
| US9159644B2 (en) | 2011-12-19 | 2015-10-13 | Stmicroelectronics S.R.L. | Manufacturing of DSC type electronic devices by means of spacer insert |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6234153B2 (en) | 1987-07-24 |
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