JPS5872260A - Memory sharing device - Google Patents

Abstract

PURPOSE:To make use of a memory connected to an opposite bus possible by converting an address by an individual name and access level in case of using a common memory in a computer composite system. CONSTITUTION:At the time of memory access by processors 1001-100n respectively connected to processor adaptors 1201-120n, these adaptors 1201-120n output memory addresses and names and access level signals which are peculiar to respective processors to a common bus 400. An address conversion table in an address converter 300 connected to the common bus 400 converts the address outputted from the processors 1001-100n. Only when the access levels are higher that the contents of an access level register, a common memory 200 is permitted to be accessed.

Description

[Detailed Description of the Invention] The present invention provides memory sharing in a computer complex system.
It is related to the device.

In recent years, computer systems combining multiple inexpensive processors with excellent reliability and high speed have been developed in various places, and the results are highly anticipated.

One of the purposes of such computer complex systems is to easily realize functional distributed processing, load distributed processing, and parallel processing (by sharing the memory of each processor with other processors). .

Conventionally, when connecting a new common bus type composite processor of the same type to a so-called common path type composite processor that connects multiple processors on a common path, one processor is connected between the two common paths. A method is adopted in which two-way address translation tables are connected, the address output from the processor is translated, and the memory connected to the common path of the other party is accessed.

According to this method, an arbitrary address space of each processor is allocated to the memory connected to the common path of the other side, and when accessing the memory, each processor f side is responsible for the address output from each processor. An inconvenience arises in that the address must be converted or output in a unified address format taken into consideration when the user creates the program, and then the address must be further converted using an address conversion table. On the other hand, it is necessary to provide memory protection means for the O3IIC, which has the disadvantage of increasing the burden on the O8.

The present invention has been made in consideration of the above-mentioned drawbacks of the conventional art.
Accordingly, an object of the present invention is to provide memory that corresponds to each processor and is selected based on the unique name and access level of the plurality of processors when using a memory connected to a common bus from a plurality of processors. A novel memory sharing device which performs address translation using multiple address translation tables, and which is equipped with a memory protection mechanism and which allocates and accesses the memory space of nine partners as an individual memory space for each processor, thereby solving the above-mentioned drawbacks of the conventional memory sharing device. Our goal is to provide the following.

The above object of the present invention is to connect a plurality of processors forming a first group to a first bus, to connect a memory to each of the plurality of processors, and to connect a plurality of processors forming a first group to a first bus. The shared memory connects the processor and at least the shared memory, and further connects the first bus and the first bus to the first group Kt with a unique name and access level of the 1111ko processor included in the first group. This is achieved by a memory sharing device characterized in that it is connected by an address translation device that provides an address of .

Hereinafter, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory sharing device according to the present invention. In the figure, a plurality of processors tloo1 to 100rr are connected to the common path 〇〇 through respective adapters /con1 to /con. Further, local memories /101 to /10n are connected to each of the plurality of processors 1001 to 100nK. Further, the common bus 4100 and the common bus soo are connected by an address translation device 5ooK. common bus zoo
K is also connected to a shared (used) memory core 00.

FIG. 1 is a block diagram showing an embodiment of an address translation device constituting a memory sharing device according to the present invention. The address translation device yoo has n address translation tables 3101 to 3101 to 100m corresponding to the processors 1001 to 100m connected to the common bus K11l and n access levels corresponding to the processors 1001 to 100n. Register 3/j1~3tsn,! : Control N part s2゜ and data output from the processor are shared on a common bus! 00
and a gate circuit 330 for outputting to.

Next, the functions of each part constituting the device according to the present invention will be explained.

The processor adapters 01-/20n output memory addresses, processor-specific names, and access level signals to the common bus 4100 when the processors 1001-100n connected thereto access the memory. The address translation device 300 has address translation tables 3101 to J#7nf corresponding to the processors 1001 to 100nK connected to the common bus 200, and address translation tables 3101 to J#7nf that are selected by the control unit 3 and correspond to the respective processors. This converts the nine addresses output from the processor.

Further, the 1-address translation device 300 has access level registers 3111-5tsnwo corresponding to the processors 1001-100n connected to the common bus 1Ioo, and the access level value is preset in the bov register. The access level is a priority level value that determines whether access is possible when accessing the shared memory SOO from each processor, and access is possible only when the level value to be accessed is higher than the preset access level register value. forgiven.

If access is not permitted, that is, if the level value to be accessed is lower than the preset access level register value, a protection signal is sent from the control unit 320 to the processor that requested the memory access.

Next, the operation of the device according to the present invention will be explained with reference to FIG. 7 and FIG. 1. For ease of explanation, it is assumed that one processor 1001 and 1002 are connected to the common path OOK, and that the common bus 200 is connected to the shared memory J00. Therefore, the processor 1001. 100
Local memo 9 connected to 2 ttol, tt
o2 Tsume % Recapacity 1d to 4 +KW, and shared memory co oo FitoKW. Note that the address conversion is performed by /KW@PC. Also, the address translation device 5ooco access level register 3/11.
JonK will be explained on the assumption that @J'' and @J'' are highlighted, respectively.

Now, the local memory of processor 1001/lower lKw of 101 is allocated to the local memory of processor 1002/the upper kw of shared memory 200.
Assume that tKW of shared memory JOO is allocated to 7V and 1Kw of shared memory JOO, and tKW of shared memory 200 is occupied by processor 1O01.
11l is shared by processor 1001 and processor 1002.

Figure 3 shows the contents of the address translation table at this time.
In FIG. 3, AT/ corresponds to processor 1001, and AT- corresponds to processor 1002K.

To further explain FIG. 3 in detail, access t 1oo1
accesses the address included in the lower iKW of local memory/101 of access t 1oo1 (IN)
, according to the address translation table 5io1 corresponding to the processor l001 of the address translation device 300] shared memory 2
Addresses included in the 7 fields of 00 are accessed (OU
T) means something.

Under these conditions, when processor 1O01 accesses an address in the lower l penalty at access level @J'',
Access name 1 at the same time as the address from Proryu Tuna adapter/co 01 connected to processor 1001
001 and access level signal 'J#' are output. The control unit Jco0 of the address conversion device 3θθ receives the access level signal II output from the processor adapter 1101.
Compare the value @J'' of access level register 3/!11 corresponding to JI''hi-processor 1001. in this case,
The 9 access level value output from access "W" 1001 is stored in access level register 3! When the value is 1, the processor name lθθ嘗 output from the processor adapter/101 is decoded and the processor name
The address conversion table 3101 corresponding to 1 is selected. The address output from the processor 1001 is converted by the address conversion table 3101,
Access 7KW of shared memory JOO. Note that at this time, data output from the processor 1001 is also sent and received by the control unit 3O via the second gate circuit 330.

Next, an example of accessing the shared memory 〇〇 from the processor 002 will be explained. Let us consider a case where the processor 1002 accesses the upper part of the local memory using the access level signal ``similar to access t1001.

In this case, the processor adapter/co 02 outputs the friend address from the processor 1002 to the common bus 00, the unique name 10θ2 of the processor 1002, and the access level signal 1co”.Access f 1002
The access level signal llJ'' output from the access level register J/j2 corresponding to the processor 1002
is compared with the value "4!-". In this case, when the value of the access level register 31!2 is larger than the access level value of the access f1002, the processor 1002 is not given the access right and the protection signal is sent from the control unit J0 to the processor 1002. returned.

Note that when the accesses 1001 and 1002 output an address that is not assigned to the address translation table, the address translation device 3000 control unit 320 does not output the address to the common bus 200 and outputs the address to each processor/θ0.
1, 1002 local memory/101. /1
Access 02.

In the explanation so far, addresses in the local memory of each processor are considered to be shared memory, but it is easily possible to allocate addresses beyond the local memory to shared memory 100. In this case, the processor adapter may be equipped with a function to output the processor address, processor-specific name, and access level signal only in the next case beyond the local memory.

In addition, it would be more effective to allocate the shared memory for each KW, but to do so by the segment method.

In addition, in this explanation, in order to make the explanation easier, we will use the common bus!
Although θOK was not connected to a processor, this is naturally necessary in an actual computer complex system. Furthermore, it is conceivable to connect a shared memory to the common bus 4100 as well. In this case, address translation tables for the number of processors are connected to the address translation device in the direction from the common bus 200 to the common bus l100.

Also, in this explanation, setting and resetting the address translation table and setting and resetting the access level register are performed statically, but it would be even more effective if they were performed dynamically with one processor dedicated to it. be.

Furthermore, it is also possible to set access levels for each read/write.

As explained above, the present invention connects a common bus type computer complex system, enables each processor to use the memory connected to the other party's path by the address translation table corresponding to the other processor, and allows each processor to use an arbitrary The present invention provides a memory sharing device which can allocate a memory space to an arbitrary memory space of the other party's memory and which has a film-retaining mechanism in the memory, and is extremely effective in practical use.

The present invention has been described above with respect to one preferred embodiment thereof, but
These are merely illustrative, and it goes without saying that the present invention is not limited to the nine embodiments described herein.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a memory sharing device according to the present invention, FIG. 1 is a block configuration diagram showing a specific example of an address translation device of the memory sharing device shown in FIG. 1,
FIG. 3 is a conceptual diagram showing an example of an address translation table. 1001-100n--processor, /101-l1
0r1...Local memory, /ko01~/koOn...
・Pulcessor adapter 1.200...shared memory, 3
00...Address translation device, riθ0. ! 900...
Common bus, 3101 to J10n...Address conversion table, j/61 to . 7/jn...Access level register, 3 pieces O...Control unit, 330...Gate circuit. Patent applicant: NEC Corporation Representative: Patent attorney Yutabe Kumagai Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A plurality of processors forming a first group are connected to the first bus, each memory is connected to the plurality of processors, and at least a shared memory is connected to the first bus with the plurality of processors forming the first group. connecting the first path to the first path and giving the first group an address of the shared memory with a unique name and access level of a plurality of processors included in the group of stripes L; A memory sharing device characterized by being connected by an address translation device.