JPS5882560A - Cmos integrated circuit - Google Patents
Cmos integrated circuitInfo
- Publication number
- JPS5882560A JPS5882560A JP56179653A JP17965381A JPS5882560A JP S5882560 A JPS5882560 A JP S5882560A JP 56179653 A JP56179653 A JP 56179653A JP 17965381 A JP17965381 A JP 17965381A JP S5882560 A JPS5882560 A JP S5882560A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- potential level
- internal circuit
- control element
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
この発明は０ＭＯ８で構成された集積回路（以下ＣＭＯ
８Ｉ−Ｃという）に係り、特にラッチアップを防止した
０ＭＯ８Ｉ・Ｃに関する。DETAILED DESCRIPTION OF THE INVENTION This invention is an integrated circuit (hereinafter referred to as CMO) configured with 0MO8.
8I-C), and particularly relates to 0MO8I-C that prevents latch-up.
０ＭＯ８Ｉ・Ｃの動作は通常１電源で行うのが普通であ
るが、２電源を必要とする場合もある。その際、電源の
投入順序を誤まると前記電源からＣＭＯ８Ｉ−Ｃの構造
に起因する過電流が流れ出す、いわゆるラッチアップ現
象が発生することがある。The operation of 0MO8I/C is normally performed with one power supply, but there are cases where two power supplies are required. At this time, if the order of turning on the power is incorrect, a so-called latch-up phenomenon may occur in which an overcurrent due to the structure of the CMO8I-C flows from the power supply.
第１図は、０ＭＯ８Ｉ−Ｃのラッチアップ現象を説明す
るための図であって、Ｎ型サブストレート上に形成され
た０ＭＯ８）ランジスタの断面構造及び相互接続を示し
たものである。FIG. 1 is a diagram for explaining the latch-up phenomenon of 0MO8I-C, and shows the cross-sectional structure and interconnection of an 0MO8) transistor formed on an N-type substrate.
１は低い電位レベルを有する電源端子で、例えば５〜６
ｖの電源が、２は高い電位レベルを有する電源端子で、
例えば１Ｏ−７−１２Ｖの電源が接続されている。３は
共通電源端子であって通常は接地されている。４．５は
それぞれＰチャネル、ＮチャネルＭＯ８）ランジスタで
ある。ＰチャネルＭＯＳトランジスタ４のソース６は電
源端子１に接続され、ＮチャネルＭＯ８）ランジスタ５
のソース７及びＰウェル層８は相互接続されて共通電源
端子３に接続されている。1 is a power supply terminal with a low potential level, for example 5 to 6
2 is a power supply terminal with a high potential level,
For example, a 1O-7-12V power supply is connected. 3 is a common power supply terminal, which is normally grounded. 4.5 are P-channel and N-channel MO8) transistors, respectively. The source 6 of the P-channel MOS transistor 4 is connected to the power supply terminal 1, and the source 6 of the P-channel MOS transistor 4 is connected to the power supply terminal 1.
The source 7 and the P-well layer 8 are interconnected and connected to the common power supply terminal 3.
さて、このような接続をされた０ＭＯ８Ｉ−Ｃにおいて
、電源端子１のみに低い電位レベルを有する電源が接続
され、電源端子２には、まだ高い電位レベルを有する電
源が接続されていない状態を考える。Now, consider a situation in which a power supply having a low potential level is connected to only power supply terminal 1 of the 0MO8I-C connected in this way, and a power supply having a high potential level is not yet connected to power supply terminal 2. .
ＰチャネルＭＯ８）ランジスタ４のソース６のサブスト
レート９、Ｐウェル層８およびＮチャネルＭＯ８）ラン
ジスタ５のソース７によってＰＮＰＮ サイリスタが構
成されておシ、そのアノードとＮゲート間が順方向バイ
アスされ、Ｐゲートとカソードが接続された形になって
いる。従がって、高い電位レベルを有する電源が電源端
子２に接続された瞬間、上記のＰＮＰＮサイリスタが駆
動されて、電源端子１及び２から共通電源端子３に向か
う過電流が生じ、いわゆるラッチアップ現象が起こる。A PNPN thyristor is configured by the substrate 9 of the source 6 of the P-channel MO8) transistor 4, the P well layer 8, and the source 7 of the N-channel MO8) transistor 5, and its anode and N gate are forward biased, The P gate and cathode are connected. Therefore, the moment a power supply with a high potential level is connected to power supply terminal 2, the above-mentioned PNPN thyristor is driven, and an overcurrent flows from power supply terminals 1 and 2 to common power supply terminal 3, resulting in so-called latch-up. A phenomenon occurs.
一方逆に電源端子２のみに高い電位レベルを有する電源
が接続され、電源端子２には、まだ低い電位レベルを有
する電源が接続されていない状態では、上記ＰＮＰＮサ
イリスタのアノードとＮゲート間は逆ノ４イアスされて
いるので、低い電位レベルを有する電源が電源端子１に
接続されてもＰＮＰＮサイリスタは駆動されないので、
ラッチアップ現象は起こらない。On the other hand, when a power source with a high potential level is connected only to power terminal 2, and a power source with a low potential level is not yet connected to power terminal 2, the anode and N gate of the PNPN thyristor are reversed. 4, so even if a power supply with a low potential level is connected to power supply terminal 1, the PNPN thyristor will not be driven.
No latch-up phenomenon occurs.
従がって、このような従来の０ＭＯ８Ｉ−Ｃでは電源の
投入順序において、電位レベルの低い電源を電位レベル
の高い電源よシも先に印加してはならないという制約が
あった。Therefore, in such a conventional 0MO8I-C, there is a restriction in the order in which power is applied that a power source with a lower potential level must not be applied before a power source with a higher potential level.
この発明の目的は、電源投入順序に制約を設けなくても
ラッチアップ現象を引き起こすことのない０ＭＯ８ｉ−
ｃ を提供するにある。An object of the present invention is to provide an 0MO8i-
c.
この目的を達成するためにこの発明においては、高い電
位レベルを有する第１の電源と、低い電位レベルを有す
る第２の電源とが印加されて動作する内部回路を有して
なるＣＭＯ８集積回路において、前記第２の電源と前記
内部回路との間に介在し、前記第１の電源が印加された
場合に限シ前記第２の電源を前記内部回路に接続させる
制御素子を設ける事を特甲としている。In order to achieve this object, the present invention provides a CMO8 integrated circuit having an internal circuit that operates when a first power source having a high potential level and a second power source having a low potential level are applied. , a control element is provided between the second power source and the internal circuit, and connects the second power source to the internal circuit only when the first power source is applied. It is said that
以下、この発明実施例を第２図、第３図に基づいて詳細
に説明する。なお、図面中の符号に関しては、第１図と
同一部分は同一符号を付しである。Embodiments of this invention will be described in detail below with reference to FIGS. 2 and 3. Regarding the reference numerals in the drawings, the same parts as in FIG. 1 are given the same reference numerals.
第２図は、この発明の第１の実施例を示す回路図であっ
て、ＰチャネルＭＯ８）ランジスタ４、ＮチャネルＭＯ
８）ランジスタ５を複数組合わせる事によシ内部回路を
構成している。１０はこの発明によっ、て付加された制
御素子であって、本実施例では単一のＮチャネルＭＯ８
）ランジスタを使用している。制御素子１０は内部回路
と一体に同一サブストレート上に集積化出来る。制御素
子１０は低い電位レベルを有する電源端子１と内部回路
との間に接続されており、その制御端子１１によって高
い電位レベルを有する電源が印加されたか否かを検出し
、この信号に応答して制御素子１０を動作させ、低い電
位レベルを有する電源が内部回路に印加されるよう動作
する。本実施例では制御端子１１が直接電源端子２に接
続されている。電源端子１と内部回路とは制御素子１０
を介して接続されているが、制御端子１１に高い電位レ
ベルを、有する電源が印加されない限シ、制御素子１０
は動作しないので、内部回路を動作させるべき低い電位
レベルを有する電源は内部回路には印加されない。なお
制御端子１１と共通電源端子３との間に接続された抵抗
１２は、電源端子２に高い電位レベルを有する電源が印
加されていない状態で、制御素子１０を確実に非導通の
状態に保つために設けられている。FIG. 2 is a circuit diagram showing a first embodiment of the present invention, in which P-channel MO8) transistor 4, N-channel MO
8) An internal circuit is constructed by combining a plurality of transistors 5. 10 is a control element added according to the present invention, and in this embodiment, a single N-channel MO8
) uses a transistor. The control element 10 can be integrated on the same substrate with the internal circuitry. The control element 10 is connected between the power supply terminal 1 having a low potential level and the internal circuit, detects whether a power supply having a high potential level is applied through the control terminal 11, and responds to this signal. The control element 10 is operated so that a power supply having a low potential level is applied to the internal circuit. In this embodiment, the control terminal 11 is directly connected to the power supply terminal 2. The power supply terminal 1 and the internal circuit are the control element 10
However, unless a power source having a high potential level is applied to the control terminal 11, the control element 10
does not operate, so a power supply having a low potential level that should operate the internal circuit is not applied to the internal circuit. Note that the resistor 12 connected between the control terminal 11 and the common power supply terminal 3 reliably keeps the control element 10 in a non-conductive state when no power having a high potential level is applied to the power supply terminal 2. It is provided for.
本実施例では制御素子１０に単一のＮチャネルＭＯ８）
ランジスタを使用したので簡単な構成で実現出来るとい
う利点がある。制御素子１０は、本実施例のような単一
構造に限定されることなく複数のＭＯＳ ）ランジスタ
を組合せて構成出来ることはいうまでもない。また制御
端子１１の接続位置も、直接高い電位レベルを有する電
源端子２に限定されるものではなく、高い電位レベルを
検出用−来る位置であれば良い。In this embodiment, the control element 10 includes a single N-channel MO8)
Since transistors are used, there is an advantage that it can be realized with a simple configuration. It goes without saying that the control element 10 is not limited to a single structure as in this embodiment, but can be constructed by combining a plurality of MOS transistors. Further, the connection position of the control terminal 11 is not limited to the power supply terminal 2 which directly has a high potential level, but may be any position where a high potential level is detected.
第３図は、この発明の第２の実施例を示す回路図である
。１１は内部回路に印加される入力信号の１つであって
、このような入力信号１１も、低い電位レベルを有する
電源とみなせる場合には、内部回路の静電破壊を防止す
る保護ダイオード１２のアノードと電源端子１との間に
制御素子１０を介在させれば、第１の実施例と同様な効
果〜が期待出来る。FIG. 3 is a circuit diagram showing a second embodiment of the invention. 11 is one of the input signals applied to the internal circuit, and if such input signal 11 can also be considered as a power source with a low potential level, a protection diode 12 is applied to prevent electrostatic damage to the internal circuit. If the control element 10 is interposed between the anode and the power supply terminal 1, the same effects as in the first embodiment can be expected.
即ち、第３図に示した回路においては、保護ダイオード
１２が順方向にバイアスされないようにすれば良いから
である。That is, in the circuit shown in FIG. 3, it is sufficient to prevent the protection diode 12 from being forward biased.
なお、第２の実施例においても、制御素子１０の構成に
関しては第１の実施例の場合と同様である。Note that in the second embodiment, the configuration of the control element 10 is the same as in the first embodiment.
以上、詳細に説明したように、この発明においては、ス
イッチ機能を有する制御素子を低い電位レベルを有する
電源と内部回路との間に介在させ、この制御素子の導通
、非導通を高い電位レベルを有する電源によって制御す
るようにしたので、電源又は入力信号の投入順序を制約
する必要がなくなるという利点を有する。As explained above in detail, in the present invention, a control element having a switching function is interposed between a power supply having a low potential level and an internal circuit, and conduction/non-conduction of this control element is controlled by a high potential level. Since the control is performed using the power supply, there is no need to restrict the order in which the power supply or input signals are turned on.
第１図は、０ＭＯ８Ｉ−Ｃのラッチアップ現象を説明す
るための図、第２図は、この発明の第１の実施例を示す
回路図、第３図は第２の実施例を示す回路図である。
１．２・・電源端子、１０・・・制御素子。Fig. 1 is a diagram for explaining the latch-up phenomenon of 0MO8I-C, Fig. 2 is a circuit diagram showing the first embodiment of the present invention, and Fig. 3 is a circuit diagram showing the second embodiment. It is. 1.2...Power terminal, 10...Control element.
Claims (1)
レベルを有する第２の電源とが印加されて動作する内部
回路を有してなるＣＭＯ８集積回路において、前記第２
の電源と前記内部回路との間に介在し、前記第１の電源
が印加された場合に限り、前記第２の電源を前記内部回
路に接続させる制御素子を具備してなるＣＭＯ８集積回
路。 （２、特許請求の範囲第（１）項記載のＣＭＯ８集積回
路において、前記第２の電源が前記内部回路への入力信
号の１つであるＣＭＯ８集積回路。 （３）特許請求の範囲第（１）項又は第（２）項記載の
ＣＭＯ８集積回路において、前記制御素子は前記内部回
路と一体に集積化されたＮチャネルトランジスタである
ＣＭＯ８集積回路。[Scope of Claims] (1) In a CMO8 integrated circuit having an internal circuit that operates when a first power source having a high potential level and a second power source having a low potential level are applied, 2
A CMO8 integrated circuit comprising a control element interposed between a power source and the internal circuit, and connecting the second power source to the internal circuit only when the first power source is applied. (2. The CMO8 integrated circuit according to claim (1), wherein the second power supply is one of the input signals to the internal circuit. (3) Claim (1) The CMO8 integrated circuit according to item 1) or item (2), wherein the control element is an N-channel transistor integrated with the internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56179653A JPS5882560A (en) | 1981-11-11 | 1981-11-11 | Cmos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56179653A JPS5882560A (en) | 1981-11-11 | 1981-11-11 | Cmos integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5882560A true JPS5882560A (en) | 1983-05-18 |
| JPH0118587B2 JPH0118587B2 (en) | 1989-04-06 |
Family
ID=16069531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56179653A Granted JPS5882560A (en) | 1981-11-11 | 1981-11-11 | Cmos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5882560A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4571505A (en) * | 1983-11-16 | 1986-02-18 | Inmos Corporation | Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits |
| US4837460A (en) * | 1983-02-21 | 1989-06-06 | Kabushiki Kaisha Toshiba | Complementary MOS circuit having decreased parasitic capacitance |
| JPH01220470A (en) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | Complementary semiconductor integrated circuit device |
| JP2014027279A (en) * | 2012-07-27 | 2014-02-06 | Freescale Semiconductor Inc | Single-event latch-up prevention technique for semiconductor device |
-
1981
- 1981-11-11 JP JP56179653A patent/JPS5882560A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4837460A (en) * | 1983-02-21 | 1989-06-06 | Kabushiki Kaisha Toshiba | Complementary MOS circuit having decreased parasitic capacitance |
| US4571505A (en) * | 1983-11-16 | 1986-02-18 | Inmos Corporation | Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits |
| JPH01220470A (en) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | Complementary semiconductor integrated circuit device |
| JP2014027279A (en) * | 2012-07-27 | 2014-02-06 | Freescale Semiconductor Inc | Single-event latch-up prevention technique for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0118587B2 (en) | 1989-04-06 |
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