JPS59110122A - Semiconductor integrated circuit device having nitride film - Google Patents
Semiconductor integrated circuit device having nitride filmInfo
- Publication number
- JPS59110122A JPS59110122A JP57219760A JP21976082A JPS59110122A JP S59110122 A JPS59110122 A JP S59110122A JP 57219760 A JP57219760 A JP 57219760A JP 21976082 A JP21976082 A JP 21976082A JP S59110122 A JPS59110122 A JP S59110122A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- nitride film
- integrated circuit
- thermal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 6
- 239000002253 acid Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000035699 permeability Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- NOSVTINSKLIVGN-UHFFFAOYSA-N [Si]=O.[As] Chemical compound [Si]=O.[As] NOSVTINSKLIVGN-UHFFFAOYSA-N 0.000 description 1
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 温特性を向上させた半導体集積回路装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device with improved thermal characteristics.
一般にトランジスタ、ダイオード、半導体抵抗およヒコ
ンデンサ等の半導体素子並びにこれらの素子間を相互配
線し、さらにリード引出端子を設けてなる半導体集積回
路装置は、一般に外界からの水分、導電性物質およびイ
オン性物質などの影響を受は特性が劣化することが知ら
れている。そのため、その表面特に特性に影響のある活
性領域並ひにその近傍をシリコン酸(ヒ膜等の保護膜で
包囲する方、法が行なわれている。しかし一層では不十
分であることが明らかになり2重又は多重保護が行なわ
れるようになった。Semiconductor integrated circuit devices, which generally consist of semiconductor elements such as transistors, diodes, semiconductor resistors, and capacitors, interconnected wiring between these elements, and lead extraction terminals, are generally susceptible to moisture, conductive substances, and ions from the outside world. It is known that properties deteriorate when affected by chemical substances. For this reason, methods are being used to surround the surface, particularly the active region that affects its characteristics, and the vicinity thereof with a protective film such as silicone acid (arsenic film). However, it has become clear that one layer is not sufficient. This led to double or multiple protection.
一例としてシリコン酸化膜とシリコン窒化膜の2重保護
膜では内側の保護膜のシリコン酸化膜を外側の保護膜の
シリコン窒化膜で覆いシリコンとの良好な特性保持をシ
リコン酸化膜で、外部からの水分等の不純物の侵入をシ
リコン窒化膜で防ぐ構造が採用されている。その他リン
ガラス(PSG)も用いられるが、PSGは一般に吸湿
性が大きいことやケミカルエツチングされ易い等の性質
があるので酸化シリコン(SiC+z )上にP、SG
を形成、さらに5iU2で被覆するという3重構造、
・しかも完全に上層の5iOzで密閉する方法が提案さ
れている。For example, in a double protective film of silicon oxide film and silicon nitride film, the inner protective film silicon oxide film is covered with the outer protective film silicon nitride film, and the silicon oxide film maintains good characteristics with silicon. The structure uses a silicon nitride film to prevent impurities such as moisture from entering. Phosphorus glass (PSG) is also used, but since PSG generally has properties such as high hygroscopicity and easy chemical etching, P and SG are used on silicon oxide (SiC+z).
A triple structure of forming and further covering with 5iU2,
・Moreover, a method has been proposed in which the upper layer is completely sealed with 5iOz.
シリコン窒〔ヒ膜は水分やアルカリイオン等の遮蔽性が
極めてよいので拡散層最上層の保護膜として多用されて
おり拡散層の保護の場合前記(7たように5iUzも完
全に覆う、すなわちシリコン窒化膜の端部を直接シリコ
ンに接する構造が多く用いられたが、このような構造で
はシリコン窒fヒ膜の開口にあたり、シリコン基板に損
傷を与えるという問題があり、特に拡散の浅い、又は微
細パターンの高密度集積回路装置では好ましくない問題
である。又この場合の保護は拡散層のみの保護しか考え
ておらず配線部は保護されない構造となっている為、拡
散層が保護されたとしても、配線部が損傷してしまい半
導体装置の機能をはださなくなってしまう。−又配線の
保護の目的でシリコン窒化膜を配線層上部に被着しても
第1図のような構造となることが多い。第1図は従来の
半導体集積回路の配線構造を示す断面図である。図にお
いて、1は半導体基板であり、その上には熱酸比5iQ
2酸化膜2の開口部を通してシリコン基板に形成した累
子領域に接続している。4は第1のAl配線3上に形成
した層間絶縁膜としてのCVD5i(,12である。ま
た5は層間絶縁膜4の開口部を通じ第1Al配線3に接
続し層間絶縁膜4上に形成した第2のAl配線である。Silicon nitride film has extremely good shielding properties against moisture and alkali ions, so it is often used as a protective film for the uppermost layer of the diffusion layer. A structure in which the edge of the nitride film is in direct contact with silicon has often been used, but this structure has the problem of damaging the silicon substrate due to the opening in the silicon nitride film, especially when the diffusion is shallow or fine. This is an undesirable problem in high-density integrated circuit devices with patterns.In addition, the protection in this case is only concerned with protecting the diffusion layer, and the wiring section is not protected, so even if the diffusion layer is protected, , the wiring section will be damaged and the semiconductor device will no longer function properly.Also, even if a silicon nitride film is coated on top of the wiring layer for the purpose of protecting the wiring, the structure as shown in Figure 1 will result. Figure 1 is a cross-sectional view showing the wiring structure of a conventional semiconductor integrated circuit.
It is connected to the resistor region formed on the silicon substrate through the opening of the dioxide film 2. 4 is a CVD5i (, 12) as an interlayer insulating film formed on the first Al wiring 3; 5 is a CVD 5i (, 12) formed on the interlayer insulating film 4 connected to the first Al wiring 3 through the opening of the interlayer insulating film 4; This is the second Al wiring.
また6は第2のAl配線のパッド部8を除く表面に形成
したC V D S iOzであpl 7は最上層の保
護膜であるシリコン窒化膜である。Further, 6 is C V D SiOz formed on the surface of the second Al wiring except for the pad portion 8, and pl 7 is a silicon nitride film which is the uppermost protective film.
第1図よりわかる通り第2のAl配線のパッド部8の外
側は前記した理由もあり熱酸化膜2.眉間絶縁膜のCV
L)Si024、Al配線保護用のCVD5i026.
プラズマシリコン窒化膜7が重なっているが側面には
各層の端部が露出している。As can be seen from FIG. 1, the outside of the pad portion 8 of the second Al wiring is covered with a thermal oxide film 2. CV of glabellar insulating film
L) Si024, CVD5i026 for Al wiring protection.
Although the plasma silicon nitride films 7 overlap, the ends of each layer are exposed on the side surfaces.
しかしCVDSiO2膜4および6の層は何れもAl配
線形成後の付着であるため高温酸化は採用することがで
きず、止むなく500℃以下の低温のCVDで形成され
る。従って形成されたS iOzは高温熱酸化膜に比べ
質も緻密でなく特に吸水性、透湿性が大きい。そのため
水分はこの層の側面から9の経路を通って容易にAl配
線のパッド部に到達しAl配線、特にパッド部を劣化さ
せ、半導体集積回路装置の信頼性を大幅に低下させる結
果となっている。However, since both the CVDSiO2 films 4 and 6 are deposited after the Al wiring is formed, high-temperature oxidation cannot be used, and they are inevitably formed by CVD at a low temperature of 500° C. or less. Therefore, the formed SiOz is less dense than a high-temperature thermal oxide film and has particularly high water absorption and moisture permeability. Therefore, moisture easily reaches the pad portion of the Al wiring through the path 9 from the side of this layer, deteriorating the Al wiring, especially the pad portion, and significantly reducing the reliability of the semiconductor integrated circuit device. There is.
本発明の目的は上記問題点に対処してなされたもので、
耐水性がすぐれ、信頼性の犬なる半導体集積回路装置を
提供するにある。The purpose of the present invention is to address the above-mentioned problems.
It is an object of the present invention to provide a highly reliable semiconductor integrated circuit device with excellent water resistance.
本発明は、半導体基板の主表面に熱酸化膜が設けられ、
該熱緻化映上に前記熱酸化膜よシ耐湿性の低い被膜が設
けられ、該被膜上に窒化膜が設けられた半導体集積回路
装置において、前記被膜は前記窒化膜で俊われておシ、
かつ前記窒化膜端部以下実施例に基き本発明の詳細な説
明
第2図は本発明の一実施例による半導体集積回路装置の
要部断面図である。図において1〜8は第1図と同じ部
分をあらわす。第2図の第1図とことなる主要点は、第
1層のhl配線3上にCVIJ法により形成された層間
絶縁膜としての8 i0z膜4は周辺部で除去され、ま
た第2のAl配線5の上に形成されたCVDSiQ2膜
6は、層間絶縁膜4の端部を覆い熱酸1ヒ膜2の上に達
し、さきにエツチング除去した層間絶縁膜4に準じて、
パッドの外側周辺部が除去されて熱酸化により形成した
8iUz2の外囲部が露出されている。然るのちhll
バッド部を除く全表面にプラズマシリコン窒化膜7が形
成され、シリコン窒化膜はCVDSi02膜が除去され
露出している熱酸〔ヒ8iQ2膜2に接している。In the present invention, a thermal oxide film is provided on the main surface of a semiconductor substrate,
In a semiconductor integrated circuit device in which a film having lower moisture resistance than the thermal oxide film is provided on the thermally densified film, and a nitride film is provided on the film, the film is densified by the nitride film. ,
Detailed explanation of the present invention based on an embodiment of the nitride film end portion FIG. 2 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 1 to 8 represent the same parts as in FIG. The main points in FIG. 2 that are different from FIG. The CVDSiQ2 film 6 formed on the wiring 5 covers the end of the interlayer insulating film 4 and reaches above the thermally oxidized arsenic film 2, similar to the interlayer insulating film 4 that was etched away earlier.
The outer periphery of the pad has been removed to expose the 8iUz2 envelope formed by thermal oxidation. After that hll
A plasma silicon nitride film 7 is formed on the entire surface except for the pad portion, and the silicon nitride film is in contact with the thermally oxidized [H8iQ2 film 2] exposed after the CVDSi02 film has been removed.
すなわち、本実施例によれば半導体集積回路装置の上表
面は吸水性、透水性が極めて小さく、かつ不純物も通し
にぐいプラズマシリコン窒化膜でパッド部以外が覆われ
、その窒化膜は熱酸化により形成した緻密質で吸水性、
透水性の小さいシリコン酸化膜に接している。またプラ
ズマシリコン窒化膜の段差部等の被覆性は非常によいの
で、シリコン窒叱膜、熱酸比シリコン酸化膜、およびそ
の接触部を通じての水分等の侵入は殆んどない。That is, according to this embodiment, the upper surface of the semiconductor integrated circuit device is covered except for the pad portion with a plasma silicon nitride film that has extremely low water absorption and water permeability and is impermeable to impurities, and the nitride film is coated by thermal oxidation. Formed dense and water absorbent,
It is in contact with a silicon oxide film that has low water permeability. Furthermore, since the plasma silicon nitride film has very good coverage of stepped portions, etc., there is almost no intrusion of moisture or the like through the silicon nitride film, the thermal oxidation silicon oxide film, and the contact portions thereof.
また第2のhlJ配線のシリコン窒出膜被覆はAlへの
直接付着でな(CVDによるシリコン酸rヒ膜を介して
いるのでAg配線に損傷を与えることなく、かつ密着性
も良好となり、この部分からの水分の侵入は起りにくい
。また窒化シリコン膜は直接シリコン基板に接していな
いため窒出膜除去に際して生ずるシリコン表面の損傷問
題も防ぐことができる。In addition, the silicon nitride film coating on the second hlJ wiring is not directly attached to Al (it is coated with a silicon oxide arsenic film by CVD, so it does not damage the Ag wiring and has good adhesion. Intrusion of moisture from these parts is unlikely to occur.Furthermore, since the silicon nitride film is not in direct contact with the silicon substrate, damage to the silicon surface that occurs when removing the nitride film can be prevented.
例のものは500〜100OHで始めて同様結果となり
数倍の4命改良が認められた。In the case of the example, the results were similar when starting with 500 to 100 OH, and a several-fold improvement in 4 lives was observed.
以上説明したとおり、本発明によれば半導体集積回路装
置の特性を落とすことなく、耐湿特性を向上させること
ができ、信頼性を大幅に向上させることかできる。As described above, according to the present invention, the moisture resistance can be improved without deteriorating the characteristics of a semiconductor integrated circuit device, and the reliability can be significantly improved.
第1図は従来の半導体集積回路装置の要部断面図、第2
図は本発明の一実施例による半導体集積回路装置の要部
断面図である。
1・・・・・・シリコン半導体基板、2・・・・・・熱
酸比シリコン酸比膜、3・・・・・・第1層hl配線、
4,6・・・・・・CVDによるシリコン酸比膜、5・
・・・・・第2層のAg配線、7・・・・・・プラズマ
・シリコン窒出膜、8・・・・・・パッド部、9・・・
・・・水分侵入経路。Figure 1 is a sectional view of the main parts of a conventional semiconductor integrated circuit device;
The figure is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention. 1...Silicon semiconductor substrate, 2...Thermal acid ratio silicon acid ratio film, 3...First layer hl wiring,
4,6... Silicon acid ratio film by CVD, 5.
...Second layer Ag wiring, 7...Plasma silicon nitride film, 8...Pad portion, 9...
...Water intrusion route.
Claims (1)
上に前記熱酸化膜より耐湿性の低い被膜が設けられ、該
被膜上に窒化膜が設けられた半導体集積回路装置におい
て、前記被膜は前記窒化膜で覆われておシ、かつ前記窒
化膜端部は前記熱酸化膜に接していることを特徴とする
窒化膜を有する半導体集積回路装置。In a semiconductor integrated circuit device, a thermal oxide film is provided on the main surface of a semiconductor substrate, a film having lower moisture resistance than the thermal oxide film is provided on the oxide film, and a nitride film is provided on the film, A semiconductor integrated circuit device having a nitride film, wherein a film is covered with the nitride film, and an end portion of the nitride film is in contact with the thermal oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57219760A JPS59110122A (en) | 1982-12-15 | 1982-12-15 | Semiconductor integrated circuit device having nitride film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57219760A JPS59110122A (en) | 1982-12-15 | 1982-12-15 | Semiconductor integrated circuit device having nitride film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59110122A true JPS59110122A (en) | 1984-06-26 |
Family
ID=16740567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57219760A Pending JPS59110122A (en) | 1982-12-15 | 1982-12-15 | Semiconductor integrated circuit device having nitride film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59110122A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01105547A (en) * | 1987-10-19 | 1989-04-24 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| JPH03126228A (en) * | 1989-10-12 | 1991-05-29 | Nec Corp | Method for manufacturing semiconductor integrated circuit device |
| US5065222A (en) * | 1987-11-11 | 1991-11-12 | Seiko Instruments Inc. | Semiconductor device having two-layered passivation film |
| US5070386A (en) * | 1989-08-09 | 1991-12-03 | Seiko Instruments Inc. | Passivation layer structure with through-holes for semiconductor device |
| US5072263A (en) * | 1986-09-19 | 1991-12-10 | Kabushiki Kaisha Komatsu Seisakusho | Thin film el device with protective film |
| US5471084A (en) * | 1991-12-03 | 1995-11-28 | Nippondenso Co., Ltd. | Magnetoresistive element and manufacturing method therefor |
| US5523595A (en) * | 1990-08-21 | 1996-06-04 | Ramtron International Corporation | Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film |
| US5742094A (en) * | 1993-01-25 | 1998-04-21 | Intel Corporation | Sealed semiconductor chip |
| US6169304B1 (en) | 1993-08-05 | 2001-01-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer |
| US9092582B2 (en) | 2010-07-09 | 2015-07-28 | Cypress Semiconductor Corporation | Low power, low pin count interface for an RFID transponder |
| US9846664B2 (en) | 2010-07-09 | 2017-12-19 | Cypress Semiconductor Corporation | RFID interface and interrupt |
-
1982
- 1982-12-15 JP JP57219760A patent/JPS59110122A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5072263A (en) * | 1986-09-19 | 1991-12-10 | Kabushiki Kaisha Komatsu Seisakusho | Thin film el device with protective film |
| JPH01105547A (en) * | 1987-10-19 | 1989-04-24 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| US5065222A (en) * | 1987-11-11 | 1991-11-12 | Seiko Instruments Inc. | Semiconductor device having two-layered passivation film |
| US5070386A (en) * | 1989-08-09 | 1991-12-03 | Seiko Instruments Inc. | Passivation layer structure with through-holes for semiconductor device |
| JPH03126228A (en) * | 1989-10-12 | 1991-05-29 | Nec Corp | Method for manufacturing semiconductor integrated circuit device |
| US5523595A (en) * | 1990-08-21 | 1996-06-04 | Ramtron International Corporation | Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film |
| US5471084A (en) * | 1991-12-03 | 1995-11-28 | Nippondenso Co., Ltd. | Magnetoresistive element and manufacturing method therefor |
| US5742094A (en) * | 1993-01-25 | 1998-04-21 | Intel Corporation | Sealed semiconductor chip |
| US5856705A (en) * | 1993-01-25 | 1999-01-05 | Intel Corporation | Sealed semiconductor chip and process for fabricating sealed semiconductor chip |
| US6169304B1 (en) | 1993-08-05 | 2001-01-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer |
| US9092582B2 (en) | 2010-07-09 | 2015-07-28 | Cypress Semiconductor Corporation | Low power, low pin count interface for an RFID transponder |
| US9846664B2 (en) | 2010-07-09 | 2017-12-19 | Cypress Semiconductor Corporation | RFID interface and interrupt |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4472730A (en) | Semiconductor device having an improved moisture resistance | |
| US4097889A (en) | Combination glass/low temperature deposited Siw Nx Hy O.sub.z | |
| GB2083283A (en) | Resin molded type semiconductor device | |
| JPS59110122A (en) | Semiconductor integrated circuit device having nitride film | |
| US20170301623A1 (en) | Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit | |
| US7002256B1 (en) | Semiconductor device having wiring patterns and dummy patterns covered with insulating layer | |
| EP0529717A2 (en) | Method of manufacturing a semiconductor device having overlapping contacts | |
| GB1559512A (en) | Semi-conductor devices | |
| JPS6156608B2 (en) | ||
| JPH05218015A (en) | Semiconductor device | |
| JPS59232424A (en) | Semiconductor device and manufacture of the same | |
| JPS63116458A (en) | Semiconductor device with photosenser and signal processing circuit | |
| JP2723559B2 (en) | Semiconductor integrated circuit device | |
| JPH05234991A (en) | Semiconductor device | |
| JPH0555199A (en) | Semiconductor device | |
| US4824801A (en) | Method of manufacturing aluminum bonding pad with PSG coating | |
| JPS6340333A (en) | Semiconductor device | |
| JP3413653B2 (en) | Semiconductor device | |
| JPS6057635A (en) | Semiconductor device | |
| JPS60145628A (en) | Semiconductor device | |
| JPH0620067B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6133060A (en) | Method of protecting light sensitive regions of integrated circuits | |
| JPS6356704B2 (en) | ||
| JPH02116132A (en) | Protective film for wiring of integrated circuit | |
| JPS6127177Y2 (en) |