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JPS59112643A - Complementary MOS semiconductor integrated circuit device - Google Patents

Complementary MOS semiconductor integrated circuit device

Info

Publication number
JPS59112643A
JPS59112643A JP58184986A JP18498683A JPS59112643A JP S59112643 A JPS59112643 A JP S59112643A JP 58184986 A JP58184986 A JP 58184986A JP 18498683 A JP18498683 A JP 18498683A JP S59112643 A JPS59112643 A JP S59112643A
Authority
JP
Japan
Prior art keywords
film
high resistance
layer
type
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58184986A
Other languages
Japanese (ja)
Other versions
JPH0248142B2 (en
Inventor
Kotaro Nishimura
光太郎 西村
Norimasa Yasui
安井　徳政
Satoshi Meguro
目黒　怜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58184986A priority Critical patent/JPS59112643A/en
Publication of JPS59112643A publication Critical patent/JPS59112643A/en
Publication of JPH0248142B2 publication Critical patent/JPH0248142B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a high resistance element in a CM1SIC without adding any new step by merely altering part of a mask pattern. CONSTITUTION:A p<-> type well is formed in an n<-> type layer on an n<--> type Si substrate, and an Si3N4 film 7 on an oxidized film 6 is selectively removed by a resist mask 8. With CVD oxidized films 9, 10 as masks B and P ions are sequentially implanted, the film 7 is selectively oxidized at 11 to form a p type layer 11 and an n type layer 13, and the films 7, 6 are removed. Then, a polysilicon layer 16 is selectively formed on a gate oxidized film 15 and conducted. Subsequently. CVD oxidized film masks 17, 18 are sequentially covered, and B and P ions are implanted to form an n<+> type layer 18 and a p<+> type layer 20. At this time the part 21 of the polysilicon layer 16 is not ion implanted, a high resistance layer is formed, and both terminals are connected to the n<+> type layer. According to this configuration, the diffusing masks are positively used to form the polysilicon region in which impurities of both types are not doped and to utilize it for a high resistance element.

Description

【発明の詳細な説明】 この発明は相補型ＭＱ８半導体装置（以下ＣＭＯ８と略
称する）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MQ8 semiconductor device (hereinafter abbreviated as CMO8).

従来のＣＭＱＳ製造法では、一つの半導体基板上にｐチ
ャネル及びｎチャネルのソース・ドレイン領域をそれぞ
れ形成するためにｐ型拡散用マスクとｎ型拡散用のマス
クを交互に使用して、互いに異なる領域へのドープ時に
ｋＸＣＶＤ法（気相化学析出法）による５ｔｏ２（二酸
化シリコン）膜の上記マスクな被着することで異なる不
純物が他の領域の半導体基板にドープされるのを防止す
る方法がとられている。この方法によればポリシリコン
・ゲートと共に形成した他のポリシリコン配線は、ソー
ス・ドレイン部拡散と同時に不純物ドープが行なわれる
ため不純物が高濃度にドープされ、低抵抗の導体部とし
て利用される。ところで、ＭＱＳＩＣにおいては回路構
成の一部として高抵抗素子を必要とする場合、この高抵
抗素子のために従来は不純物ドープのないポリシリコン
形成工程を別に用意するため工程数が増加することにな
った。In the conventional CMQS manufacturing method, in order to form p-channel and n-channel source/drain regions on one semiconductor substrate, p-type diffusion masks and n-type diffusion masks are alternately used, and different A method of preventing different impurities from being doped into the semiconductor substrate in other regions is to deposit a 5to2 (silicon dioxide) film using the above-mentioned mask using the kXCVD method (vapor phase chemical deposition method) when doping the region. It is being According to this method, the other polysilicon wiring formed together with the polysilicon gate is doped with impurities at the same time as the source/drain region diffusion, so that it is doped with impurities at a high concentration and is used as a low-resistance conductor. By the way, in MQSIC, when a high resistance element is required as part of the circuit configuration, conventionally, a separate polysilicon formation process without impurity doping is required for this high resistance element, which increases the number of steps. Ta.

本発明においては前記ｐ型及びｎ型拡散用のマスクを積
極的に利用し、どちらの不純物もドープされないポリシ
リコン領域をつくり、それを高抵抗素子として利用しよ
うとするものである。The present invention actively utilizes the masks for p-type and n-type diffusion to create a polysilicon region that is not doped with either impurity, and uses it as a high-resistance element.

したがって、本発明の目的はＣＭＯ８’ＩＣに適合した
スタティック・ランダム・アクセス・メモＩＪ（ＳＲＡ
Ｍと略称）を提供することにある。Therefore, an object of the present invention is to develop a static random access memory IJ (SRA) compatible with CMO8'IC.
(abbreviated as M).

上記目的を達成するために、本発明は周辺ＣＭＱＳのメ
モリ・セルＮＭＯ８構成のＳ　ＲＡＭにおいて、メモリ
セルの負荷である高抵抗ポＩＪ　Ｓ　ｉの両端をＮ型に
ハイトープされたポリシリコン配線にて構成したもので
ある。In order to achieve the above object, the present invention provides an SRAM with a peripheral CMQS memory cell NMO8 configuration, in which both ends of a high resistance point IJSi, which is a load of a memory cell, are connected to an N-type high-topped polysilicon wiring. It is composed of

以下、本発明を実施例にそって具体的に説明する。The present invention will be specifically described below with reference to Examples.

第１図（ａ）〜（ｊ）はｎ型Ｓｉ基板上にｐチャネルＭ
ＱＳＦＥＴとｎチャネルＭＱｓＦＥＴを形成し、一部に
高抵抗回路を有するＣＭＱＳＩＣ５例えばメモリセルの
製造に本発明を適用した場合の工程図を示す。Figures 1(a) to (j) show a p-channel M on an n-type Si substrate.
A process diagram is shown in which the present invention is applied to the manufacture of a CMQSIC5, such as a memory cell, in which a QSFET and an n-channel MQsFET are formed and a portion thereof has a high resistance circuit.

（ａｌ　　ｎ−一部Ｓｉ基板１を用意し、全面にｐ（リ
ン）イオンの打込みを行う。次いで表面酸化膜（Ｓ　ｉ
　０２）２を形成し、ホトレジスト３によるウェル窓開
し、Ｂ（ボロン）イオン打込みを行う。(al n-A partial Si substrate 1 is prepared, and p (phosphorous) ions are implanted into the entire surface. Then, a surface oxide film (Si
02) 2 is formed, a well window is opened using photoresist 3, and B (boron) ions are implanted.

（ｂ）ウェル拡散のための熱処理を行い、基板表面層に
ｎ一層４とｐ−ウェル５を形成する。(b) Heat treatment for well diffusion is performed to form an n-layer 4 and a p-well 5 on the substrate surface layer.

（Ｃ）酸化膜２を全面除去し、洗浄後、新たに薄い酸化
膜６を形成し、次いでＳｉ３Ｎ４膜７をデボジショ／し
、ホトレジスト８によりＳｉ３Ｎ４膜を部分的に除去す
る。(C) After removing the entire surface of the oxide film 2 and cleaning, a new thin oxide film 6 is formed, then a Si3N4 film 7 is deposited, and the Si3N4 film is partially removed using a photoresist 8.

（ｄ）全面にＣＶＤ膜９を形成し、ホトレジスト処理ニ
ヨリｐ−ウェル側のＣＶＤを取除いた後、Ｂイオン打込
みを行う。(d) After forming a CVD film 9 on the entire surface and removing the CVD film on the p-well side after photoresist treatment, B ions are implanted.

（ｅ）ＣＶＤ膜９を取除いてｎ−基板側を露出すると同
時にｐ−ウェル側を新たなＣＶＤ膜１０で覆い、ｐイオ
ン打込みを行う。(e) Remove the CVD film 9 to expose the n-substrate side, simultaneously cover the p-well side with a new CVD film 10, and perform p ion implantation.

（ｆｌ　　前記Ｓｉ、Ｎ、膜をマスクとしてフィルド部
に選択酸化膜１１を形成すると同時に、この酸化膜１１
の下にｐ領域１２及びｎ領域１３を拡散する。このあと
両面エッチを行ってＳｉ３Ｎ、膜７及び薄い酸化膜６を
除去する。(fl At the same time, a selective oxide film 11 is formed in the filled part using the Si, N, and film as a mask.
A p region 12 and an n region 13 are diffused below. Thereafter, double-sided etching is performed to remove Si3N, film 7, and thin oxide film 6.

（ｇ）　　ゲート酸化膜１５を生成し、次いで、ポリＳ
ｉ層１６をデポジションし、ホトレジスト処理によりソ
ース・ドレイン部を窓開する。このあとポリＳｉ層１６
に対し低濃度不純物イオン打込みを、かるく行う。(g) Generate gate oxide film 15, then polyS
The i-layer 16 is deposited and the source/drain portions are opened by photoresist processing. After this, poly-Si layer 16
Low-concentration impurity ion implantation is performed lightly.

（ｈｌｃＶＤ酸化膜を形成し、ホトレジスト処理により
ｎ−基板側を露出するｐ＋マスク１７となし、高濃度Ｂ
拡散によりｐ＋ソース、ドレイン１８を形成する。(A hlcVD oxide film is formed, a p+ mask 17 is formed to expose the n- substrate side by photoresist processing, and a high concentration B
A p+ source and drain 18 are formed by diffusion.

（ｉ）　　ｐ＋マスク１７を取除き、ｐ−ウェル側を露
出するｎ＋マスク１９を形成、高濃度ｐ拡散によりｎ＋
ソース、ドレイン２０を形成する。これらの工程におい
て、第２図に示すようにボＩＪ　Ｓ　ｉ層の一部にｎ＋
マスク（ＣＶＤ酸化膜）１９ａが残るようなパターンの
ホトマスクｍ、、ｍ２を使用し、このｎ　マスク１９ａ
によってボＩＪ　Ｓ　ｉ層の一部は高抵抗部２１となっ
て残り、マスク１９ａで覆われない部分１６は高濃度不
純物ドープにより低折抗部となる。(i) Remove the p+ mask 17 and form the n+ mask 19 that exposes the p- well side, and by high concentration p diffusion, the n+
A source and drain 20 are formed. In these steps, as shown in FIG.
Using photomasks m, m2 with a pattern that leaves the mask (CVD oxide film) 19a, this n mask 19a
As a result, a part of the IJ Si layer remains as a high resistance part 21, and a part 16 not covered with the mask 19a becomes a low fold part due to high concentration impurity doping.

（ｊ）全面にＰＳＧ（リン・シリケート・ガラス）膜２
２を形成し、Ｎ２アニールの後、コンタクト部ホトエツ
チングを行い、次いでＡｇ蒸着、配線パターンマスクに
よるホトエツチングを行ってＭ配線２３を完成する。(j) PSG (phosphorus silicate glass) film 2 on the entire surface
After N2 annealing, photoetching of the contact portion is performed, followed by Ag evaporation and photoetching using a wiring pattern mask to complete the M wiring 23.

第３図はこの発明の第４図の回路に対応するメモリセル
の平面形状を示す。同図において、斜線ハツチングを施
した部分がポＩＪ　Ｓ　ｉ層１６からなる配線でその一
部をＭＣ８ＦＥＴ（Ｑ＋　　、Ｑ２　　。FIG. 3 shows a planar shape of a memory cell corresponding to the circuit of FIG. 4 of the present invention. In the figure, the hatched portion is the wiring made of the POIJSi layer 16, and part of it is connected to the MC8FET (Q+, Q2).

Ｑ３　、Ｑ４　）の各ゲートを構成する。又、破線でハ
ンチングを施した部分は高抵抗部（Ｒ１，Ｒ２）である
。このＲ，、Ｒ２は第５図に示すよりなｐ＋拡散マスク
ｍ、とｎ＋拡散マスクｍ２とを使用し、これらのマスク
の重複する部分ｍＲ，，ｍＲ２によって不純物のドープ
されない高抵抗部をつくるものである。Q3, Q4) are configured. Furthermore, the portions hatched with broken lines are high resistance portions (R1, R2). These R, , R2 use p+ diffusion masks m, and n+ diffusion masks m2 shown in FIG. 5, and the overlapping portions of these masks mR, , mR2 create a high resistance part that is not doped with impurities. It is.

上記実施例で明らかなように上記例によればマスクパタ
ーンの一部を変更するのみで、新たな工程を付加するこ
となく６ＭＯ８に高抵抗素子を形成することができる。As is clear from the above embodiment, according to the above embodiment, a high resistance element can be formed in 6MO8 by only changing a part of the mask pattern and without adding any new process.

この発明＆’！　ＣＭ　ＯＳを用いた半導体装置で、高
抵抗素子を必要とするすべての場合に適用できる。This invention &'! It can be applied to any semiconductor device using CMOS that requires a high resistance element.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｊｌはこの発明の一実施例の工程図、
第２図はこの発明の原理説明のための断面図、第３図は
この発明を応用したメモリセルの平面図、第４図は第３
図に等価の回路図、第５図は第３図のメモリセル装置の
際にｐ＋拡散及びｎ＋拡散に使用するマスクの形状を示
す平面図である。 １・・・ｎ−型８１基板、２・・・表面酸化膜、３・・
・ホトレジスト、４・・・ｎ−ｉ、５・・・ｐ−ウェル
、６・・・酸化膜、７・・・Ｓｉ、、Ｎ４膜、８・・・
ホトレジスト、９・・・ＣＶＤ膜、１０・・・ＣＶＤ膜
、１１・・・選択酸化膜、１２・・・ｎ領域、１３・・
・ｎ領域、１５・・・ゲート酸化膜、１６・・・ポリＳ
ｉ層、１７・・・ｐ　マスク、１８・・・ｐ　ソース、
ドレイン、１９・・・ｎ　マスク、２０・・・ｎ　ソー
ス、ドレイン、２１・・・高抵抗部、２２・・・ＰＳＧ
膜、２３・・・Ａ４配線。 第　　１　　図 第　　１　　図 第　　２　　図 ７Ｄ Ｉ 第　　４　　図　　　　　　第　　５　　図第　　３　
　図FIG. 1(a) to (jl are process diagrams of one embodiment of this invention,
FIG. 2 is a cross-sectional view for explaining the principle of this invention, FIG. 3 is a plan view of a memory cell to which this invention is applied, and FIG.
The figure is an equivalent circuit diagram, and FIG. 5 is a plan view showing the shape of a mask used for p+ diffusion and n+ diffusion in the memory cell device of FIG. 3. 1... N-type 81 substrate, 2... Surface oxide film, 3...
・Photoresist, 4... n-i, 5... p-well, 6... oxide film, 7... Si, N4 film, 8...
Photoresist, 9...CVD film, 10...CVD film, 11...selective oxide film, 12...n region, 13...
・N region, 15... Gate oxide film, 16... Poly S
i layer, 17...p mask, 18...p source,
Drain, 19...n Mask, 20...n Source, drain, 21...High resistance part, 22...PSG
Membrane, 23...A4 wiring. Figure 1 Figure 1 Figure 2 Figure 7D I Figure 4 Figure 5 Figure 3
figure

Claims (1)

【特許請求の範囲】 ｌ・　　　　　゛　　　　　　　　　　　　　メモリの
負荷となるべきポリシリコン高抵抗を有し、前記高抵抗
の両端は直接Ｎ型に高濃度ドープされたポリシリコン配
線に接続され、Ｐ型ウェル領域を有する相補型ＭＩＳ半
導体集積回路装置。 ２゜上記特許請求の範囲第１項の記載の相補型ＭＩＳ半
導体集積回路装置においで、上記高抵抗の一端は、Ｎ型
に高濃度ドープされたポリシリコン配線を介してＮ型の
ソースまたθニドレイン領域に接続されてなることを特
徴とする相補型ＭＩ８半導体集積回路装置。[Claims] l・゛ It has a polysilicon high resistance to serve as a memory load, and both ends of the high resistance are directly connected to an N-type heavily doped polysilicon wiring, and a P-type well region is connected to the polysilicon wiring. A complementary MIS semiconductor integrated circuit device having: 2. In the complementary MIS semiconductor integrated circuit device according to claim 1, the one end of the high resistance is connected to the N-type source or θ via the N-type heavily doped polysilicon wiring. 1. A complementary MI8 semiconductor integrated circuit device, characterized in that the MI8 semiconductor integrated circuit device is connected to a dorain region.
JP58184986A 1983-10-05 1983-10-05 Complementary MOS semiconductor integrated circuit device Granted JPS59112643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184986A JPS59112643A (en) 1983-10-05 1983-10-05 Complementary MOS semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184986A JPS59112643A (en) 1983-10-05 1983-10-05 Complementary MOS semiconductor integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2022177A Division JPS53105990A (en) 1977-02-28 1977-02-28 Manufacture of mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS59112643A true JPS59112643A (en) 1984-06-29
JPH0248142B2 JPH0248142B2 (en) 1990-10-24

Family

ID=16162794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184986A Granted JPS59112643A (en) 1983-10-05 1983-10-05 Complementary MOS semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59112643A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02128465A (en) * 1988-11-08 1990-05-16 Yamaha Corp Manufacture of integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02128465A (en) * 1988-11-08 1990-05-16 Yamaha Corp Manufacture of integrated circuit device

Also Published As

Publication number Publication date
JPH0248142B2 (en) 1990-10-24

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