JPS59127286A - Main storage control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly, to a control method for a main storage device having a hierarchical structure.

[Prior art]

The main memory capacity of information processing systems has increased dramatically in recent years due to advances in semiconductor technology that have increased the capacity of main memory elements and reduced the cost per bit, but this trend is expected to accelerate further in the future. I think it will go. In addition, as the importance of the role played by information processing systems in society has increased, the impact on society and the magnitude of losses in the event of a failure in an information processing system have increased significantly in recent years. The need for higher reliability is rapidly increasing.

Under such circumstances, a conventional technique for improving the reliability of the main memory in an information processing system is to add redundancy check bits to information bits and write them in the main memory based on coding theory. , the so-called E CC (Fyror
CheckinLlandCorrtctin,g
) method has been widely used. By the way, if a certain bit of the main memory element permanently fails, and if this is one pit in a set of bit strings, for example, 8-byte information bits and its redundancy check bit, then it is a correctable error.
The information processing system is able to obtain 1J error data, and system processing continues normally. but,
If another pit in the set of bit strings in which one pit has a fixed fault fails intermittently or permanently, it becomes an uncorrectable error, and the data contents cannot be detected by the information processing system. If the information is related to control information, the information processing system will no longer be able to continue processing, and the system will have to be stopped.

Such conventional technology is insufficient to achieve high reliability in main memory devices that will become larger and smaller in size in the future.
There is a need for a technology that can replace even one fixed pit fault by some means and make it a correctable error even if another pit becomes a fault. One of them is that if an uncorrectable failure occurs in the main memory, the failed area of the main memory can be moved to an appropriate area of the medium/high speed storage that stores a copy of the main memory. There is a method of deputation (Special Publication No. 54-1587).

However, in this conventional method, if the corresponding area on the buffer storage that is acting as a substitute for the failed area of the main memory is selected as a replacement target, the replacement of the area is not only prohibited, but also Block transfers from main memory to buffer storage that should be executed are also prohibited, which may result in a situation where the most recently accessed block in main memory d is not registered in buffer storage, and the original buffer storage There is a problem that functionality is significantly impaired.

[Purpose of the invention]

The purpose of the present invention is to prevent the original function of the buffer storage from being impaired as much as possible when an uncorrectable failure occurs in the above-mentioned main storage device, and the area is replaced by an appropriate area of the buffer storage. The objective is to provide a replacement control method.

[Summary of the invention]

The gist of the present invention is that if the corresponding area on the buffer storage that is acting as the failed area of the main memory is selected as a replacement target, if it is removed from the target area, the next area to be replaced will be selected. , to perform block transfer to the area.

[Embodiments of the invention]

FIG. 1 shows an example of the configuration of an information processing system targeted by the present invention. In FIG. 1, 107 is the main memory (M2O
), which includes two arithmetic processing units (CPUs) 10
1.102 and two channel devices (CH) 105.

106 is connected. Inside each CPU 101.102 is a high speed buffer storage (HBS) 108.
104 is provided. The MSU107 has a low-speed large-capacity main memory (MS) 109, a medium-speed buffer storage (NBS) 108 that is slower than the HBS 108.104 but has a larger capacity, and perhaps faster than the M8109, and an MBS 101081c memory. MS of data 1
Medium-speed buffer storage that manages addresses on 09.
Address array (MBSAA) 11g and MB81
It is composed of a replace array (box A) 111 that manages the replacement order of data stored in 08. A main memory device having such a hierarchical structure has recently attracted attention as a device that bridges the speed difference between HBS and MS.

FIG. 2 shows a detailed diagram of the MSU 107. In this example,
It is assumed that the MBS 108 and the MS 109 transfer data in units of 256 bytes. This 256-byte data is called a line. Also, the capacity of MBS 108 is 1
Suppose it is a megabyte. Therefore, MB8108 consists of 4,028 lines. M88kk110
is composed of 4.028 entries of 512 columns×80−, and each entry corresponds to each line of MJ38108 l to l. As shown in FIG. 8, each entry of MBSAA 11Q generally consists of an address field and a valid pit (V bit). This one entry 30
The address (page address) on the MS 109 of the data stored in the corresponding line of the MBS 108 corresponding to the entry is registered in the 14-bit address m of 1. The V bit is the corresponding en of MB8AA110) IJ
This indicates whether or not 801 is valid. When @1'', it is valid, and when it is "0", it is invalid.

CPU 101, 102 and Louis CH105, 106
The main memory address associated with the main memory request issued by is stored in the address register (ADR) 201.

The main memory address set in the ADR 201 is set to 51 of the MBSAA 110 using bits 14-22.
Select one column from the two columns, read the contents of the 80-minute entries contained therein, and for each row, the conveyor circuit 202 transfers bits 0 to 18 of the ADR 201 and bit 0 of each entry 1301 of the MBSAA 110. −
18 address sections are conveyed.

An entry in which an address match is detected in the conveyor circuit 202 and the V pit is “l” is MBSAA 110
If the data exists in the MBS, the data at the main memory address is
The MBS 108, which has 108K, is used to process main memory requests. That is, bits 0-8 of the MBS address register (MBSA) 204 are set to AD 2.
Bits 14-22 of 01 are set, and bits 9-11 of MB8A 204 are set to 8, which is obtained by encoding with the encoder 208 the row number of the entry in which the v bit of MBSAA 110 is l'' and the address matches. Bits 12-16 of MBSA 204 are set to bits 28-27 of AD module 201, and MBSA 204 sets bits 12-16.
S 108 accesses. Here, MBSA 204
Bits 0-8 of the bit determine eight lines in the Mf3S 108, Beep)9-11 determines one line among the eight lines, and Beep)12-16 determine the target eight bytes within the one line.

On the other hand, if the conveyor circuit 202 does not detect an address match, it means that the data at the main memory address of ADR2Ql does not exist in the MBS 108. In this case, select one row from 80- in the relevant column of MBSAA 11g, and select the address field 0 of that entry.
-18KADR201 (7) Gila) Register 0-18', set the V pit to l", and set the M corresponding to the entry.
To BS108 no line, ADR201 (D hit 0-
Transfer the data block of MS 109 designated by 22. MBSAA 110 or MBS 10B
It is called a replacement.

The RAIII in FIG. 1 determines the entry to be replaced, and the MBSAA 11o) manages the entries to be updated next corresponding to each column.

The algorithm id & etc. that determines the entry to be replaced can be seen, but here we use PIFO (First
In First Ou, t) method shall be adopted.

FIG. 4 shows one piece of replacement management data in 1 (, A11l. In FIG. 4, the replacement management data 40
1 consists of an 8-bit pass/grow counter corresponding to the eight rows of M13SAA 110.

That is, bit O is O low, bit l is 10-gold,
From then on, in the same way as F, bit 7 is set to 70-, and among these 7 bits, only 1 bit is always set to "1", and 0 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → The bits set to 1" move in the order of O. The bits set to 1" in 'G401' in RA 111 move as fv
! This is done once when the IBsAA 110 updates the registered address.

The above is an explanation of a general case where the purpose is not to increase the reliability of the MS 109, but below, for the purpose of increasing the reliability of the MS 109, an uncorrectable failure occurs in the MS 109, and the failure area is transferred to the MBS 108. An embodiment of the present invention will be described in which the area is replaced with an appropriate area.

In the present invention, the registered contents of each entry in the MBSAA 110 change as shown in FIGS. 3 to 5. That is,
In entry 501, a ■ bit is added in addition to the address field and the V bit. This ■ bit is a replacement inhibition bit, and the MBSAA in which this bit is set
110 entries are inhibited from being replaced. In other words, when an address mismatch occurs as a result of searching Mt38AA 110, the MBSA pointed to by FLAll
A 110 En) If 1 bit is set in the registered contents of IJ, do not make that entry a replacement target, count up RAIII by one more, and select the entry with the next row number? ]l-Check, and if the ebit of this entry is 0'', this entry will be replaced of course. As a result, entries with the bit set are always registered on the MBSAA 110, and requests for the address will not be accepted. is always processed using MS8108k, and the address of MS IQ9 is never accessed.

■The bit is set when one of the following conditions is met for the MS 109 bladder output data: (1) When a correctable error occurs a specified number of times at the same location; (2) When an uncorrectable error occurs. done at times. This set of I bits is
This may be done at the same time as registering a new address in the M8BAA 110, or at any time during registration. (2) When a store request occurs at an address corresponding to an entry with bit=:1, it is desirable to suppress the store request to the MS to prevent a failure from occurring in the MS due to the store request.

FIG. 6 shows one embodiment of the present invention, and the parts that overlap with those in FIG. 2 are omitted. From FIG. 2, if MSBAA 110 is searched by the address set in ADR 201 and no address match is detected in any row,
A not in MBS signal 207 is output. At this time, in Figure 6, the MBS determined by the address at that time
The 80-minute I bit of AA 110 is read and input to selector 601. The output of f(A 111 is input to the selector 601 as a select signal. Now, of the 8 outputs of the I bit of MBSAA 110, the 10th
Only - minute is '1'' and 3 others are 10'', and )t, A
If the output of Ill is "01000000" and points to the 10th- bit, the selector 601 selects the 10th- bit, and its output becomes "1".

AND circuit 605 K is the output of selector 601 and not
Now that the in BS signal 207 is input, both signals are "■", so an AND is performed, and the output of the AND circuit 605 becomes 1. The output of the AND circuit 605 is input to the RA count up circuit eos'vc. The current output value of LAIII (01000000) is input to this A count up circuit 608. AN
Since the input from the D circuit 605 becomes 11'', the A count up circuit 60B creates "00100000" and convolves it with the A 111. As a result, f
'The output of LA111 now points to the 20th-, and the selector 601 selects the 20th-, so the selector 601
The output of 1 becomes '0''. Therefore, the A of the AND circuit 605
The ND condition no longer holds true.

The output of selector 601 is passed through inverter 606 to AN
It is input to the D circuit 607. The other input to the AND circuit 607 is the n'o t in MBS signal 207. Since the row number pointed to by RAIII changes from 1 to 2, the AND condition of the AND circuit 607 is satisfied, and the output of the M mountain circuit 607 activates the not in MB8 processing circuit 608.

The main operations of the not in MB8 processing circuit 608 are as follows.

■ MB indicated by bits 0-11 of MBSA 204
The line of MS 109 indicated by bits 0-22 of MAI (201) is read and stored at the line address of S108.

(2) Write bits 0 to 18 of the MA 201 and the V bit to the corresponding entry in the MBSA Allo through the column address circuit 604 indicated by the bits 14 to 22 of the MAR 201 and using the row address indicated by the RA 111; At this time, according to the above conditions, if necessary, I bit 6
Enter 09 to write the ebit.

■ The RA count amplifier 602 counts up the RA.

[Changes to Examples]

In FIGS. 5 and 6, it is assumed that the EVIT is included in the MSBAA, but it is also possible to configure an I-pit array in which only the I-pits are independent.

In addition, in the embodiment, a hierarchical structure of MBS is based on MsU,
Although it has been described that the failure area 'i MBS of the MS is substituted, the HBS within the CPU may be substituted.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when an uncorrectable fault occurs in the main storage, when replacing that area with an appropriate area of the storage, the entry of the replaced buffer storage is replaced. The entry in the next ranking will be removed from the list and replaced, so the replacement will be carried out without any problems.
Normal system operation is possible without impairing the original function of buffer storage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of an information processing system targeted by the present invention, FIG. 2 is a diagram showing an example of the configuration of the main storage device in i6 in FIG. 1, and FIG. 3 is a general buffer address array. FIG. 4 is a diagram showing the contents of one entry in the replacement array. FIG. 5 is a diagram showing the contents of one entry in the buffer address array of the present invention. FIG. FIG. 1 is a diagram showing a configuration example of an embodiment. 101.102...Central processing unit, 103.104.
...High speed buffer storage, 108...Medium speed buffer storage, 109...Main memory, 110...Buffer storage address array, 111...Replace array. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] (1) A main memory, a buffer storage for tally entries that stores a copy of the main memory, an address array that stores addresses on the main memory corresponding to each entry in the buffer storage, and and a replace array that stores an entry replacement algorithm, and in response to a memory storage request, searches the address array to see if the data at the main memory address of the request is in the buffer storage, and if the data is in the buffer storage. accesses the buffer storage, and if it is not in the buffer storage, accesses the main memory,
In a main memory control method for writing data read from the main memory to a buffer storage entry (replace entry) selected according to the contents of the replace array, being selected as a replacement entry corresponding to the buffer storage entry. If a buffer storage entry for which this bit is set is selected as a replacement target, that entry is removed from the replacement target and the next entry for which this bit is not set is set. A main memory control method characterized in that data read from main memory is written as a replacement entry.