JPS59139196A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to MO8 type random access dynamic read/write memory.

Dynamic MOS memories have traditionally used bistable differential sense amplifiers whose inputs are connected to bit lines (column lines) divided into two halves. A dummy cell provides a reference voltage on the half bit line to the unselected ζ. This type of sense amplifier is known from U.S. Pat. No. 4,239,993 issued to McAlexander White, Rao, U.S. Pat. No. 3,940,747, issued in 1999. All of these have been transferred to the Texas Institution.

Previously used differential sense amplifiers required a period of time during the cycle to equalize each half of the bit lines while precharging.

This period is, for example, 50 nanoseconds, and this pressure equalization period has become an important element when aiming at manufacturing high-speed devices.

A primary object of the present invention is to provide an improved sense amplifier for high speed random access read/write memories, particularly one transistor cell arrays. Another object is to provide a sense amplifier for use in a dynamic memory array that has short cycle times because the precharge time is shortened.

SUMMARY OF THE INVENTION In accordance with one embodiment of the present invention, a semiconductor memory device having an array of rows and columns of dynamic one-transistor memory cells connects the entire column line of each column line rather than connecting to two halves of the column line. A bistable circuit with an unbalance-terminated (single-ended) differential amplifier connected to the column line with a p-coupled drive transistor connected on one side to the column line by a first coupling transistor. Ru. This coupling transistor turns off when the row line goes high, leaving a fixed reference voltage. The other side of the circuit is now connected to the column line by a second coupling transistor. This coupling transistor turns on after the column line is stable. This column line voltage is related to whether a 1 or a 0 is being stored. The time required to precharge the column line is short. The two halves of the column lines do not need to be precharged from different levels, thus reducing memory cycle time.

The device is also less sensitive to errors due to alpha particles since changes in bit line voltage affect both inputs of the sense amplifier equally.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to FIG. 1, a non-balance terminated sense amplifier circuit for a dynamic memory in accordance with the present invention is illustrated. This memory device is similar to that disclosed in U.S. Pat. No. 4,239,999, except that the bit line is not divided into two halves.
It is in the format described in the issue. The array of one-transistor dynamic memory cells 10 is, for example, 256K.
Alternatively, it is formed on a semiconductor chip with a 1 megabit configuration.

Each cell 10 has a storage capacity i-element 11 and an access transistor 12. all transistors 1 in a row
The gates of 2 are connected to the row line 13 and the drains of all transistors in the column are connected to the column line 14. 256
A device typically has 512 row lines 13 and 512 column lines 14, and the device is partitioned into blocks so that on a particular column line, for example, there are only 128 cells, thereby The ratio between the capacitance 11 of the cell and the capacitance of the bit line 14 falls within an acceptable range.

The sense amplifier consists of two cross-coupled drive transistors 15 connecting a pair of sense nodes 16 and 17 to a ground node 18. Nodes 16 and 17 are coupled to bit line 14 by two separate coupled transistors 20 and 21 with clock voltages 4 and φt on their gates, respectively.
connected to. Transistor 20 serves to set a reference voltage on sense node 16 (similar to a dummy cell in a conventional sense amplifier), and transistor 21 serves to connect the sensed cell to another sense node 17.

As shown in the timing table of FIG. 2, the voltage of the clock φ8 decreases before (or at the same time as) the selected XW iE voltage of one of the row lines 13 becomes a high potential, and the voltage of the clock φ8 decreases at the node 16.
Isolate the reference voltage above. Then, the selected cell capacitive element 11 drops a voltage of +11 (or 1).
(or 0, depending on which one is stored) After that, the voltage drop φt isolates the voltage sensed at node 17 from the others.

Each bit line 14 is precharged by a transistor 24 to which a p clock φpc is applied at the date.

This precharge clock φpo is at a high potential during the precharge cycle, and then, before φB or goes down.

Normally, the voltage of the precharge clock is lowered by receiving the chip input pull clock 01c from outside the chip.

In devices with multiplexed addressing, the row address stroso RAS voltage initiates the read cycle. This is followed by a column address strobe OAS. Therefore, i in FIG. 2 corresponds to i in the multiplex device.

Ground node 18 is connected to ground via a transistor 25 receiving date clock voltage φl.

As can be seen from FIG. 2, during the time when φt is at a high potential, the clock φt is at a high potential, causing the cross-coupled drive transistor to start a latch operation. Transistor 25 is shared with all sense amplifiers on the chip.

Also, instead of using a single grounded transistor, two or three transistors that turn on with a short delay time may be used as described in US Pat. No. 4,239,993.

U.S. Patent Nos. 4.239,993 and 4,081.7
The active pulldown circuit described in No. 01 is connected to sense nodes 16 and 17. These circuits have a load transistor 27 at the gate that receives the boost clock φb. A shunt transistor 28 having a trap voltage Vtr on its date connects the date of transistor 27 to node 16 or 17. The trap voltage Vtr is kept at vdd during precharge, and then φpc
When the voltage of transistor 27 drops, the Vdd voltage falls below one or two thresholds below Vdd.
The capacitive element 29 is formed by remaining above and being trapped.

The voltage at one of the nodes 16 or 17 is φl = 1. The transistor 28 is turned on, the date of this transistor 27 is discharged, and the date capacitance element 29 on this side has a condition of zero capacitance. Therefore, when the sunset voltage φb becomes a high potential, the capacitive element 29 is not formed on the side where the potential is zero, and the r-) of the transistor 27 on that side is shunted to its source by the transistor 28, so the capacitive element 29 is not formed on the side where the potential is zero. transistor 27 is never turned on. On the other side, transistor 28 is off and the φb voltage pulls up the date of transistor 27 to a voltage higher than Vnd, pulling node 16 or 17 fully to V(1). If it remains, the full Vaa can be provided to refresh the selected cell capacitive element 11 after φt goes high again. When node 17 goes low, the zero is refreshed. .

The output from the sense amplifier for read operations (or input for write operations) passes through a pair of transistors 30, each with 2φy applied to their date.

This Y selection voltage φy is connected from the Y decoder, and connects the selected column to a buffer for connection to the outside of the chip. In a read operation, as shown in Figure 2, sometime after φ1 goes high, the clock φ
y becomes a high potential.

Transistors 20 and 21 connect sense nodes 16 and 1
7 physical, 1! In order to maintain a mechanical balance, each transistor has transistors 20& and 21a connected in parallel. The transistor 20a is
Similarly, 4 days are applied, but the date of transistor 21 & is connected to ground. The apparent capacity on node 16 is greater than the capacity on node 17. This results in 7-
It decouples more charge from node 16 than from node 17, creating a reference offset voltage (as traditionally done with a dummy cell that is half the size of the capacitive cell). Transistors 20.20a, 21.21& are all physically the same size. When φB goes low, the negative going offset reduces the voltage on node 16 by a predetermined amount, e.g. 200 millivolts, but when φt goes low, only one transistor experiences a negative voltage change. 7-, the voltage on node 17 is reduced to half of the above amount. However, in addition to this effect on node 17, an offset is provided by the selected storage capacitive element. As a result, if O is stored after φt, the voltage at node 16 will be lower than that at node 17, but if 1 is stored, the voltage at node 17 will be higher than that at node 16. The latch formed by transistor 15 therefore flips after φl goes to a high potential.

FIG. 2 shows the voltages on bit line 14 and sense node 16.17 during an active cycle, with the 1 stored state and the O stored state.

Since the precharge voltage φpO% word line voltage XW and clock φday and φt are boosted to a height higher than V4d (indicated by Vcl here), all the 7th nodes are completely at the ■dd level. Hail!

A feature of the invention is the operation during the precharge portion of the cycle. As shown in FIG. 2, when the active cycle is completed and φpc goes high, the bit line 14 is immediately precharged to Vaa (or vaa - Vt) to equalize the two halves of the pit line set. The problem of doing so has been resolved. In the past, long periods of time were used to ensure that half the bit lines (one half at 1 and the other half at 0) had exactly the same voltage. Since the halved bit line set has a relatively large capacity, it takes a longer time to equalize the voltage. On the other hand, the bit line 14 in the present invention has a slightly lower voltage when it is 0 than when it is 1, but this is an important problem because the sense amplifiers on both sides are equally affected. Not.

Naturally, nodes 16 and 17 must be pressure equalized, but since there is a very small agreement between them, such pressure equalization can be done quickly. The transistor 31 is φpc
is used to equalize the voltages at nodes 16 and 17 between. After a short delay period, the next cycle begins by dropping the voltages φpc and φday, so that the cycle time of the memory device is no longer actually much longer than the access time, but is shortened.

Another important feature of the invention is that it is relatively robust to errors caused by alpha particles.

When an alpha particle impinges on a silicon chip, it instantly creates a small electrically conductive area. Operation of the cell or bit line is disturbed by a tortoise change which is comparable to a change in the voltage of the data bit or bit line being stored.

Conventional dynamic RAM with bit lines divided in half
In the circuit, the alpha particles will therefore create a differential voltage at the input of the sense amplifier and possibly an error output. However, in the circuit of the invention, changes in the amount of charge on the bit line 14 caused by alpha particles affect both inputs 16 and 17 connected to the sense amplifier equally and therefore do not generate errors.

As described above, by using unbalanced-terminated differential sense amplifiers connected to all five row lines and column lines without halving them, the period for pressure equalization can be shortened, and the α particle It is possible to provide a dynamic RAM memory that is not affected by

Although the invention has been described with reference to specific embodiments, this description is not intended to be limiting. Various modifications of the embodiments shown, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description.

It is therefore intended that the appended claims cover any such variations and modifications that fall within the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is an electrical schematic diagram of a portion of a memory array illustrating the sense amplifier circuit of the present invention. FIG. 2 is a graph showing the voltages present in various parts of the circuit of FIG. 1 versus time. 10...Access transistor 13...Row line 14...Column line 15...702 Coupled drive transistor 6 16.17...Sense node 18...Ground node 20.21...Coupling transistor 24...Transistor agent for precharging Haru Asamura Engraving of drawing (no change in content) Procedural amendment (method) % formula % 1. Indication of the case Showa, 1932 Patent Application No. 172λ 2, Invention Name 3. Relationship with the case of the person making the amendment. Patent applicant address 4. Agent 5. Date of amendment order: February 1939. Day 6, number of inventions increased by amendment 7, engraving of drawings subject to amendment (no change in content)

Claims (9)

[Claims] (1) An array of rows and columns of memory cells each having an access transistor with the drain connected to the column line and the date connected to the row line, and an unbalanced termination sense differential amplifier connected to each column line. each sense amplifier has a pair of cross-coupled P drive transistors, first and second separate coupling transistors, each transistor having an electrical path between a source and a drain; The amplifier further includes means for connecting an electrical path between the source and drain of the first coupling transistor between the column line and the first sense node and a second coupling between the column line and the second sense node. means for connecting an electrical path between the source and drain of the transistor, wherein the electrical path between the source and drain of the drive transistor separately connects the first and second sense nodes to the ground node. a sense amplifier; a precharge means for precharging the column line to a predetermined voltage before the start of the active cycle; and a sense amplifier for turning off the first coupling transistor at a first time at the start of the active cycle. a first clock voltage applied to a first coupling transistor within the amplifier; row addressing means; and a second clock voltage applied to the state of the coupling transistor in the sense amplifier to turn off the second coupling transistor at a second time of said active cycle after said first time. A memory device with. (2) The device according to claim 1, wherein the first sense node f has a larger capacity than the second sense node. (3) The device according to claim 2, wherein the memory cell is a dynamic memory cell that stores data in a storage capacitor element. 4. The apparatus of claim 6, wherein said grounding means connects said groundmate to a reference potential at a sixth time after said first time of said active cycle. (5) In the above device, after the sixth time in the active cycle, the second voltage again goes to a high potential to refresh the selected memory cell via the column line. Apparatus according to paragraph 4. (6) The apparatus of claim 4, wherein the output means is connected to at least one of the sense nodes at a fourth time in the active cycle after the second time. . (7) In the above device, each of the first and second coupling transistors has one transistor connected in parallel with each other to form a pair, and the other transistor to form a pair of the first coupling transistor. date is the first date above.
5. The device of claim 4, wherein the r-to of the other transistor of the pair of said second coupling transistor is connected to ground potential. (8) A column line selectively connected to the memory cell at a first time, a differential sense circuit having first and second inputs, and the first and second inputs separately connected to the column line. first and second coupling means for connecting a first input to a column line before said first time;
timing means for activating the first coupling means for isolating the first input from the column line after a time period of , and thereby establishing a reference voltage on the first input; and before the first time period. The second input is connected to the column line during the start period and remains connected until a second time after the first time to isolate the input of apprentice 2 from the column line, thereby selecting and timing means for activating the second coupling means to set a voltage on the second input in relation to the contents of the memory cell. (9) The timing means again connects the second input to the column line after a delay time after the second time, thereby refreshing the selected memory cell. circuit. aω The circuit according to claim 8, wherein the memory cell in the circuit is a dynamic one-transistor cell having a storage capacitor element. OD. The circuit of claim 8, wherein the sense circuit is a bistable p-coupled sense amplifier. (12+) The circuit according to claim 8, wherein the capacitance of the first input is larger than that of the second input.