JPS59147467A - static induction transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic charge transistor in which an active region is vertically formed using a compound semiconductor on an insulating semiconductor substrate made of a compound semiconductor.

Quiet? h Ffi conductive transistor (hereinafter referred to as SIT).

) have excellent characteristics such as inherently low series resistance and low parasitic capacitance, so compared to bipolar transistors and field effect transistors, they can be used for higher frequencies, higher speeds, higher outputs, and lower This has great advantages in terms of noise reduction, etc.

In particular, an SIT with a fine structure using a compound semiconductor such as G8^S, which has a high carrier movement speed, is called a pallitic transistor, and is expected to be an element with the ultimate high speed.

Furthermore, monolithic integrated circuits (hereinafter referred to as SIT ICs) including S-cards having these excellent characteristics are also expected to have similar properties.

However, conventional SITs are formed on the L of a low-resistance semiconductor substrate, as typically shown in FIGS.
For this reason, there were the following problems. In Figures 1 to 3, 1 is an N-type low-resistance semiconductor substrate, 2 is an N-type high-resistance semiconductor region, and 3 is a P-type low-resistance semiconductor region. , 4 is an ohmic electrode for the source, 5 is an ohmic electrode for the gate, 6 is an ohmic electrode for the drain, 7 is a Schottky electrode for the gate, and 8 is an insulator.

As shown in Figures 1 and 2, the single S
Regardless of the case where S I '1- is constructed, as shown in FIG.
When composing a unit S, the train electrode 6 is first connected to each unit S.
Since there is one in common for I'r, each unit SI'r
Secondly, since the drain electrode is on the back side of the substrate 1, it is difficult to connect it to the source and gate of each unit S I T on the opposite side. When forming the IC's 11 old Raku constants and mutual wiring in an insulating film on the same substrate on which the unit Sl'r is formed in 3, the capacitance between this and the low resistance group 4fy will inevitably become large. There is a problem that there is no l/l.

Therefore, it is not possible to freely design the SI'T"-IC, and the SI'F-I which takes advantage of the above-mentioned advantages of the
It becomes impossible to realize C.

The present invention has been made in view of the above, and its objective is to form an sr'r having a vertical active region on one side of an insulating substrate made of a compound semiconductor. Therefore, each electrode can be taken out only from one side, and a plurality of SITs can be separated from each other to form "ζ".

The present invention will be explained in detail below. In this embodiment, a compound semiconductor such as GaAs is used as the semiconductor. In FIG. 4, numeral 9 is an insulating semiconductor substrate made of a compound semiconductor, and its specific resistance is 10 6 Ω or more. 10 is an N-type low resistance semiconductor region forming a drain region; 11
is an N-type high resistance semiconductor region forming a channel region,
12 is an N-type low resistance semiconductor region forming a source region;
Reference numeral 13 denotes a P-type low resistance semiconductor region forming a gate region, and an active region formed by these semiconductor regions is formed by vertically stacking layers by medium epitaxial growth. 14 is an ohmic electrode for the drain, 15 is an ohmic electrode for the gate, 1
6 is an ohmic electrode for the source, 17 is the electrode 14
18 is an insulating material for separating the electrode 15 from the electrode 1G.

r) Since one S I'V is vertically constructed on one side of the insulating semiconductor substrate 9 as shown in the figure, it can be seen only from one side of the insulating semiconductor substrate 9]. Each electrode can be pulled out.

In addition, even when a plurality of SITs constitute S]TIC, they can be formed in the same way on one side of the insulating substrate 9, and in this case, the SITs at positions ti' are mutually interconnected by the insulating semiconductor substrate 9. It is insulated and can easily interconnect electrodes on one side. FIG. 5 is an example of this, in which the ohmic electrode 14 for the drain of the SIT on the left is connected to the ohmic electrode 14 for the drain of the SIT on the right.
It is ohmically connected to the ohmic electrode 15 for the gate.

In addition, even if other circuit constants such as inductance and capacitance necessary for IC conversion and interconnections are formed on the side of the insulating semiconductor substrate 9, the insulating semiconductor substrate 9 is present in these parts. , it is possible to significantly reduce the extra capacitance.

It should be noted that the drain region 1o and the source region 12 can of course be used in the opposite manner, and an insulating protective film is formed on the insulating semiconductor substrate 9 to cover a portion thereof. The ohmic electrode 14 can also be formed in this manner.

Next, a method for manufacturing the SIT shown in FIG. 4 will be explained. First, a low-resistance semiconductor region 10 is formed on an insulating semiconductor substrate 9 by eviximal growth, then a high-resistance semiconductor region 11 is similarly formed by eviximal growth, and then a low-resistance semiconductor region 12 is similarly grown by eviximal growth. These form a vertically laminated active region consisting of a drain region, a channel region, a JG, and a source region.

Then, by fumetetching, parts of the active area are left and other parts are removed. At this time, the etching solution is, for example, 112 SO4:I (202:I-
(Use 20 threads.

Next, an electrode 14 is formed on the insulating semiconductor substrate 9 by vapor deposition to make an ohmic contact with the low resistance semiconductor region 1o, and then an insulator 17 is formed on the second side of the electrode 14. This insulator 17 is made of, for example, an oxide film of NO and Si11, or a nitride film of Nll3, Δr and 5itl+, at a temperature of 20°.
Plasma CV°1. ) Formed by law.

Next, Zn-doped SiO2 is deposited on the insulator 17 by a thermal decomposition method, and Zn is diffused into the high-resistance semiconductor region 11 by heat treatment at 5[)0 to 600°C to form a A semiconductor region 13 is formed. After this, Z n doped S
iO2 is removed.

Next, the electrode 15 is formed on the insulator 17 by vapor deposition.
I) type semiconductor region 13 and the insulator 18 is formed on the electrode 15 in the same manner as the above insulator I7, and finally the low 1] (antibiotic conductor ff+ region 12 and insulated An electrode 16 is formed on the negative side of object 1B by vapor deposition.
An ohmic contact is made to the low resistance semiconductor region 12.

Note that the above SIT has 1) as a gate region in the active region.
type semiconductor region 13 is formed, and a PN junction is formed between it and the N-type li':l resistive semiconductor region 11. However, the gate electrode 15 is made of Schottky metal (ΔI, T'1X
Pt, Mo, W, etc.), a Schottky barrier is formed at the junction between the Schottky metal and the N-type high resistance semiconductor region 11.
does not need to be formed.

Furthermore, it goes without saying that the above-mentioned P-type and N-type semiconductors can be made of opposite conductivity types.

From the above, according to the present invention, since the SIT is formed by vertically forming the active regions of the same compound semiconductor on the second and second sides of the insulating semiconductor substrate made of the compound semiconductor, the same Even if a plurality of SITs are formed on a common insulating semiconductor substrate, there is no problem with the difference δ11 between the heights s i ``r, and all the electrodes can be taken out from the same surface. -10 is easy to design, and even if other phase 1/8 elements or phase 7 and 7 wiring are provided, the extra capacitance can be reduced to a large one.

In addition, SO8 was previously used to form a transistor on an insulating substrate, but in this case, the transistor is formed on sapphire, and the active region and the substrate are made of different materials, so the bonding is difficult. Therefore, when a plurality of IfIl transistors are formed on the sapphire and integrated into an IC, variations among the transistors become a problem.

In this regard, since the SIT of the present invention uses the same compound semiconductor for the substrate and the active region, there is no mismatch at the interface, there are few defects, and the SIT has good crystallinity.
It has the characteristics of being able to perform C every 4 times, with small variations, good characteristics, and a long operating life.

[Brief explanation of the drawing]

Figures 1 to 3 are cross-sectional views of the conventional S I i'';
The figure is a sectional view of SI'F in one embodiment of the present invention, and FIG. 5 is a sectional view of s+'r-+c in another embodiment]. 9... Insulating semiconductor substrate, lO... N-type low resistance semiconductor region, 11... N-type high resistance semiconductor region, 12.
. . . N type low resistance semiconductor region, 13 . . . P type semiconductor region, 14 . Ill・
··Insulator. Patent Issue 1 Uto New Japan Radio Co., Ltd. Agent Patent Attorney Shijko Tomiaki Figure 3 Figure 4

Claims (1)

[Claims] (I) A low-resistance semiconductor region is formed on the surface of an insulating semiconductor substrate made of a compound semiconductor, the conductor is a compound of the same type as the compound semiconductor, and the upper surface of the low-resistance semiconductor region is connected to the low-resistance semiconductor region. a high resistance semiconductor region of a conductivity type is formed, a low resistance semiconductor region of the conductivity type is formed on an upper surface of the high resistance semiconductor region, and a gate is formed to surround at least a portion of the 1111 resistance semiconductor region; An electrostatic induction transistor characterized in that each electrode is drawn out from the gate and both low resistance semiconductor regions while maintaining mutual insulation.