JPS59165509A - Control circuit of resistance value - Google Patents
Control circuit of resistance valueInfo
- Publication number
- JPS59165509A JPS59165509A JP3947883A JP3947883A JPS59165509A JP S59165509 A JPS59165509 A JP S59165509A JP 3947883 A JP3947883 A JP 3947883A JP 3947883 A JP3947883 A JP 3947883A JP S59165509 A JPS59165509 A JP S59165509A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistors
- switching
- resistance value
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/24—Frequency- independent attenuators
- H03H7/25—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable
Landscapes
- Filters And Equalizers (AREA)
- Attenuators (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は回路定数の製造上のバラツキをタップを選択す
ることにより抵抗値を愛知最適動作となるように調整す
る回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that adjusts a resistance value to achieve Aichi optimum operation by selecting taps to compensate for manufacturing variations in circuit constants.
回路を構成する場合、素子の定数はある７９ラツキを持
って分布する。殊ｖｃ隼積回路の場合は回路をＩｖ１人
立１の際、適当々値のものを選択して構成するというこ
とが出来な（へので製造時の条件の微妙表変化によって
製品としての集積回路の特性のバラツキな避は難い。こ
のバラツキが間素に表る場合Ｔｌｃは調整を要すること
になる。この調整の方法として抵抗から端子を増ね出し
、その端子を操作することにより抵抗値を調整して回路
の特性を補正し最適動作にする方法がある。この抵抗値
を調整する回路として従来の回路例を第１図及び第２図
に示す。When configuring a circuit, the constants of the elements are distributed with a certain 79 randomness. In particular, in the case of a VC integrated circuit, it is not possible to configure the circuit by selecting an appropriate value when the circuit is Iv1. It is difficult to avoid variations in the characteristics of the resistor. If this variation appears in the intermetallic element, Tlc will need to be adjusted. One method for this adjustment is to increase the number of terminals from the resistor and increase the resistance value by manipulating the terminals. There is a method of adjusting the resistance value to correct the circuit characteristics and achieve optimum operation.Examples of conventional circuits for adjusting this resistance value are shown in FIGS. 1 and 2.
第１図は従来の回路の第１の例を示すものである。第１
図において３，４，５，６Ｆｉ同じ抵抗値を持つ抵抗で
あわ、抵抗３，４，５．６は直列に接続されている。７
．８，９．１０はスイッチング回路であり、スイッチン
グ回路７は抵抗３と４の接続麿と端子２の間を、スイッ
チング回路８け抵抗４と５の接続点と端子２の間を、ス
イ・ノチング回路９け抵抗５と６の接続声と端子２の間
を、スイッチング回路１０け端子１と端子２の間をそれ
ぞれ開閉するように構成されている。［７たがって抵抗
３，４，５．６の各抵抗値をＲとすれば０゜Ｒ，２Ｒ，
３Ｒ，４Ｆｌの５種の抵抗値がスイッチング回路７．８
．９．１０の開閉によね端子１と端子２の間に得られる
。一般に第１図と同原理で構成するとＮ個のスイッチン
グ回路に対ｔ、（Ｎ＋１）種の抵抗値が選択できる。（
７ｆＣがって選択すべき抵抗値の種類が多くなると、そ
れにほぼ比例して多数のスイッチング回路を必要とする
のが第１図の回路と同原理の回路の欠点である。スイッ
チング回路は調整に用いるので数が少ない方が望しいの
である。FIG. 1 shows a first example of a conventional circuit. 1st
In the figure, 3, 4, 5, and 6Fi are resistors having the same resistance value, and the resistors 3, 4, and 5.6 are connected in series. 7
．． 8, 9, and 10 are switching circuits, and the switching circuit 7 connects between the connecting point of the resistors 3 and 4 and the terminal 2, and the switching circuit 8 connects the connecting point of the resistors 4 and 5 and the terminal 2 with a switch. The circuit is configured to open and close between the connecting terminals of the 9-piece resistors 5 and 6 and the terminal 2, and between the 10-piece switching circuit and the terminals 1 and 2, respectively. [7 Therefore, if the resistance values of resistors 3, 4, and 5.6 are R, then 0°R, 2R,
5 types of resistance values 3R, 4Fl are switching circuit 7.8
．． 9. A spring is obtained between terminal 1 and terminal 2 by opening and closing of 10. In general, if the configuration is based on the same principle as in FIG. 1, t (N+1) types of resistance values can be selected for N switching circuits. (
7fC A disadvantage of a circuit based on the same principle as the circuit shown in FIG. 1 is that as the number of resistance values to be selected increases, a proportionally large number of switching circuits are required. Since switching circuits are used for adjustment, it is desirable to have fewer switching circuits.
第２図は従来の回路の第２の例を示すものである。第２
図の回路は少ない調整用のスイッチング回路で多くの抵
抗値を選択する為の回路構成Ｋ したものである。第２
図において１３．１４．１５，１６１７．１８．１９は
同じ抵抗値を持つ抵抗であり、抵抗１３，１４，１５，
１６，１７，１８．１９は直列に接続されている。２５
けデコーダでありλ４ＯＦ’１ＦＥＴを用いた場合の例
を示している。７０．２１．２２はスイッチング回路で
あり、＋ＶＤＤもしくけ−ｙａｓのどちらかに選択し７
で接続される。スイッチング回路によって選択された信
月はデコー・り２５に入り、デコーダの出力は抵抗１３
．１４．１５，１６゜１７．１８．１９の各啼続点及び
端子１１．１２接続されている。スイッチング回路２０
，２１．２２の組入合せによへてデコーダで選択された
出力端子１２と同電位になるように構成されている。以
十の回路構成により３個のスイッチング回路２０゜２１
．２２の選択により（０，０，０）から（１゜１．１）
までの８状態を選択できることにより、抵抗１３，１４
，１５，１６，１７，１８．１９ の各抵抗値をＲとす
ればＯ，Ｒ，２Ｂ、３Ｒ，４Ｆｌ。FIG. 2 shows a second example of a conventional circuit. Second
The circuit shown in the figure has a circuit configuration K for selecting a large number of resistance values with a small number of switching circuits for adjustment. Second
In the figure, 13.14.15, 1617.18.19 are resistors with the same resistance value, and resistors 13, 14, 15,
16, 17, 18, and 19 are connected in series. 25
An example is shown in which a λ4OF'1 FET is used. 70.21.22 is a switching circuit, which selects either +VDD or -yas.
Connected with The signal selected by the switching circuit enters the decoder 25, and the output of the decoder is connected to the resistor 13.
．． Connection points 14, 15, 16, 17, 18, and 19 and terminals 11, 12 are connected. switching circuit 20
, 21 and 22, the output terminal 12 is configured to have the same potential as the output terminal 12 selected by the decoder. Three switching circuits 20°21 with the following circuit configuration
．． From (0,0,0) to (1°1.1) by selecting 22
By being able to select 8 states up to, resistors 13 and 14
, 15, 16, 17, 18.19. If each resistance value is R, then O, R, 2B, 3R, 4Fl.
５Ｆ、６Ｒ，７Ｈの８種の抵抗値を端子１１と１２の間
にとり出すことができる。しかし々からこの回路方式は
第２図に卯られる通り、配線やデコーダに多大な素子を
必要とする。Eight types of resistance values, 5F, 6R, and 7H, can be taken out between terminals 11 and 12. However, as shown in FIG. 2, this circuit system requires a large number of wiring and decoder elements.
以上、従来の回路においては少いビット数で、かつ簡単
な回路構成を特徴とする回路は調整の範囲が狭く、また
少いビット数で広い範囲を調整できる回路は構成に要す
る素子数が多くなるという欠点があった。As mentioned above, in conventional circuits, circuits with a small number of bits and a simple circuit configuration have a narrow adjustment range, and circuits that can adjust a wide range with a small number of bits require a large number of elements to configure. There was a drawback.
本発明は少いビット数の調整で、かつ簡単で素子数の少
い回路構成で広い範囲の抵抗値を調整できる回路を提供
するものである。The present invention provides a circuit that can adjust resistance values over a wide range with a small number of bits and a simple circuit configuration with a small number of elements.
以下、実施例に基づいて本発明の詳細な説明する。Hereinafter, the present invention will be described in detail based on examples.
第３図は本発明の第１の実施例である。第３図において
２８，２９，３０け抵抗であり、それぞれの抵抗値の比
は１：２：４となっている。つまり抵抗２８の抵抗値を
Ｒとすれば抵抗２９の抵抗値は２Ｒであり、抵抗６０の
抵抗値け４Ｒである。FIG. 3 shows a first embodiment of the invention. In FIG. 3, there are 28, 29, and 30 resistors, and the ratio of their resistance values is 1:2:4. That is, if the resistance value of the resistor 28 is R, the resistance value of the resistor 29 is 2R, and the resistance value of the resistor 60 is 4R.
抵抗２８，２９．３０は直列ＶＣ壕続されている。Resistors 28, 29, and 30 are connected in series with VC.
３１．３２，３３ｕスイッチング回路である。スイッチ
ング回路６１は抵抗２８に並列に、スイッチング回路３
２け抵抗２９Ｖｃ並列に、スイッチング回路３３は抵抗
３０に並列にそれぞれ接続されている。さて以上の回路
においてスイ・ソチング回路３１．３２．３３の開閉を
様々に組入合せることにより端子２６と端子２７の間の
抵抗値を様々に変えることができる。表１はスイッチン
グ回路３１゜ ５−
３２．３３の開閉の組み合せと、その場合における端子
２６と端子２７の間の抵抗値の関係を図示したものであ
る。31, 32, 33u switching circuit. The switching circuit 61 is connected in parallel to the resistor 28, and the switching circuit 3
Two resistors 29Vc are connected in parallel, and the switching circuit 33 is connected in parallel to the resistor 30. Now, in the above circuit, the resistance value between the terminal 26 and the terminal 27 can be varied by various combinations of opening and closing of the switching circuits 31, 32, and 33. Table 1 illustrates the combinations of opening and closing of the switching circuit 31.degree.
表１
表１を見ればわかる様にスイッチング回路３１゜３２．
３３の開閉を適当に選択することにより端子２６と端子
２７の間の抵抗値として０．Ｒ，２Ｒ。Table 1 As you can see from Table 1, the switching circuit 31°32.
By appropriately selecting the opening and closing of 33, the resistance value between the terminals 26 and 27 can be set to 0. R, 2R.
３Ｒ，４Ｆ、５Ｒ，６Ｒ，７ＦＴのＲずつ異なった値を
８種類、かつもれなく設定できることが分る。It can be seen that eight different values of R, 3R, 4F, 5R, 6R, and 7FT, can be set without omission.
６−
こｈは一般に２進法ですべての自然数を連続的１て表わ
すことができるので、Ｎ個の抵抗を２°：２１：２２：
・・・・・・２Ｎ−１の比で構成すれば基本単位の抵抗
値をＲとして０から（２Ｎ−１）・ＦまでＲごとに連続
して２Ｎ個の抵抗値が選べることに起因している。6- Since all natural numbers can generally be expressed as consecutive 1s in binary system, N resistors can be expressed as 2°:21:22:
...This is due to the fact that if it is configured with a ratio of 2N-1, 2N resistance values can be selected consecutively for each R from 0 to (2N-1)・F, with the basic unit resistance value being R. ing.
第４図は本発明の第２の実施例である。第４図は埴５図
の回路に更に抵抗とスイッチング回路をそねそれ１個ず
つ増やした回路である。第４図において５６．３７．３
８．３９ は抵抗であり、それぞれの抵抗値の比け１
：２：４：８となっている。FIG. 4 shows a second embodiment of the invention. Figure 4 is a circuit in which one additional resistor and one switching circuit are added to the circuit shown in Figure 5. 56.37.3 in Figure 4
8.39 is the resistance, and the comparison of each resistance value is 1
:2:4:8.
つまり抵抗６６の抵抗値をＦとすれば抵抗６７゜３８．
３９の抵抗値はそれぞれ２Ｒ，４Ｒ，８Ｒである。抵抗
５６，３７，３８．３９Ｂ直列ｖｃ 、ｆＩ続されてい
る。４０，４１，４２，４３けスイッチング回路である
、スイッチング回路４０．４１．４２゜４５は抵抗３６
，３７，３８．３９にそれぞれ並列に接続されている。In other words, if the resistance value of the resistor 66 is F, then the resistance is 67°38.
The resistance values of 39 are 2R, 4R, and 8R, respectively. Resistors 56, 37, and 38.39B are connected in series with vc and fI. 40, 41, 42, 43 are switching circuits, switching circuit 40, 41, 42° 45 is a resistor 36
, 37, 38, and 39 are connected in parallel.
以上の回路によってスイッチング回路４０，４１，４２
．４３の開閉の組み合せにより第３図の回路で説明した
同じ原理によ杓０から１５ＲｆｆＲごとＶＣ１６種の抵
抗値を端子３４と端子３５の間に作り出すことができる
。The switching circuits 40, 41, 42 by the above circuit
．． By the combination of opening and closing of 43, resistance values of 16 types of VC can be created between the terminals 34 and 35 for every 0 to 15 RffR according to the same principle as explained in the circuit of FIG.
さて本発明の回路である第４図の回路は抵抗を４個、ス
イッチング回路を４個用いており、従来の回路である筑
１図の回路も抵抗を４個、スイッチング回路を４個用い
ている。したがって第１図と第４図は従来の回路と本発
明の回路の比較として適当であると考えられるが、従来
の回路の第１図の回路は５種の抵抗値しか選択できない
のに対し、本発明の回路の第４図は１６種の抵抗値を選
択できる。一般にＮ個の抵抗とスイッチング回路に対し
、第１図の従来の回路方式では前述したように（Ｎ＋１
） 種類の抵抗値しか得られないが、本発明の回路方式
では２Ｎ種類の抵抗値が得られる。Now, the circuit of Figure 4, which is the circuit of the present invention, uses four resistors and four switching circuits, and the conventional circuit, the circuit of Figure 4, uses four resistors and four switching circuits. There is. Therefore, FIGS. 1 and 4 are considered to be appropriate as a comparison between the conventional circuit and the circuit of the present invention, but whereas the conventional circuit shown in FIG. 1 can only select five resistance values, In the circuit of the present invention shown in FIG. 4, 16 resistance values can be selected. In general, for N resistors and switching circuits, the conventional circuit system shown in Fig. 1 has (N+1
) types of resistance values can be obtained, but with the circuit system of the present invention, 2N types of resistance values can be obtained.
したがってＮの値が大＾〈なればなる程、従来の回路方
式と本発明の回路方式の差は極端にひらく。Therefore, the larger the value of N becomes, the more the difference between the conventional circuit system and the circuit system of the present invention becomes extremely wide.
さて本発明の回路である第３図の回路Ｖｉヌイッチング
回路が３個の組み合せで８種の抵抗値を選択でき、従来
の回路である第２図の回路はやはりスイッチング回路の
３個の糾み合せて８種の抵抗値を選択できる。したがっ
て第２図と第３図は従来の回路と本発明の回路の土較と
１．て適当であると考憂らねるが、第２図と第３図を叶
較すれば−桿して明らかな様に第２図の従来の回路方式
の方がρ線やトランジスタの素子数が圧倒的に多くなり
、かつ回路も複雑である。この素子数差及び複雑差は選
択すべき抵抗値の種類が大きくなればなる程急激に著し
くなる。Now, the circuit Vi switching circuit of FIG. 3, which is the circuit of the present invention, can select eight resistance values by combining three circuits, and the circuit of FIG. A total of eight resistance values can be selected. Therefore, FIGS. 2 and 3 show a comparison between the conventional circuit and the circuit of the present invention. However, if we compare Figures 2 and 3, it becomes clear that the conventional circuit system shown in Figure 2 has a lower ρ line and the number of transistor elements. The number of circuits is overwhelmingly large, and the circuits are also complicated. This difference in the number of elements and the difference in complexity become more significant as the types of resistance values to be selected become larger.
第５図は本発明の第３の実施例である。本発明を第３図
や第４図で説明【７たが第３図や第４図の回路の中のス
イッチング回路は回路の開閉の役目をすればどの様な回
路もｊ、くけ素子で構成１７ても自く、トランジスタで
も良いし、複雑な論理回路で構成１．ても白いし、配線
で接続するか否かでも良いし、ポリシリコンヒユーズの
切断か否かでもＶい。第５図ｉｔ第３図の回路のスイッ
チング回路３１．３２．３３をＭＯ８ＦＦｉＴＶＣよる
トランスミ・ソションゲート４９，５０．５１に置き換
えたものであり、かつトランスミ ・ジョンゲート４９
，５０゜５１の開閉をそれぞれスイ・Ｉチング回路５２
．５３５４によｈ ＋ｖｎｎ ｆ））−Ｖａｓ カ’に
選択スルコトＩｃ ヨｂ ９−
行う方式をとって（ハろ。したがってトランスミッショ
ンゲート４９七スイツチング回路５２の絹み合せでひと
つのスイッチング回路を構成していると卵々せる。同様
にトランスミッションゲート５ｎとスイッチング回路５
３、またトランスミッションゲート５１とスイッチング
回路５４のそれぞれの組み合せがそれぞれひとつのスイ
・ソチング回路とも考えられる。中た第３図の抵抗２８
，２９．３０は第５図の抵抗４６，４７．４８にそれぞ
れ対応している。第５図は第５図の原理的な回路をより
具体的回路に置き換えた回路例であるとともに、従来の
回路である第２図の回路のスイッチング回路２０．２１
．２２と同じ使い方をする回路方式に直したものである
。第２図と第５図を比較しても本発明の回路方式が如何
に素子数が少〈てすむ秀れた回路方式であるかが分る。FIG. 5 shows a third embodiment of the invention. The present invention will be explained with reference to Figs. 3 and 4.[7] However, the switching circuits in the circuits shown in Figs. 17 It can also be made of transistors or a complex logic circuit.1. It's white even when it's connected, it doesn't matter whether it's connected by wiring or not, it doesn't matter whether the polysilicon fuse is cut or not. Fig. 5 It is a circuit in which the switching circuits 31, 32, and 33 of the circuit shown in Fig. 3 are replaced with transmi-solution gates 49, 50, 51 by MO8FFiTVC, and transmi-sion gates 49.
, 50° 51 are opened and closed by switching circuits 52.
．． According to 5354, one switching circuit is constructed by combining the transmission gate 49 and seven switching circuits 52. Similarly, transmission gate 5n and switching circuit 5
3. Also, each combination of the transmission gate 51 and the switching circuit 54 can be considered as one switching circuit. Resistor 28 in Figure 3
, 29.30 correspond to resistors 46, 47.48 in FIG. 5, respectively. FIG. 5 is an example of a circuit in which the principle circuit of FIG. 5 is replaced with a more concrete circuit, and the switching circuit 20.21 of the circuit of FIG. 2, which is a conventional circuit.
．． This is a modified circuit system that can be used in the same way as No. 22. Comparing FIG. 2 and FIG. 5, it can be seen how the circuit system of the present invention is an excellent circuit system that requires a small number of elements.
第６図は本発明の第４の実施例である。第６図は本発明
の回路を集積回路内部と集積回路外部にｈｆｃって構成
１５たものである。第６図において破＠６７Ｆｉ集積回
路内部と外部の境界を示している。FIG. 6 shows a fourth embodiment of the present invention. FIG. 6 shows a configuration 15 in which the circuit of the present invention is arranged as a hfc inside an integrated circuit and outside the integrated circuit. FIG. 6 shows the boundary between the inside and outside of the 67Fi integrated circuit.
１０−
５７．５８．５９は抵抗であり、それぞれの抵抗値の比
け１：２：４となっている。抵抗５７．５８゜５９は直
列に接続され、その両端は端子６９と端子６８になって
いる。６３，６４．６５．６６は端子であり、集積回路
内部と外部の中継点である。10-57, 58, and 59 are resistors, and the ratio of their resistance values is 1:2:4. The resistors 57, 58, and 59 are connected in series, with terminals 69 and 68 at both ends. Terminals 63, 64, 65, and 66 are relay points between the inside and outside of the integrated circuit.
端子６３は端子６９に１端子６４は抵抗５７と５８の接
続点に、端子６５ｄ抵抗５８と５９の接続点に、端子６
６は端子６８Ｖｃそれぞれ接続されている。以上が集積
回路内部に構成されている。６０゜６１．６２はスイッ
チング回路であり、ヌイ・ソチング回路６０け端子６３
と６４の間に、スイッチング回路６１け端子６４と６５
の間に、スイッチング回路６２け端子６５と６６の間に
それぞれ設けられる。以上スイ・ソチング回路６０．６
１．６２は集積回路外部に構成される。したがって第６
図の回路のような場合には集積回路内部には抵抗５７゜
５８．５９と端子６３，６４，６５．６６のみの場合が
ある。Terminal 63 is connected to terminal 69, terminal 64 is connected to the connection point between resistors 57 and 58, terminal 65d is connected to the connection point between resistors 58 and 59, and terminal 64 is connected to the connection point between resistors 58 and 59.
6 are connected to terminals 68Vc, respectively. The above is configured inside the integrated circuit. 60゜61.62 is a switching circuit, which has a 60-pin terminal 63
and 64, switching circuit 61 terminals 64 and 65
In between, a switching circuit 62 is provided between terminals 65 and 66, respectively. Above is the sui-soching circuit 60.6
1.62 is configured external to the integrated circuit. Therefore, the sixth
In the case of the circuit shown in the figure, there may be only a resistor 57.degree. 58.59 and terminals 63, 64, 65.66 inside the integrated circuit.
以上、本発明は（Ｎ＋１ ）個の抵抗をそれぞれ２°：
２’ ： ２２ Ｉ＋・・・・・・・・：２Ｎの抵抗
値に設定し、それぞれの抵抗の両端を開閉する（Ｎ＋１
）個のスイッチング回路を設ける回路を構成することに
より少ないビ・ト数の調整で、かつ少ない素子数の回路
で多種の抵抗値を順にもれなく選択できる回路を提供す
るものである。As described above, the present invention provides (N+1) resistors each at 2°:
2': 22 I+...: Set the resistance value to 2N, and open and close both ends of each resistor (N+1
) By configuring a circuit in which switching circuits are provided, a circuit with a small number of bits can be adjusted, and a wide variety of resistance values can be selected without exception using a circuit with a small number of elements.
第１図、第２図は従来の回路例を示す図、第３図は本発
明の実施例を示す回路図、第４図、第５図、第６図は本
発明の実施例を示す回路図である。
１、２．１１．１２．２６．２７．３４．３５．４４，
４５６３、６４．６５．６６、６８．６９・・・・・・
・・端子３、４．５．６．１３．１４．１５．１６．１
７．１８゜１９、２８．２９．３［１，３６，３７，３
８，３９，４６゜４７、４８．５７．５８．５９・・・
・・・・・抵抗７、８．９．１０．２０．２１．２２．
３１．３２．５３゜４０、４１．４２．４３．５２．５
３．５４．６０．６１゜６２・・・・・・・・スイッチ
ング回路２３．５５・・・・・・＋■＊ｒ）
２４、５６−＝−−−Ｖｓｓ
２５・・・・・・デコーダ
４９．５０．５１・・・・・・トランスミ・ソションゲ
ート６７・・・・・・集積回路内部と外部の境界線以
上
出願人 株式会社 諏訪精工台
１３−FIGS. 1 and 2 are diagrams showing conventional circuit examples, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIGS. 4, 5, and 6 are circuit diagrams showing an embodiment of the present invention. It is a diagram. 1, 2.11.12.26.27.34.35.44,
4563, 64.65.66, 68.69...
...Terminal 3, 4.5.6.13.14.15.16.1
7.18°19, 28.29.3[1,36,37,3
8, 39, 46° 47, 48.57.58.59...
...Resistance 7, 8.9.10.20.21.22.
31.32.53゜40, 41.42.43.52.5
3.54.60.61゜62...Switching circuit 23.55...+■*r) 24, 56-=----Vss 25...Decoder 49.50.51...Transmission gate 67...Beyond the boundary between the inside and outside of the integrated circuit
Applicant Suwa Seikodai Co., Ltd. 13-
Claims (2)
” ：・・・・・・・・＝２Ｎの比の関係にある（Ｎ＋
１）個の抵抗と、前記（Ｎ＋１）個の抵抗のそれぞれの
両端を開閉できる（Ｎ＋１）個のスイ・ソチング回路か
らなることを特徴と干る抵抗値調整回路。(1) Each resistance value is 1:2:2 where N is a natural number
” :・・・・・・・・・=2N ratio (N+
1) A resistance value adjustment circuit comprising: (N+1) resistors and (N+1) switching circuits that can open and close both ends of each of the (N+1) resistors.
積回路に内蔵されたことｊ−特徴とする特許請求の範囲
第１項記載の抵抗値調整回路。(2) The resistance value adjusting circuit according to claim 1, characterized in that the front HE' resistor and the switching circuit are built into an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3947883A JPS59165509A (en) | 1983-03-10 | 1983-03-10 | Control circuit of resistance value |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3947883A JPS59165509A (en) | 1983-03-10 | 1983-03-10 | Control circuit of resistance value |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165509A true JPS59165509A (en) | 1984-09-18 |
Family
ID=12554168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3947883A Pending JPS59165509A (en) | 1983-03-10 | 1983-03-10 | Control circuit of resistance value |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165509A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117885U (en) * | 1986-01-16 | 1987-07-27 | ||
| FR2641131A1 (en) * | 1988-12-28 | 1990-06-29 | Alcatel Transmission | Power attenuator for microwaves |
| US6407627B1 (en) | 2001-02-07 | 2002-06-18 | National Semiconductor Corporation | Tunable sallen-key filter circuit assembly and method |
| CN103731119A (en) * | 2012-10-16 | 2014-04-16 | 飞思卡尔半导体公司 | Electronic circuits with variable attenuators and methods of their operation |
| US10432148B2 (en) | 2012-01-27 | 2019-10-01 | Nxp Usa, Inc. | Phase shift and attenuation circuits for use with multiple-path amplifiers |
| CN110380731A (en) * | 2019-07-25 | 2019-10-25 | 上海类比半导体技术有限公司 | A kind of D/A conversion circuit |
| CN110380692A (en) * | 2019-06-28 | 2019-10-25 | 上海类比半导体技术有限公司 | A kind of difference amplifier trims circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152948A (en) * | 1978-05-24 | 1979-12-01 | Seiko Epson Corp | Variable resistor |
-
1983
- 1983-03-10 JP JP3947883A patent/JPS59165509A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152948A (en) * | 1978-05-24 | 1979-12-01 | Seiko Epson Corp | Variable resistor |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117885U (en) * | 1986-01-16 | 1987-07-27 | ||
| FR2641131A1 (en) * | 1988-12-28 | 1990-06-29 | Alcatel Transmission | Power attenuator for microwaves |
| US6407627B1 (en) | 2001-02-07 | 2002-06-18 | National Semiconductor Corporation | Tunable sallen-key filter circuit assembly and method |
| US10432148B2 (en) | 2012-01-27 | 2019-10-01 | Nxp Usa, Inc. | Phase shift and attenuation circuits for use with multiple-path amplifiers |
| CN103731119A (en) * | 2012-10-16 | 2014-04-16 | 飞思卡尔半导体公司 | Electronic circuits with variable attenuators and methods of their operation |
| JP2014082755A (en) * | 2012-10-16 | 2014-05-08 | Freescale Semiconductor Inc | Electronic circuits with variable attenuators and methods of their operation |
| CN110380692A (en) * | 2019-06-28 | 2019-10-25 | 上海类比半导体技术有限公司 | A kind of difference amplifier trims circuit |
| CN110380692B (en) * | 2019-06-28 | 2020-11-24 | 上海类比半导体技术有限公司 | Trimming circuit of differential amplifier |
| US12143071B2 (en) | 2019-06-28 | 2024-11-12 | Shanghai Analogy Semiconductor Technology Ltd. | Trimming circuit of differential amplifier |
| CN110380731A (en) * | 2019-07-25 | 2019-10-25 | 上海类比半导体技术有限公司 | A kind of D/A conversion circuit |
| US11838031B2 (en) | 2019-07-25 | 2023-12-05 | Shanghai Analogy Semiconductor Technology Ltd. | Digital-to-analog conversion circuit |
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